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redbear |
/*
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define __RW_MGR_ac_mrs1 0x04
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#define __RW_MGR_ac_mrs3 0x06
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#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
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#define __RW_MGR_ac_act_1 0x11
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#define __RW_MGR_ac_write_postdata 0x1A
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#define __RW_MGR_ac_act_0 0x10
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#define __RW_MGR_ac_des 0x0D
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#define __RW_MGR_ac_init_reset_1_cke_0 0x01
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#define __RW_MGR_ac_write_data 0x19
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#define __RW_MGR_ac_init_reset_0_cke_0 0x00
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#define __RW_MGR_ac_read_bank_0_1_norden 0x22
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#define __RW_MGR_ac_pre_all 0x12
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#define __RW_MGR_ac_mrs0_user 0x02
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#define __RW_MGR_ac_mrs0_dll_reset 0x03
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#define __RW_MGR_ac_read_bank_0_0 0x1D
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#define __RW_MGR_ac_write_bank_0_col_1 0x16
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#define __RW_MGR_ac_read_bank_0_1 0x1F
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#define __RW_MGR_ac_write_bank_1_col_0 0x15
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#define __RW_MGR_ac_write_bank_1_col_1 0x17
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#define __RW_MGR_ac_write_bank_0_col_0 0x14
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#define __RW_MGR_ac_read_bank_1_0 0x1E
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#define __RW_MGR_ac_mrs1_mirr 0x0A
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#define __RW_MGR_ac_read_bank_1_1 0x20
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#define __RW_MGR_ac_des_odt_1 0x0E
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#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
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#define __RW_MGR_ac_zqcl 0x07
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#define __RW_MGR_ac_write_predata 0x18
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#define __RW_MGR_ac_mrs0_user_mirr 0x08
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#define __RW_MGR_ac_ref 0x13
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#define __RW_MGR_ac_nop 0x0F
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#define __RW_MGR_ac_rdimm 0x23
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#define __RW_MGR_ac_mrs2_mirr 0x0B
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#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
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#define __RW_MGR_ac_read_en 0x21
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#define __RW_MGR_ac_mrs3_mirr 0x0C
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#define __RW_MGR_ac_mrs2 0x05
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#define __RW_MGR_CONTENT_ac_mrs1 0x10090000
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#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
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#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
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#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
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#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
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#define __RW_MGR_CONTENT_ac_act_0 0x10680000
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#define __RW_MGR_CONTENT_ac_des 0x30780000
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#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
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#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
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#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
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#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
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#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
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#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080231
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#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080330
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#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
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#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
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#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
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#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
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#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
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#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
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#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
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#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0000
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#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
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#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
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#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100802C8
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#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
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#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
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#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080249
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#define __RW_MGR_CONTENT_ac_ref 0x10480000
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#define __RW_MGR_CONTENT_ac_nop 0x30780000
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#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
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#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090010
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#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
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#define __RW_MGR_CONTENT_ac_read_en 0x33780000
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#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
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#define __RW_MGR_CONTENT_ac_mrs2 0x100A0008
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/*
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define __RW_MGR_READ_B2B_WAIT2 0x6B
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#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
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#define __RW_MGR_REFRESH_ALL 0x14
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#define __RW_MGR_ZQCL 0x06
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#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
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#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
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#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
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#define __RW_MGR_MRS2_MIRR 0x0A
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#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
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#define __RW_MGR_ACTIVATE_1 0x0F
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#define __RW_MGR_MRS2 0x04
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
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#define __RW_MGR_MRS1 0x03
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#define __RW_MGR_IDLE_LOOP1 0x7B
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#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
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#define __RW_MGR_MRS3 0x05
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#define __RW_MGR_IDLE_LOOP2 0x7A
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#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
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#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
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#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
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#define __RW_MGR_RDIMM_CMD 0x79
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
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#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
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#define __RW_MGR_GUARANTEED_READ_CONT 0x54
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#define __RW_MGR_REFRESH_DELAY 0x15
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#define __RW_MGR_MRS3_MIRR 0x0B
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#define __RW_MGR_IDLE 0x00
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#define __RW_MGR_READ_B2B 0x59
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
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#define __RW_MGR_GUARANTEED_WRITE 0x18
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#define __RW_MGR_PRECHARGE_ALL 0x12
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#define __RW_MGR_SGLE_READ 0x7D
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#define __RW_MGR_MRS0_USER_MIRR 0x0C
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#define __RW_MGR_RETURN 0x01
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#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
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#define __RW_MGR_MRS0_USER 0x07
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#define __RW_MGR_GUARANTEED_READ 0x4C
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#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
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#define __RW_MGR_INIT_RESET_1_CKE_0 0x74
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#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
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#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
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#define __RW_MGR_MRS0_DLL_RESET 0x02
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#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
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#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22
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#define __RW_MGR_CLEAR_DQS_ENABLE 0x49
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#define __RW_MGR_MRS1_MIRR 0x09
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#define __RW_MGR_READ_B2B_WAIT1 0x61
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#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
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#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
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#define __RW_MGR_CONTENT_ZQCL 0x008380
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
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#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
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#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
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#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
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#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
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#define __RW_MGR_CONTENT_MRS2 0x008280
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
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#define __RW_MGR_CONTENT_MRS1 0x008200
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#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
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#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
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#define __RW_MGR_CONTENT_MRS3 0x008300
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#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
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#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
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#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
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#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
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#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
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#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
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#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680
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#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
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#define __RW_MGR_CONTENT_IDLE 0x080000
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#define __RW_MGR_CONTENT_READ_B2B 0x040E88
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
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#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
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#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
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#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
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#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
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#define __RW_MGR_CONTENT_RETURN 0x080680
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#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
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#define __RW_MGR_CONTENT_MRS0_USER 0x008100
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#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
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#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
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#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
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#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
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#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
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#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
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#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
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#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
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#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
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#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
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