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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.sta.rpt] - Blame information for rev 40

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Line No.	Rev	Author	Line
1	32	redbear	`TimeQuest Timing Analyzer report for spw_fifo_ulight`
2	40	redbear	`Mon Feb 5 00:59:04 2018`
3			`Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition`
4	32	redbear
5
6			`---------------------`
7			`; Table of Contents ;`
8			`---------------------`
9			`1. Legal Notice`
10			`2. TimeQuest Timing Analyzer Summary`
11			`3. Parallel Compilation`
12			`4. SDC File List`
13			`5. Clocks`
14			`6. Slow 1100mV 85C Model Fmax Summary`
15			`7. Timing Closure Recommendations`
16			`8. Slow 1100mV 85C Model Setup Summary`
17			`9. Slow 1100mV 85C Model Hold Summary`
18			`10. Slow 1100mV 85C Model Recovery Summary`
19			`11. Slow 1100mV 85C Model Removal Summary`
20			`12. Slow 1100mV 85C Model Minimum Pulse Width Summary`
21			`13. Slow 1100mV 85C Model Metastability Summary`
22			`14. Slow 1100mV 0C Model Fmax Summary`
23			`15. Slow 1100mV 0C Model Setup Summary`
24			`16. Slow 1100mV 0C Model Hold Summary`
25			`17. Slow 1100mV 0C Model Recovery Summary`
26			`18. Slow 1100mV 0C Model Removal Summary`
27			`19. Slow 1100mV 0C Model Minimum Pulse Width Summary`
28			`20. Slow 1100mV 0C Model Metastability Summary`
29			`21. Fast 1100mV 85C Model Setup Summary`
30			`22. Fast 1100mV 85C Model Hold Summary`
31			`23. Fast 1100mV 85C Model Recovery Summary`
32			`24. Fast 1100mV 85C Model Removal Summary`
33			`25. Fast 1100mV 85C Model Minimum Pulse Width Summary`
34			`26. Fast 1100mV 85C Model Metastability Summary`
35			`27. Fast 1100mV 0C Model Setup Summary`
36			`28. Fast 1100mV 0C Model Hold Summary`
37			`29. Fast 1100mV 0C Model Recovery Summary`
38			`30. Fast 1100mV 0C Model Removal Summary`
39			`31. Fast 1100mV 0C Model Minimum Pulse Width Summary`
40			`32. Fast 1100mV 0C Model Metastability Summary`
41			`33. Multicorner Timing Analysis Summary`
42			`34. Board Trace Model Assignments`
43			`35. Input Transition Times`
44			`36. Signal Integrity Metrics (Slow 1100mv 0c Model)`
45			`37. Signal Integrity Metrics (Slow 1100mv 85c Model)`
46			`38. Signal Integrity Metrics (Fast 1100mv 0c Model)`
47			`39. Signal Integrity Metrics (Fast 1100mv 85c Model)`
48			`40. Setup Transfers`
49			`41. Hold Transfers`
50			`42. Recovery Transfers`
51			`43. Removal Transfers`
52			`44. Report TCCS`
53			`45. Report RSKM`
54			`46. Unconstrained Paths Summary`
55			`47. Clock Status Summary`
56			`48. Unconstrained Input Ports`
57			`49. Unconstrained Output Ports`
58			`50. Unconstrained Input Ports`
59			`51. Unconstrained Output Ports`
60			`52. TimeQuest Timing Analyzer Messages`
61
62
63
64			`----------------`
65			`; Legal Notice ;`
66			`----------------`
67			`Copyright (C) 2017 Intel Corporation. All rights reserved.`
68			`Your use of Intel Corporation's design tools, logic functions`
69			`and other software and tools, and its AMPP partner logic`
70			`functions, and any output files from any of the foregoing`
71			`(including device programming or simulation files), and any`
72			`associated documentation or information are expressly subject`
73			`to the terms and conditions of the Intel Program License`
74			`Subscription Agreement, the Intel Quartus Prime License Agreement,`
75	40	redbear	`the Intel FPGA IP License Agreement, or other applicable license`
76			`agreement, including, without limitation, that your use is for`
77			`the sole purpose of programming logic devices manufactured by`
78			`Intel and sold by Intel or its authorized distributors. Please`
79			`refer to the applicable agreement for further details.`
80	32	redbear
81
82
83	40	redbear	`+--------------------------------------------------------------------------------------+`
84			`; TimeQuest Timing Analyzer Summary ;`
85			`+-----------------------+--------------------------------------------------------------+`
86			`; Quartus Prime Version ; Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;`
87			`; Timing Analyzer ; TimeQuest ;`
88			`; Revision Name ; spw_fifo_ulight ;`
89			`; Device Family ; Cyclone V ;`
90			`; Device Name ; 5CSEMA4U23C6 ;`
91			`; Timing Models ; Final ;`
92			`; Delay Model ; Combined ;`
93			`; Rise/Fall Delays ; Enabled ;`
94			`+-----------------------+--------------------------------------------------------------+`
95	32	redbear
96
97			`+------------------------------------------+`
98			`; Parallel Compilation ;`
99			`+----------------------------+-------------+`
100			`; Processors ; Number ;`
101			`+----------------------------+-------------+`
102			`; Number detected on machine ; 4 ;`
103			`; Maximum allowed ; 2 ;`
104			`; ; ;`
105	40	redbear	`; Average used ; 1.17 ;`
106	32	redbear	`; Maximum used ; 2 ;`
107			`; ; ;`
108			`; Usage by Processor ; % Time Used ;`
109			`; Processor 1 ; 100.0% ;`
110	40	redbear	`; Processor 2 ; 17.2% ;`
111	32	redbear	`+----------------------------+-------------+`
112
113
114			`+--------------------------------------------------------------------------------------------------+`
115			`; SDC File List ;`
116			`+--------------------------------------------------------------+--------+--------------------------+`
117			`; SDC File Path ; Status ; Read at ;`
118			`+--------------------------------------------------------------+--------+--------------------------+`
119	40	redbear	`; sdc/spw_fifo_ulight.out.sdc ; OK ; Mon Feb 5 00:57:55 2018 ;`
120			`; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Mon Feb 5 00:57:55 2018 ;`
121	32	redbear	`+--------------------------------------------------------------+--------+--------------------------+`
122
123
124	40	redbear	`+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
125			`; Clocks ;`
126			`+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+`
127			`; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;`
128			`+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+`
129			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i } ;`
130			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; Base ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i } ;`
131			`; din_a ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { din_a } ;`
132			`; FPGA_CLK1_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ;`
133			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e } ;`
134			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|vco0ph[0] ; { u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk } ;`
135			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 16 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|refclkin ; { u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] } ;`
136			`+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+`
137	32	redbear
138
139	40	redbear	`+----------------------------------------------------------------------------------------------------------------------------------+`
140			`; Slow 1100mV 85C Model Fmax Summary ;`
141			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
142			`; Fmax ; Restricted Fmax ; Clock Name ; Note ;`
143			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
144			`; 82.1 MHz ; 82.1 MHz ; FPGA_CLK1_50 ; ;`
145			`; 123.85 MHz ; 123.85 MHz ; din_a ; ;`
146			`; 127.19 MHz ; 127.19 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; ;`
147			`; 145.58 MHz ; 145.58 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; ;`
148			`; 159.54 MHz ; 159.54 MHz ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; ;`
149			`; 201.09 MHz ; 201.09 MHz ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; ;`
150			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
151	32	redbear	This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
152
153
154			`----------------------------------`
155			`; Timing Closure Recommendations ;`
156			`----------------------------------`
157			`HTML report is unavailable in plain text report export.`
158
159
160	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
161			`; Slow 1100mV 85C Model Setup Summary ;`
162			`+--------------------------------------------------------------------------------------------+--------+---------------+`
163			`; Clock ; Slack ; End Point TNS ;`
164			`+--------------------------------------------------------------------------------------------+--------+---------------+`
165			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -4.369 ; -113.702 ;`
166			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -3.697 ; -1112.931 ;`
167			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -3.138 ; -13.527 ;`
168			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -2.473 ; -27.460 ;`
169			`; din_a ; -2.037 ; -45.867 ;`
170			`; FPGA_CLK1_50 ; -1.110 ; -2.017 ;`
171			`+--------------------------------------------------------------------------------------------+--------+---------------+`
172	32	redbear
173
174	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
175			`; Slow 1100mV 85C Model Hold Summary ;`
176			`+--------------------------------------------------------------------------------------------+-------+---------------+`
177			`; Clock ; Slack ; End Point TNS ;`
178			`+--------------------------------------------------------------------------------------------+-------+---------------+`
179			`; FPGA_CLK1_50 ; 0.322 ; 0.000 ;`
180			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.336 ; 0.000 ;`
181			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.393 ; 0.000 ;`
182			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.470 ; 0.000 ;`
183			`; din_a ; 0.547 ; 0.000 ;`
184			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.624 ; 0.000 ;`
185			`+--------------------------------------------------------------------------------------------+-------+---------------+`
186	32	redbear
187
188	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
189			`; Slow 1100mV 85C Model Recovery Summary ;`
190			`+--------------------------------------------------------------------------------------------+--------+---------------+`
191			`; Clock ; Slack ; End Point TNS ;`
192			`+--------------------------------------------------------------------------------------------+--------+---------------+`
193			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -0.289 ; -4.795 ;`
194			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 5.248 ; 0.000 ;`
195			`; FPGA_CLK1_50 ; 14.466 ; 0.000 ;`
196			`+--------------------------------------------------------------------------------------------+--------+---------------+`
197	32	redbear
198
199	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
200			`; Slow 1100mV 85C Model Removal Summary ;`
201			`+--------------------------------------------------------------------------------------------+-------+---------------+`
202			`; Clock ; Slack ; End Point TNS ;`
203			`+--------------------------------------------------------------------------------------------+-------+---------------+`
204			`; FPGA_CLK1_50 ; 0.563 ; 0.000 ;`
205			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.308 ; 0.000 ;`
206			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.746 ; 0.000 ;`
207			`+--------------------------------------------------------------------------------------------+-------+---------------+`
208	32	redbear
209
210	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
211			`; Slow 1100mV 85C Model Minimum Pulse Width Summary ;`
212			`+--------------------------------------------------------------------------------------------+-------+---------------+`
213			`; Clock ; Slack ; End Point TNS ;`
214			`+--------------------------------------------------------------------------------------------+-------+---------------+`
215			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.533 ; 0.000 ;`
216			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.575 ; 0.000 ;`
217			`; din_a ; 0.994 ; 0.000 ;`
218			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
219			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.301 ; 0.000 ;`
220			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 3.952 ; 0.000 ;`
221			`; FPGA_CLK1_50 ; 9.195 ; 0.000 ;`
222			`+--------------------------------------------------------------------------------------------+-------+---------------+`
223	32	redbear
224
225			`-----------------------------------------------`
226			`; Slow 1100mV 85C Model Metastability Summary ;`
227			`-----------------------------------------------`
228			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
229	40	redbear	`Number of Synchronizer Chains Found: 49`
230	32	redbear	`Shortest Synchronizer Chain: 2 Registers`
231			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
232	40	redbear	`Worst Case Available Settling Time: 12.091 ns`
233	32	redbear
234
235
236
237	40	redbear	`+----------------------------------------------------------------------------------------------------------------------------------+`
238			`; Slow 1100mV 0C Model Fmax Summary ;`
239			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
240			`; Fmax ; Restricted Fmax ; Clock Name ; Note ;`
241			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
242			`; 84.77 MHz ; 84.77 MHz ; FPGA_CLK1_50 ; ;`
243			`; 127.58 MHz ; 127.58 MHz ; din_a ; ;`
244			`; 130.77 MHz ; 130.77 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; ;`
245			`; 149.1 MHz ; 149.1 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; ;`
246			`; 159.18 MHz ; 159.18 MHz ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; ;`
247			`; 205.8 MHz ; 205.8 MHz ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; ;`
248			`+------------+-----------------+--------------------------------------------------------------------------------------------+------+`
249	32	redbear	This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
250
251
252	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
253			`; Slow 1100mV 0C Model Setup Summary ;`
254			`+--------------------------------------------------------------------------------------------+--------+---------------+`
255			`; Clock ; Slack ; End Point TNS ;`
256			`+--------------------------------------------------------------------------------------------+--------+---------------+`
257			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -4.207 ; -109.829 ;`
258			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -3.461 ; -1038.103 ;`
259			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -2.976 ; -12.650 ;`
260			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -2.359 ; -27.122 ;`
261			`; din_a ; -1.919 ; -41.436 ;`
262			`; FPGA_CLK1_50 ; -0.765 ; -1.140 ;`
263			`+--------------------------------------------------------------------------------------------+--------+---------------+`
264	32	redbear
265
266	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
267			`; Slow 1100mV 0C Model Hold Summary ;`
268			`+--------------------------------------------------------------------------------------------+-------+---------------+`
269			`; Clock ; Slack ; End Point TNS ;`
270			`+--------------------------------------------------------------------------------------------+-------+---------------+`
271			`; FPGA_CLK1_50 ; 0.211 ; 0.000 ;`
272			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.325 ; 0.000 ;`
273			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.388 ; 0.000 ;`
274			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.478 ; 0.000 ;`
275			`; din_a ; 0.530 ; 0.000 ;`
276			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.599 ; 0.000 ;`
277			`+--------------------------------------------------------------------------------------------+-------+---------------+`
278	32	redbear
279
280	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
281			`; Slow 1100mV 0C Model Recovery Summary ;`
282			`+--------------------------------------------------------------------------------------------+--------+---------------+`
283			`; Clock ; Slack ; End Point TNS ;`
284			`+--------------------------------------------------------------------------------------------+--------+---------------+`
285			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -0.346 ; -5.707 ;`
286			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 5.377 ; 0.000 ;`
287			`; FPGA_CLK1_50 ; 14.772 ; 0.000 ;`
288			`+--------------------------------------------------------------------------------------------+--------+---------------+`
289	32	redbear
290
291	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
292			`; Slow 1100mV 0C Model Removal Summary ;`
293			`+--------------------------------------------------------------------------------------------+-------+---------------+`
294			`; Clock ; Slack ; End Point TNS ;`
295			`+--------------------------------------------------------------------------------------------+-------+---------------+`
296			`; FPGA_CLK1_50 ; 0.464 ; 0.000 ;`
297			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.288 ; 0.000 ;`
298			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.777 ; 0.000 ;`
299			`+--------------------------------------------------------------------------------------------+-------+---------------+`
300	32	redbear
301
302	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
303			`; Slow 1100mV 0C Model Minimum Pulse Width Summary ;`
304			`+--------------------------------------------------------------------------------------------+-------+---------------+`
305			`; Clock ; Slack ; End Point TNS ;`
306			`+--------------------------------------------------------------------------------------------+-------+---------------+`
307			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.499 ; 0.000 ;`
308			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.523 ; 0.000 ;`
309			`; din_a ; 0.986 ; 0.000 ;`
310			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
311			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.324 ; 0.000 ;`
312			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 3.980 ; 0.000 ;`
313			`; FPGA_CLK1_50 ; 9.277 ; 0.000 ;`
314			`+--------------------------------------------------------------------------------------------+-------+---------------+`
315	32	redbear
316
317			`----------------------------------------------`
318			`; Slow 1100mV 0C Model Metastability Summary ;`
319			`----------------------------------------------`
320			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
321	40	redbear	`Number of Synchronizer Chains Found: 49`
322	32	redbear	`Shortest Synchronizer Chain: 2 Registers`
323			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
324	40	redbear	`Worst Case Available Settling Time: 12.233 ns`
325	32	redbear
326
327
328
329	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
330			`; Fast 1100mV 85C Model Setup Summary ;`
331			`+--------------------------------------------------------------------------------------------+--------+---------------+`
332			`; Clock ; Slack ; End Point TNS ;`
333			`+--------------------------------------------------------------------------------------------+--------+---------------+`
334			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -2.086 ; -3.029 ;`
335			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -1.935 ; -13.800 ;`
336			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -1.826 ; -329.386 ;`
337			`; din_a ; -1.068 ; -12.429 ;`
338			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -0.558 ; -5.149 ;`
339			`; FPGA_CLK1_50 ; -0.405 ; -0.405 ;`
340			`+--------------------------------------------------------------------------------------------+--------+---------------+`
341	32	redbear
342
343	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
344			`; Fast 1100mV 85C Model Hold Summary ;`
345			`+--------------------------------------------------------------------------------------------+-------+---------------+`
346			`; Clock ; Slack ; End Point TNS ;`
347			`+--------------------------------------------------------------------------------------------+-------+---------------+`
348			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.122 ; 0.000 ;`
349			`; FPGA_CLK1_50 ; 0.175 ; 0.000 ;`
350			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.179 ; 0.000 ;`
351			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.217 ; 0.000 ;`
352			`; din_a ; 0.242 ; 0.000 ;`
353			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.302 ; 0.000 ;`
354			`+--------------------------------------------------------------------------------------------+-------+---------------+`
355	32	redbear
356
357	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
358			`; Fast 1100mV 85C Model Recovery Summary ;`
359			`+--------------------------------------------------------------------------------------------+--------+---------------+`
360			`; Clock ; Slack ; End Point TNS ;`
361			`+--------------------------------------------------------------------------------------------+--------+---------------+`
362			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.648 ; 0.000 ;`
363			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 6.842 ; 0.000 ;`
364			`; FPGA_CLK1_50 ; 16.136 ; 0.000 ;`
365			`+--------------------------------------------------------------------------------------------+--------+---------------+`
366	32	redbear
367
368	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
369			`; Fast 1100mV 85C Model Removal Summary ;`
370			`+--------------------------------------------------------------------------------------------+-------+---------------+`
371			`; Clock ; Slack ; End Point TNS ;`
372			`+--------------------------------------------------------------------------------------------+-------+---------------+`
373			`; FPGA_CLK1_50 ; 0.424 ; 0.000 ;`
374			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.665 ; 0.000 ;`
375			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.750 ; 0.000 ;`
376			`+--------------------------------------------------------------------------------------------+-------+---------------+`
377	32	redbear
378
379	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
380			`; Fast 1100mV 85C Model Minimum Pulse Width Summary ;`
381			`+--------------------------------------------------------------------------------------------+-------+---------------+`
382			`; Clock ; Slack ; End Point TNS ;`
383			`+--------------------------------------------------------------------------------------------+-------+---------------+`
384			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.732 ; 0.000 ;`
385			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.833 ; 0.000 ;`
386			`; din_a ; 1.215 ; 0.000 ;`
387			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
388			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.480 ; 0.000 ;`
389			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 4.240 ; 0.000 ;`
390			`; FPGA_CLK1_50 ; 9.073 ; 0.000 ;`
391			`+--------------------------------------------------------------------------------------------+-------+---------------+`
392	32	redbear
393
394			`-----------------------------------------------`
395			`; Fast 1100mV 85C Model Metastability Summary ;`
396			`-----------------------------------------------`
397			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
398	40	redbear	`Number of Synchronizer Chains Found: 49`
399	32	redbear	`Shortest Synchronizer Chain: 2 Registers`
400			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
401	40	redbear	`Worst Case Available Settling Time: 14.729 ns`
402	32	redbear
403
404
405
406	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
407			`; Fast 1100mV 0C Model Setup Summary ;`
408			`+--------------------------------------------------------------------------------------------+--------+---------------+`
409			`; Clock ; Slack ; End Point TNS ;`
410			`+--------------------------------------------------------------------------------------------+--------+---------------+`
411			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -1.794 ; -2.071 ;`
412			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -1.717 ; -6.939 ;`
413			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -1.507 ; -230.983 ;`
414			`; din_a ; -0.704 ; -5.641 ;`
415			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -0.395 ; -3.443 ;`
416			`; FPGA_CLK1_50 ; -0.113 ; -0.113 ;`
417			`+--------------------------------------------------------------------------------------------+--------+---------------+`
418	32	redbear
419
420	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
421			`; Fast 1100mV 0C Model Hold Summary ;`
422			`+--------------------------------------------------------------------------------------------+-------+---------------+`
423			`; Clock ; Slack ; End Point TNS ;`
424			`+--------------------------------------------------------------------------------------------+-------+---------------+`
425			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.104 ; 0.000 ;`
426			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.164 ; 0.000 ;`
427			`; FPGA_CLK1_50 ; 0.166 ; 0.000 ;`
428			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.199 ; 0.000 ;`
429			`; din_a ; 0.208 ; 0.000 ;`
430			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.263 ; 0.000 ;`
431			`+--------------------------------------------------------------------------------------------+-------+---------------+`
432	32	redbear
433
434	40	redbear	`+---------------------------------------------------------------------------------------------------------------------+`
435			`; Fast 1100mV 0C Model Recovery Summary ;`
436			`+--------------------------------------------------------------------------------------------+--------+---------------+`
437			`; Clock ; Slack ; End Point TNS ;`
438			`+--------------------------------------------------------------------------------------------+--------+---------------+`
439			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.654 ; 0.000 ;`
440			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 7.148 ; 0.000 ;`
441			`; FPGA_CLK1_50 ; 16.628 ; 0.000 ;`
442			`+--------------------------------------------------------------------------------------------+--------+---------------+`
443	32	redbear
444
445	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
446			`; Fast 1100mV 0C Model Removal Summary ;`
447			`+--------------------------------------------------------------------------------------------+-------+---------------+`
448			`; Clock ; Slack ; End Point TNS ;`
449			`+--------------------------------------------------------------------------------------------+-------+---------------+`
450			`; FPGA_CLK1_50 ; 0.327 ; 0.000 ;`
451			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 0.616 ; 0.000 ;`
452			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 0.684 ; 0.000 ;`
453			`+--------------------------------------------------------------------------------------------+-------+---------------+`
454	32	redbear
455
456	40	redbear	`+--------------------------------------------------------------------------------------------------------------------+`
457			`; Fast 1100mV 0C Model Minimum Pulse Width Summary ;`
458			`+--------------------------------------------------------------------------------------------+-------+---------------+`
459			`; Clock ; Slack ; End Point TNS ;`
460			`+--------------------------------------------------------------------------------------------+-------+---------------+`
461			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.757 ; 0.000 ;`
462			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.823 ; 0.000 ;`
463			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
464			`; din_a ; 1.293 ; 0.000 ;`
465			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1.525 ; 0.000 ;`
466			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 4.335 ; 0.000 ;`
467			`; FPGA_CLK1_50 ; 9.039 ; 0.000 ;`
468			`+--------------------------------------------------------------------------------------------+-------+---------------+`
469	32	redbear
470
471			`----------------------------------------------`
472			`; Fast 1100mV 0C Model Metastability Summary ;`
473			`----------------------------------------------`
474			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
475	40	redbear	`Number of Synchronizer Chains Found: 49`
476	32	redbear	`Shortest Synchronizer Chain: 2 Registers`
477			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
478	40	redbear	`Worst Case Available Settling Time: 15.223 ns`
479	32	redbear
480
481
482
483	40	redbear	`+------------------------------------------------------------------------------------------------------------------------------------------------------------+`
484			`; Multicorner Timing Analysis Summary ;`
485			`+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+`
486			`; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;`
487			`+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+`
488			`; Worst-case Slack ; -4.369 ; 0.104 ; -0.346 ; 0.327 ; 0.499 ;`
489			`; FPGA_CLK1_50 ; -1.110 ; 0.166 ; 14.466 ; 0.327 ; 9.039 ;`
490			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -3.697 ; 0.164 ; 5.248 ; 0.616 ; 3.952 ;`
491			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -4.369 ; 0.104 ; N/A ; N/A ; 0.523 ;`
492			`; din_a ; -2.037 ; 0.208 ; N/A ; N/A ; 0.986 ;`
493			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -3.138 ; 0.263 ; -0.346 ; 0.684 ; 1.301 ;`
494			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -2.473 ; 0.199 ; N/A ; N/A ; 0.499 ;`
495			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ;`
496			`; Design-wide TNS ; -1315.504 ; 0.0 ; -5.707 ; 0.0 ; 0.0 ;`
497			`; FPGA_CLK1_50 ; -2.017 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;`
498			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; -1112.931 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;`
499			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; -113.702 ; 0.000 ; N/A ; N/A ; 0.000 ;`
500			`; din_a ; -45.867 ; 0.000 ; N/A ; N/A ; 0.000 ;`
501			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; -13.527 ; 0.000 ; -5.707 ; 0.000 ; 0.000 ;`
502			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; -27.460 ; 0.000 ; N/A ; N/A ; 0.000 ;`
503			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
504			`+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+`
505	32	redbear
506
507			`+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
508			`; Board Trace Model Assignments ;`
509			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
510			`; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;`
511			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
512	40	redbear	`; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
513			`; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
514	35	redbear	`; dout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
515			`; sout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
516	32	redbear	`; LED[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
517			`; LED[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
518			`; LED[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
519			`; LED[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
520			`; LED[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
521			`; LED[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
522			`; dout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
523			`; sout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
524			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
525
526
527			`+-----------------------------------------------------------------+`
528			`; Input Transition Times ;`
529			`+--------------+--------------+-----------------+-----------------+`
530			`; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;`
531			`+--------------+--------------+-----------------+-----------------+`
532			`; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
533			`; FPGA_CLK1_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
534			`; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
535			`; din_a ; LVDS ; 2000 ps ; 2000 ps ;`
536			`; sin_a ; LVDS ; 2000 ps ; 2000 ps ;`
537			`; din_a(n) ; LVDS ; 2000 ps ; 2000 ps ;`
538			`; sin_a(n) ; LVDS ; 2000 ps ; 2000 ps ;`
539			`+--------------+--------------+-----------------+-----------------+`
540
541
542			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
543			; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
544			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
545			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
546			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
547	40	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
548			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
549	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
550			; sout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
551	32	redbear	; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
552			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
553			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
554			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
555			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
556			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
557			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
558			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
559			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
560
561
562			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
563			; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
564			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
565			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
566			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
567	40	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
568			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
569	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
570			; sout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
571	32	redbear	; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
572			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
573			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
574			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
575			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
576			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
577			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
578			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
579			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
580
581
582			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
583			; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
584			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
585			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
586			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
587	40	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
588			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
589	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
590			; sout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
591	32	redbear	; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
592			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
593			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
594			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
595			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
596			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
597			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
598			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
599			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
600
601
602			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
603			; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
604			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
605			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
606			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
607	40	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
608			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
609	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
610			; sout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
611	32	redbear	; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
612			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
613			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
614			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
615			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
616			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
617			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
618			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
619			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
620
621
622	40	redbear	`+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
623			`; Setup Transfers ;`
624			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
625			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
626			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
627			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ;`
628			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ;`
629			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ;`
630			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
631			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ;`
632			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ;`
633			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
634			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; false path ; 0 ;`
635			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ;`
636			`; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ;`
637			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ;`
638			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ;`
639			`; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ;`
640			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ;`
641			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ;`
642			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1 ; 0 ; 0 ; 0 ;`
643			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 34 ; 15 ; 4 ; 90 ;`
644			`; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 60 ; 0 ; 0 ; 0 ;`
645			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 1600 ; 0 ; 0 ; 0 ;`
646			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
647	32	redbear	`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
648
649
650	40	redbear	`+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
651			`; Hold Transfers ;`
652			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
653			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
654			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
655			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ;`
656			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ;`
657			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ;`
658			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
659			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ;`
660			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ;`
661			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
662			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; false path ; 0 ;`
663			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ;`
664			`; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ;`
665			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ;`
666			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ;`
667			`; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ;`
668			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ;`
669			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ;`
670			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 1 ; 0 ; 0 ; 0 ;`
671			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 34 ; 15 ; 4 ; 90 ;`
672			`; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 60 ; 0 ; 0 ; 0 ;`
673			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 1600 ; 0 ; 0 ; 0 ;`
674			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+`
675	32	redbear	`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
676
677
678	40	redbear	`+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
679			`; Recovery Transfers ;`
680			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
681			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
682			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
683			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ;`
684			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
685			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ;`
686			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ;`
687			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ;`
688			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 20 ; 0 ; 18 ; 0 ;`
689			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
690	32	redbear	`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
691
692
693	40	redbear	`+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
694			`; Removal Transfers ;`
695			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
696			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
697			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
698			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ;`
699			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
700			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ;`
701			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ;`
702			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ;`
703			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; 20 ; 0 ; 18 ; 0 ;`
704			`+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+`
705	32	redbear	`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
706
707
708			`---------------`
709			`; Report TCCS ;`
710			`---------------`
711			`No dedicated SERDES Transmitter circuitry present in device or used in design`
712
713
714			`---------------`
715			`; Report RSKM ;`
716			`---------------`
717			`No non-DPA dedicated SERDES Receiver circuitry present in device or used in design`
718
719
720			`+------------------------------------------------+`
721			`; Unconstrained Paths Summary ;`
722			`+---------------------------------+-------+------+`
723			`; Property ; Setup ; Hold ;`
724			`+---------------------------------+-------+------+`
725			`; Illegal Clocks ; 0 ; 0 ;`
726			`; Unconstrained Clocks ; 0 ; 0 ;`
727			`; Unconstrained Input Ports ; 2 ; 2 ;`
728	40	redbear	`; Unconstrained Input Port Paths ; 34 ; 34 ;`
729	32	redbear	`; Unconstrained Output Ports ; 10 ; 10 ;`
730			`; Unconstrained Output Port Paths ; 10 ; 10 ;`
731			`+---------------------------------+-------+------+`
732
733
734	40	redbear	`+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
735			`; Clock Status Summary ;`
736			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+`
737			`; Target ; Clock ; Type ; Status ;`
738			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+`
739			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ;`
740			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; Base ; Constrained ;`
741			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; Base ; Constrained ;`
742			`; din_a ; din_a ; Base ; Constrained ;`
743			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e ; Base ; Constrained ;`
744			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; Generated ; Constrained ;`
745			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; Generated ; Constrained ;`
746			`+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+`
747	32	redbear
748
749			`+---------------------------------------------------------------------------------------------------+`
750			`; Unconstrained Input Ports ;`
751			`+------------+--------------------------------------------------------------------------------------+`
752			`; Input Port ; Comment ;`
753			`+------------+--------------------------------------------------------------------------------------+`
754			`; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
755			`; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
756			`+------------+--------------------------------------------------------------------------------------+`
757
758
759			`+-----------------------------------------------------------------------------------------------------+`
760			`; Unconstrained Output Ports ;`
761			`+-------------+---------------------------------------------------------------------------------------+`
762			`; Output Port ; Comment ;`
763			`+-------------+---------------------------------------------------------------------------------------+`
764			`; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
765			`; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
766			`; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
767			`; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
768			`; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
769			`; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
770			`; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
771			`; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
772			`; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
773			`; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
774			`+-------------+---------------------------------------------------------------------------------------+`
775
776
777			`+---------------------------------------------------------------------------------------------------+`
778			`; Unconstrained Input Ports ;`
779			`+------------+--------------------------------------------------------------------------------------+`
780			`; Input Port ; Comment ;`
781			`+------------+--------------------------------------------------------------------------------------+`
782			`; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
783			`; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
784			`+------------+--------------------------------------------------------------------------------------+`
785
786
787			`+-----------------------------------------------------------------------------------------------------+`
788			`; Unconstrained Output Ports ;`
789			`+-------------+---------------------------------------------------------------------------------------+`
790			`; Output Port ; Comment ;`
791			`+-------------+---------------------------------------------------------------------------------------+`
792			`; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
793			`; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
794			`; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
795			`; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
796			`; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
797			`; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
798			`; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
799			`; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
800			`; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
801			`; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
802			`+-------------+---------------------------------------------------------------------------------------+`
803
804
805			`+------------------------------------+`
806			`; TimeQuest Timing Analyzer Messages ;`
807			`+------------------------------------+`
808			`Info: *******************************************************************`
809			`Info: Running Quartus Prime TimeQuest Timing Analyzer`
810	40	redbear	`Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition`
811			`Info: Processing started: Mon Feb 5 00:57:45 2018`
812	32	redbear	`Info: Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight`
813	40	redbear	`Info: qsta_default_script.tcl version: #3`
814	32	redbear	`Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.`
815			`Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected`
816			`Info (21077): Low junction temperature is 0 degrees C`
817			`Info (21077): High junction temperature is 85 degrees C`
818			`Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'`
819			`Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'`
820			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
821	40	redbear	`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout`
822			`Info (332098): Cell: m_x\|comb from: dataa to: combout`
823	32	redbear	`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
824			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
825			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
826			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
827			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
828			`Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON`
829			`Info: Analyzing Slow 1100mV 85C Model`
830	40	redbear	`Critical Warning (332148): Timing requirements not met`
831			`Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.`
832			`Info (332146): Worst-case setup slack is -4.369`
833	32	redbear	`Info (332119): Slack End Point TNS Clock`
834			`Info (332119): ========= =================== =====================`
835	40	redbear	`Info (332119): -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
836			`Info (332119): -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
837			`Info (332119): -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
838			`Info (332119): -2.473 -27.460 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
839			`Info (332119): -2.037 -45.867 din_a`
840			`Info (332119): -1.110 -2.017 FPGA_CLK1_50`
841			`Info (332146): Worst-case hold slack is 0.322`
842	32	redbear	`Info (332119): Slack End Point TNS Clock`
843			`Info (332119): ========= =================== =====================`
844	40	redbear	`Info (332119): 0.322 0.000 FPGA_CLK1_50`
845			`Info (332119): 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
846			`Info (332119): 0.393 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
847			`Info (332119): 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
848			`Info (332119): 0.547 0.000 din_a`
849			`Info (332119): 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
850			`Info (332146): Worst-case recovery slack is -0.289`
851	32	redbear	`Info (332119): Slack End Point TNS Clock`
852			`Info (332119): ========= =================== =====================`
853	40	redbear	`Info (332119): -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
854			`Info (332119): 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
855			`Info (332119): 14.466 0.000 FPGA_CLK1_50`
856			`Info (332146): Worst-case removal slack is 0.563`
857	32	redbear	`Info (332119): Slack End Point TNS Clock`
858			`Info (332119): ========= =================== =====================`
859	40	redbear	`Info (332119): 0.563 0.000 FPGA_CLK1_50`
860			`Info (332119): 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
861			`Info (332119): 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
862			`Info (332146): Worst-case minimum pulse width slack is 0.533`
863	32	redbear	`Info (332119): Slack End Point TNS Clock`
864			`Info (332119): ========= =================== =====================`
865	40	redbear	`Info (332119): 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
866			`Info (332119): 0.575 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
867			`Info (332119): 0.994 0.000 din_a`
868	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
869	40	redbear	`Info (332119): 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
870			`Info (332119): 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
871			`Info (332119): 9.195 0.000 FPGA_CLK1_50`
872			`Info (332114): Report Metastability: Found 49 synchronizer chains.`
873	32	redbear	`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
874	40	redbear	`Info (332114): Number of Synchronizer Chains Found: 49`
875	32	redbear	`Info (332114): Shortest Synchronizer Chain: 2 Registers`
876			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
877	40	redbear	`Info (332114): Worst Case Available Settling Time: 12.091 ns`
878	32	redbear	`Info (332114):`
879			`Info: Analyzing Slow 1100mV 0C Model`
880			`Info (334003): Started post-fitting delay annotation`
881			`Info (334004): Delay annotation completed successfully`
882			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
883	40	redbear	`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout`
884			`Info (332098): Cell: m_x\|comb from: dataa to: combout`
885	32	redbear	`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
886			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
887			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
888			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
889			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
890	40	redbear	`Critical Warning (332148): Timing requirements not met`
891			`Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.`
892			`Info (332146): Worst-case setup slack is -4.207`
893	32	redbear	`Info (332119): Slack End Point TNS Clock`
894			`Info (332119): ========= =================== =====================`
895	40	redbear	`Info (332119): -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
896			`Info (332119): -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
897			`Info (332119): -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
898			`Info (332119): -2.359 -27.122 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
899			`Info (332119): -1.919 -41.436 din_a`
900			`Info (332119): -0.765 -1.140 FPGA_CLK1_50`
901			`Info (332146): Worst-case hold slack is 0.211`
902	32	redbear	`Info (332119): Slack End Point TNS Clock`
903			`Info (332119): ========= =================== =====================`
904	40	redbear	`Info (332119): 0.211 0.000 FPGA_CLK1_50`
905			`Info (332119): 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
906			`Info (332119): 0.388 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
907			`Info (332119): 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
908			`Info (332119): 0.530 0.000 din_a`
909			`Info (332119): 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
910			`Info (332146): Worst-case recovery slack is -0.346`
911	32	redbear	`Info (332119): Slack End Point TNS Clock`
912			`Info (332119): ========= =================== =====================`
913	40	redbear	`Info (332119): -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
914			`Info (332119): 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
915			`Info (332119): 14.772 0.000 FPGA_CLK1_50`
916			`Info (332146): Worst-case removal slack is 0.464`
917	32	redbear	`Info (332119): Slack End Point TNS Clock`
918			`Info (332119): ========= =================== =====================`
919	40	redbear	`Info (332119): 0.464 0.000 FPGA_CLK1_50`
920			`Info (332119): 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
921			`Info (332119): 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
922			`Info (332146): Worst-case minimum pulse width slack is 0.499`
923	32	redbear	`Info (332119): Slack End Point TNS Clock`
924			`Info (332119): ========= =================== =====================`
925	40	redbear	`Info (332119): 0.499 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
926			`Info (332119): 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
927			`Info (332119): 0.986 0.000 din_a`
928	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
929	40	redbear	`Info (332119): 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
930			`Info (332119): 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
931			`Info (332119): 9.277 0.000 FPGA_CLK1_50`
932			`Info (332114): Report Metastability: Found 49 synchronizer chains.`
933	32	redbear	`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
934	40	redbear	`Info (332114): Number of Synchronizer Chains Found: 49`
935	32	redbear	`Info (332114): Shortest Synchronizer Chain: 2 Registers`
936			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
937	40	redbear	`Info (332114): Worst Case Available Settling Time: 12.233 ns`
938	32	redbear	`Info (332114):`
939			`Info: Analyzing Fast 1100mV 85C Model`
940			`Info (334003): Started post-fitting delay annotation`
941			`Info (334004): Delay annotation completed successfully`
942			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
943	40	redbear	`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout`
944			`Info (332098): Cell: m_x\|comb from: dataa to: combout`
945	32	redbear	`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
946			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
947			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
948			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
949			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
950	40	redbear	`Critical Warning (332148): Timing requirements not met`
951			`Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.`
952			`Info (332146): Worst-case setup slack is -2.086`
953	32	redbear	`Info (332119): Slack End Point TNS Clock`
954			`Info (332119): ========= =================== =====================`
955	40	redbear	`Info (332119): -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
956			`Info (332119): -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
957			`Info (332119): -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
958			`Info (332119): -1.068 -12.429 din_a`
959			`Info (332119): -0.558 -5.149 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
960			`Info (332119): -0.405 -0.405 FPGA_CLK1_50`
961			`Info (332146): Worst-case hold slack is 0.122`
962	32	redbear	`Info (332119): Slack End Point TNS Clock`
963			`Info (332119): ========= =================== =====================`
964	40	redbear	`Info (332119): 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
965			`Info (332119): 0.175 0.000 FPGA_CLK1_50`
966			`Info (332119): 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
967			`Info (332119): 0.217 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
968			`Info (332119): 0.242 0.000 din_a`
969			`Info (332119): 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
970			`Info (332146): Worst-case recovery slack is 0.648`
971	32	redbear	`Info (332119): Slack End Point TNS Clock`
972			`Info (332119): ========= =================== =====================`
973	40	redbear	`Info (332119): 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
974			`Info (332119): 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
975			`Info (332119): 16.136 0.000 FPGA_CLK1_50`
976			`Info (332146): Worst-case removal slack is 0.424`
977	32	redbear	`Info (332119): Slack End Point TNS Clock`
978			`Info (332119): ========= =================== =====================`
979	40	redbear	`Info (332119): 0.424 0.000 FPGA_CLK1_50`
980			`Info (332119): 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
981			`Info (332119): 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
982			`Info (332146): Worst-case minimum pulse width slack is 0.732`
983	32	redbear	`Info (332119): Slack End Point TNS Clock`
984			`Info (332119): ========= =================== =====================`
985	40	redbear	`Info (332119): 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
986			`Info (332119): 0.833 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
987			`Info (332119): 1.215 0.000 din_a`
988	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
989	40	redbear	`Info (332119): 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
990			`Info (332119): 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
991			`Info (332119): 9.073 0.000 FPGA_CLK1_50`
992			`Info (332114): Report Metastability: Found 49 synchronizer chains.`
993	32	redbear	`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
994	40	redbear	`Info (332114): Number of Synchronizer Chains Found: 49`
995	32	redbear	`Info (332114): Shortest Synchronizer Chain: 2 Registers`
996			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
997	40	redbear	`Info (332114): Worst Case Available Settling Time: 14.729 ns`
998	32	redbear	`Info (332114):`
999			`Info: Analyzing Fast 1100mV 0C Model`
1000			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
1001	40	redbear	`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout`
1002			`Info (332098): Cell: m_x\|comb from: dataa to: combout`
1003	32	redbear	`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
1004			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
1005			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
1006			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
1007			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
1008	40	redbear	`Critical Warning (332148): Timing requirements not met`
1009			`Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.`
1010			`Info (332146): Worst-case setup slack is -1.794`
1011	32	redbear	`Info (332119): Slack End Point TNS Clock`
1012			`Info (332119): ========= =================== =====================`
1013	40	redbear	`Info (332119): -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
1014			`Info (332119): -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
1015			`Info (332119): -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
1016			`Info (332119): -0.704 -5.641 din_a`
1017			`Info (332119): -0.395 -3.443 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
1018			`Info (332119): -0.113 -0.113 FPGA_CLK1_50`
1019			`Info (332146): Worst-case hold slack is 0.104`
1020	32	redbear	`Info (332119): Slack End Point TNS Clock`
1021			`Info (332119): ========= =================== =====================`
1022	40	redbear	`Info (332119): 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
1023			`Info (332119): 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
1024			`Info (332119): 0.166 0.000 FPGA_CLK1_50`
1025			`Info (332119): 0.199 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
1026			`Info (332119): 0.208 0.000 din_a`
1027			`Info (332119): 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
1028			`Info (332146): Worst-case recovery slack is 0.654`
1029	32	redbear	`Info (332119): Slack End Point TNS Clock`
1030			`Info (332119): ========= =================== =====================`
1031	40	redbear	`Info (332119): 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
1032			`Info (332119): 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
1033			`Info (332119): 16.628 0.000 FPGA_CLK1_50`
1034			`Info (332146): Worst-case removal slack is 0.327`
1035	32	redbear	`Info (332119): Slack End Point TNS Clock`
1036			`Info (332119): ========= =================== =====================`
1037	40	redbear	`Info (332119): 0.327 0.000 FPGA_CLK1_50`
1038			`Info (332119): 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
1039			`Info (332119): 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
1040			`Info (332146): Worst-case minimum pulse width slack is 0.757`
1041	32	redbear	`Info (332119): Slack End Point TNS Clock`
1042			`Info (332119): ========= =================== =====================`
1043	40	redbear	`Info (332119): 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
1044			`Info (332119): 0.823 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
1045	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
1046	40	redbear	`Info (332119): 1.293 0.000 din_a`
1047			`Info (332119): 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e`
1048			`Info (332119): 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
1049			`Info (332119): 9.039 0.000 FPGA_CLK1_50`
1050			`Info (332114): Report Metastability: Found 49 synchronizer chains.`
1051	32	redbear	`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
1052	40	redbear	`Info (332114): Number of Synchronizer Chains Found: 49`
1053	32	redbear	`Info (332114): Shortest Synchronizer Chain: 2 Registers`
1054			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
1055	40	redbear	`Info (332114): Worst Case Available Settling Time: 15.223 ns`
1056	32	redbear	`Info (332114):`
1057			`Info (332102): Design is not fully constrained for setup requirements`
1058			`Info (332102): Design is not fully constrained for hold requirements`
1059	40	redbear	`Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings`
1060			`Info: Peak virtual memory: 1444 megabytes`
1061			`Info: Processing ended: Mon Feb 5 00:59:04 2018`
1062			`Info: Elapsed time: 00:01:19`
1063			`Info: Total CPU time (on all processors): 00:01:24`
1064	32	redbear
1065

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