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32 |
redbear |
module SPW_ULIGHT_FIFO(
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input FPGA_CLK1_50,
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input [1:0] KEY,
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input din_a,
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input sin_a,
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//input din_b,
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//input sin_b,
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output dout_a,
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output sout_a,
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//output dout_b,
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//output sout_b,
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//////////// LED ////////////
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/* 3.3-V LVTTL */
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output [7:0] LED
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);
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wire reset_spw_n_b;
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wire top_auto_start;
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wire top_link_start;
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wire top_link_disable;
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wire read_enable_rx;
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wire f_full_rx;
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wire f_empty_rx;
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wire f_empty_tx;
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wire f_full_tx;
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wire [2:0] clock_sel;
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wire [5:0] top_fsm_i;
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wire clk_400_mhz;
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wire clk_pll_mhz;
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wire ppll_100_MHZ;
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wire pll_tx_locked_export;
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wire [8:0] datarx_out_flag;
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wire [13:0] monitor_a;
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wire top_tx_tick;
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wire [7:0] top_tx_time;
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wire [5:0] counter_fifotx;
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wire [5:0] counter_fiforx;
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wire top_tx_write;
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wire [8:0] top_tx_data;
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wire [7:0] time_out;
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wire tick_out;
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40 |
redbear |
wire clk_250_sys;
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redbear |
assign LED[7:7] = pll_tx_locked_export;
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ulight_fifo u0 (
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.auto_start_external_connection_export (top_auto_start), // auto_start_external_connection.export
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.clk_clk (FPGA_CLK1_50), // clk.clk
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.clock_sel_external_connection_export (clock_sel), // clock_sel_external_connection.export
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.data_flag_rx_external_connection_export (datarx_out_flag), // data_flag_rx_external_connection.export
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.data_info_external_connection_export (monitor_a), // data_info_external_connection.export
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.data_read_en_rx_external_connection_export (read_enable_rx), // data_read_en_rx_external_connection.export
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.fifo_empty_rx_status_external_connection_export (f_empty_rx), // fifo_empty_rx_status_external_connection.export
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.fifo_empty_tx_status_external_connection_export (f_empty_tx), // fifo_empty_tx_status_external_connection.export
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.fifo_full_rx_status_external_connection_export (f_full_rx), // fifo_full_rx_status_external_connection.export
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.fifo_full_tx_status_external_connection_export (f_full_tx), // fifo_full_tx_status_external_connection.export
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.led_pio_test_external_connection_export (LED[4:0]), // led_pio_test_external_connection.export
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.link_disable_external_connection_export (top_link_disable), // link_disable_external_connection.export
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.link_start_external_connection_export (top_link_start), // link_start_external_connection.export
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/*
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.memory_mem_a (<connected-to-memory_mem_a>), // memory.mem_a
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.memory_mem_ba (<connected-to-memory_mem_ba>), // .mem_ba
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.memory_mem_ck (<connected-to-memory_mem_ck>), // .mem_ck
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.memory_mem_ck_n (<connected-to-memory_mem_ck_n>), // .mem_ck_n
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.memory_mem_cke (<connected-to-memory_mem_cke>), // .mem_cke
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.memory_mem_cs_n (<connected-to-memory_mem_cs_n>), // .mem_cs_n
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.memory_mem_ras_n (<connected-to-memory_mem_ras_n>), // .mem_ras_n
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.memory_mem_cas_n (<connected-to-memory_mem_cas_n>), // .mem_cas_n
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.memory_mem_we_n (<connected-to-memory_mem_we_n>), // .mem_we_n
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.memory_mem_reset_n (<connected-to-memory_mem_reset_n>), // .mem_reset_n
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.memory_mem_dq (<connected-to-memory_mem_dq>), // .mem_dq
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.memory_mem_dqs (<connected-to-memory_mem_dqs>), // .mem_dqs
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.memory_mem_dqs_n (<connected-to-memory_mem_dqs_n>), // .mem_dqs_n
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.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
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.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
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.memory_oct_rzqin (<connected-to-memory_oct_rzqin>), // .oct_rzqin
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*/
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.pll_0_locked_export (pll_tx_locked_export), // pll_0_locked.export
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40 |
redbear |
.pll_0_outclk0_clk (clk_400_mhz),
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//.pll_0_outclk1_clk (clk_250_sys), // pll_0_outclk0.clk
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32 |
redbear |
.reset_reset_n (reset_spw_n_b), // reset.reset_n
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.timecode_ready_rx_external_connection_export (tick_out), // timecode_ready_rx_external_connection.export
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.timecode_rx_external_connection_export (time_out), // timecode_rx_external_connection.export
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.timecode_tx_data_external_connection_export (top_tx_time), // timecode_tx_data_external_connection.export
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.timecode_tx_enable_external_connection_export (top_tx_tick), // timecode_tx_enable_external_connection.export
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.timecode_tx_ready_external_connection_export (top_tx_ready_tick), // timecode_tx_ready_external_connection.export
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.write_data_fifo_tx_external_connection_export (top_tx_data), // write_data_fifo_tx_external_connection.export
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.write_en_tx_external_connection_export (top_tx_write), // write_en_tx_external_connection.export
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.fsm_info_external_connection_export (top_fsm_i), // fsm_info_external_connection.export
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.counter_tx_fifo_external_connection_export (counter_fifotx), // counter_tx_fifo_external_connection.export
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.counter_rx_fifo_external_connection_export (counter_fiforx) // counter_rx_fifo_external_connection.export
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);
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spw_ulight_con_top_x A_SPW_TOP(
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.ppll_100_MHZ(ppll_100_MHZ),
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.ppllclk(clk_pll_mhz),
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.reset_spw_n_b(reset_spw_n_b),
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40 |
redbear |
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//.clk_sys_250_mhz(clk_250_sys),
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redbear |
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.top_sin(sin_a),
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.top_din(din_a),
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.top_auto_start(top_auto_start),
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.top_link_start(top_link_start),
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.top_link_disable(top_link_disable),
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.top_tx_write(top_tx_write),
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.top_tx_data(top_tx_data),
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.top_tx_tick(top_tx_tick),
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.top_tx_time(top_tx_time),
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.read_rx_fifo_en(read_enable_rx),
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.datarx_flag(datarx_out_flag),
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.tick_out(tick_out),
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.time_out(time_out),
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.top_dout(dout_a),
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.top_sout(sout_a),
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.f_full(f_full_tx),
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.f_empty(f_empty_tx),
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.f_full_rx(f_full_rx),
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.f_empty_rx(f_empty_rx),
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.top_tx_ready_tick(top_tx_ready_tick),
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.top_fsm(top_fsm_i),
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//.data_info(data_a),
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.counter_fifo_tx(counter_fifotx),
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.counter_fifo_rx(counter_fiforx)
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);
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debounce_db db_system_spwulight_b(
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.CLK(FPGA_CLK1_50),
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.PB(KEY[1]),
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.PB_state(reset_spw_n_b),
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.PB_down(LED[5:5])
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);
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clock_reduce R_400_to_2_5_10_100_200_300MHZ(
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.clk(clk_400_mhz),
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.clock_sel(clock_sel),
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.reset_n(pll_tx_locked_export),
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.clk_reduced(clk_pll_mhz),
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.clk_100_reduced(ppll_100_MHZ)
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);
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detector_tokens m_x(
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.rx_din(dout_a),
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.rx_sin(sout_a),
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.rx_resetn(reset_spw_n_b),
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.info(monitor_a)
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);
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endmodule
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