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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_incr_burst_converter.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
4 40 redbear
// files from any of the foregoing (including device programming or simulation
5 32 redbear
// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable
8 32 redbear
// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
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13
 
14 40 redbear
// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $
15 32 redbear
// $Revision: #1 $
16 40 redbear
// $Date: 2017/07/30 $
17 32 redbear
// $Author: swbranch $
18
 
19
// ----------------------------------------------------------
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// This component is used for INCR Avalon slave
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// (slave which only supports INCR) or AXI slave.
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// It converts burst length of input packet
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// to match slave burst.
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// ----------------------------------------------------------
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`timescale 1 ns / 1 ns
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28
module altera_incr_burst_converter
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#(
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  parameter
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    // ----------------------------------------
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    // Burst length Parameters
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    // (real burst length value, not bytecount)
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    // ----------------------------------------
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    MAX_IN_LEN          = 16,
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    MAX_OUT_LEN         = 4,
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    NUM_SYMBOLS         = 4,
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    ADDR_WIDTH          = 12,
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    BNDRY_WIDTH         = 12,
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    BURSTSIZE_WIDTH     = 3,
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    IN_NARROW_SIZE      = 0,
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    PURELY_INCR_AVL_SYS = 0,
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    // ------------------
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    // Derived Parameters
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    // ------------------
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    LEN_WIDTH       = log2ceil(MAX_IN_LEN) + 1,
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    OUT_LEN_WIDTH   = log2ceil(MAX_OUT_LEN) + 1,
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    LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
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)
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(
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    input                               clk,
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    input                               reset,
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    input                               enable,
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    input                               is_write,
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    input [LEN_WIDTH       - 1 : 0]     in_len,
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    input                               in_sop,
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    input [ADDR_WIDTH      - 1 : 0]     in_addr,
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    input [ADDR_WIDTH      - 1 : 0]     in_addr_reg,
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    input [BNDRY_WIDTH     - 1 : 0]     in_burstwrap_reg,
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    input [BURSTSIZE_WIDTH - 1 : 0]     in_size_t,
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    input [BURSTSIZE_WIDTH - 1 : 0]     in_size_reg,
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    // converted output length
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    // out_len         : compressed burst, read
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    // uncompressed_len: uncompressed, write
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    output reg [LEN_WIDTH  - 1 : 0]     out_len,
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    output reg [LEN_WIDTH  - 1 : 0]     uncompr_out_len,
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    // Compressed address output
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    output reg [ADDR_WIDTH - 1 : 0]     out_addr,
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    output reg                          new_burst_export
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);
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75
    // ----------------------------------------
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    // Signals for wrapping support
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    // ----------------------------------------
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    reg [LEN_WIDTH - 1 : 0]        remaining_len;
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    reg [LEN_WIDTH - 1 : 0]        next_out_len;
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    reg [LEN_WIDTH - 1 : 0]        next_rem_len;
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    reg [LEN_WIDTH - 1 : 0]        uncompr_remaining_len;
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    reg [LEN_WIDTH - 1 : 0]        next_uncompr_remaining_len;
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    reg [LEN_WIDTH - 1 : 0]        next_uncompr_rem_len;
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    reg                            new_burst;
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    reg                            uncompr_sub_burst;
86
 
87
    // Avoid QIS warning
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    wire [OUT_LEN_WIDTH - 1 : 0]   max_out_length;
89
    assign max_out_length  = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
90
 
91
    always_comb begin
92
        new_burst_export = new_burst;
93
    end
94
 
95
    // -------------------------------------------
96
    // length remaining calculation
97
    // -------------------------------------------
98
 
99
    always_comb begin : proc_uncompressed_remaining_len
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        if ((in_len <= max_out_length) && is_write) begin
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            uncompr_remaining_len = in_len;
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        end else begin
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            uncompr_remaining_len = max_out_length;
104
        end
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106
        if (uncompr_sub_burst)
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            uncompr_remaining_len = next_uncompr_rem_len;
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    end
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110
    always_ff @(posedge clk, posedge reset) begin
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        if (reset) begin
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            next_uncompr_rem_len  <= 0;
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        end
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        else if (enable) begin
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            next_uncompr_rem_len  <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
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        end
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    end
118
 
119
    always_comb begin : proc_compressed_remaining_len
120
       remaining_len  = in_len;
121
        if (!new_burst)
122
            remaining_len = next_rem_len;
123
    end
124
 
125
    always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len
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        if(reset) begin
127
            next_uncompr_remaining_len <= '0;
128
        end
129
        else if (enable) begin
130
            if (in_sop) begin
131
                next_uncompr_remaining_len <= in_len - max_out_length;
132
            end
133
            else if (!uncompr_sub_burst)
134
                next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
135
        end
136
    end
137
 
138
    always_comb begin
139
        next_out_len = max_out_length;
140
        if (remaining_len < max_out_length) begin
141
            next_out_len = remaining_len;
142
        end
143
    end // always_comb
144
 
145
    // --------------------------------------------------
146
    // Length remaining calculation : compressed
147
    // --------------------------------------------------
148
    // length remaining for compressed transaction
149
    // for wrap, need special handling for first out length
150
 
151
    always_ff @(posedge clk, posedge reset) begin
152
        if (reset)
153
            next_rem_len  <= 0;
154
        else if (enable) begin
155
            if (new_burst)
156
                next_rem_len <= in_len - max_out_length;
157
            else
158
                next_rem_len <= next_rem_len - max_out_length;
159
        end
160
    end
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162
    always_ff @(posedge clk, posedge reset) begin
163
        if (reset) begin
164
            uncompr_sub_burst <= 0;
165
        end
166
        else if (enable && is_write) begin
167
            uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
168
        end
169
    end
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172
    // --------------------------------------------------
173
    // Control signals
174
    // --------------------------------------------------
175
    wire end_compressed_sub_burst;
176
    assign end_compressed_sub_burst  = (remaining_len == next_out_len);
177
 
178
    // new_burst:
179
    //  the converter takes in_len for new calculation
180
    always_ff @(posedge clk, posedge reset) begin
181
        if (reset)
182
            new_burst   <= 1;
183
        else if (enable)
184
            new_burst   <= end_compressed_sub_burst;
185
    end
186
 
187
    // --------------------------------------------------
188
    // Output length
189
    // --------------------------------------------------
190
    // register out_len for compressed trans
191
    always_ff @(posedge clk, posedge reset) begin
192
        if (reset) begin
193
            out_len <= 0;
194
        end
195
        else if (enable) begin
196
            out_len <= next_out_len;
197
        end
198
    end
199
 
200
    // register uncompr_out_len for uncompressed trans
201
    always_ff @(posedge clk, posedge reset) begin
202
        if (reset) begin
203
            uncompr_out_len <= '0;
204
        end
205
        else if (enable) begin
206
            uncompr_out_len <= uncompr_remaining_len;
207
        end
208
    end
209
 
210
    // --------------------------------------------------
211
    // Address Calculation
212
    // --------------------------------------------------
213
    reg [ADDR_WIDTH - 1 : 0]        addr_incr_sel;
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    reg [ADDR_WIDTH - 1 : 0]        addr_incr_sel_reg;
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    reg [ADDR_WIDTH - 1 : 0]        addr_incr_full_size;
216
 
217
    localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
218
 
219
    generate
220
        if (IN_NARROW_SIZE) begin : narrow_addr_incr
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            reg [ADDR_WIDTH - 1 : 0]    addr_incr_variable_size;
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            reg [ADDR_WIDTH - 1 : 0]    addr_incr_variable_size_reg;
223
 
224
            assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
225
            assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
226
 
227
            assign addr_incr_sel  = addr_incr_variable_size;
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            assign addr_incr_sel_reg  = addr_incr_variable_size_reg;
229
        end
230
        else begin : full_addr_incr
231
            assign addr_incr_full_size  = ADDR_INCR[ADDR_WIDTH - 1 : 0];
232
            assign addr_incr_sel  = addr_incr_full_size;
233
            assign addr_incr_sel_reg = addr_incr_full_size;
234
        end
235
    endgenerate
236
 
237
 
238
    reg [ADDR_WIDTH - 1 : 0]    next_out_addr;
239
    reg [ADDR_WIDTH - 1 : 0]    incremented_addr;
240
 
241
    always_ff @(posedge clk, posedge reset) begin
242
        if (reset) begin
243
            out_addr <= '0;
244
        end else begin
245
            if (enable) begin
246
                out_addr <=  (next_out_addr);
247
            end
248
        end
249
    end
250
 
251
    generate
252
        if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
253
            always_ff @(posedge clk, posedge reset) begin
254
                if (reset) begin
255
                    incremented_addr <= '0;
256
                end
257
                else if (enable) begin
258
                    incremented_addr <= (next_out_addr + addr_incr_sel_reg);
259
                    if (new_burst) begin
260
                        incremented_addr <= (next_out_addr + addr_incr_sel);
261
                    end
262
                end
263
            end // always_ff @
264
 
265
            always_comb begin
266
                next_out_addr = in_addr;
267
                if (!new_burst) begin
268
                    next_out_addr = incremented_addr;
269
                end
270
            end
271
        end
272
        else begin : incremented_addr_pure_av
273
            always_ff @(posedge clk, posedge reset) begin
274
            if (reset) begin
275
               incremented_addr <= '0;
276
                end
277
                else if (enable) begin
278
                    incremented_addr <= (next_out_addr + addr_incr_sel_reg);
279
                end
280
            end // always_ff @
281
 
282
            always_comb begin
283
                next_out_addr  = in_addr;
284
                if (!new_burst) begin
285
                    next_out_addr  = (incremented_addr);
286
                end
287
            end
288
 
289
        end
290
    endgenerate
291
 
292
    // --------------------------------------------------
293
    // Calculates the log2ceil of the input value
294
    // --------------------------------------------------
295
    function integer log2ceil;
296
        input integer val;
297
        reg[31:0] i;
298
 
299
        begin
300
            i = 1;
301
            log2ceil = 0;
302
 
303
            while (i < val) begin
304
                log2ceil = log2ceil + 1;
305
                i = i[30:0] << 1;
306
            end
307
        end
308
    endfunction
309
 
310
endmodule

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