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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_mem_if_dll_cyclonev.sv] - Blame information for rev 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
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// ********************************************************************************************************************************
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// This file instantiates the DLL.
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// ********************************************************************************************************************************
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_dll; -name IP_TOOL_VERSION 17.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
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module altera_mem_if_dll_cyclonev (
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        clk,
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    dll_pll_locked,
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        dll_delayctrl
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);
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parameter DLL_DELAY_CTRL_WIDTH  = 0;
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parameter DELAY_BUFFER_MODE = "";
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parameter DELAY_CHAIN_LENGTH = 0;
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parameter DLL_INPUT_FREQUENCY_PS_STR = "";
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parameter DLL_OFFSET_CTRL_WIDTH = 0;
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input                                clk;  // DLL input clock
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input                                dll_pll_locked;
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output  [DLL_DELAY_CTRL_WIDTH-1:0]   dll_delayctrl;
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wire  wire_dll_wys_m_offsetdelayctrlclkout;
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wire  [DLL_DELAY_CTRL_WIDTH-1:0]   wire_dll_wys_m_offsetdelayctrlout;
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wire  dll_aload;
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assign dll_aload = ~dll_pll_locked;
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        cyclonev_dll dll_wys_m(
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                .clk(clk),
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                .aload(dll_aload),
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                .delayctrlout(dll_delayctrl),
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                .dqsupdate(),
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                .locked(),
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                .upndnout(),
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    .dftcore()
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                `ifndef FORMAL_VERIFICATION
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                // synopsys translate_off
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                `endif
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                ,
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                .upndnin(1'b1),
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                .upndninclkena(1'b1)
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                `ifndef FORMAL_VERIFICATION
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                // synopsys translate_on
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                `endif
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                // synopsys translate_off
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                ,
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                .dffin()
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                // synopsys translate_on
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        );
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        defparam dll_wys_m.input_frequency = DLL_INPUT_FREQUENCY_PS_STR;
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        defparam dll_wys_m.jitter_reduction = "true";
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        defparam dll_wys_m.static_delay_ctrl = DELAY_CHAIN_LENGTH;
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        defparam dll_wys_m.lpm_type = "cyclonev_dll";
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endmodule
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