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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *)
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module altera_mem_if_hard_memory_controller_top_cyclonev (
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afi_clk,
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afi_half_clk,
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ctl_clk,
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mp_cmd_clk_0,
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mp_cmd_clk_1,
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mp_cmd_clk_2,
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mp_cmd_clk_3,
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mp_cmd_clk_4,
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mp_cmd_clk_5,
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mp_cmd_reset_n_0,
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mp_cmd_reset_n_1,
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mp_cmd_reset_n_2,
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mp_cmd_reset_n_3,
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mp_cmd_reset_n_4,
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mp_cmd_reset_n_5,
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mp_rfifo_clk_0,
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mp_rfifo_clk_1,
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mp_rfifo_clk_2,
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mp_rfifo_clk_3,
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mp_rfifo_reset_n_0,
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mp_rfifo_reset_n_1,
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mp_rfifo_reset_n_2,
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mp_rfifo_reset_n_3,
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mp_wfifo_clk_0,
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mp_wfifo_clk_1,
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mp_wfifo_clk_2,
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mp_wfifo_clk_3,
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mp_wfifo_reset_n_0,
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mp_wfifo_reset_n_1,
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mp_wfifo_reset_n_2,
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mp_wfifo_reset_n_3,
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csr_clk,
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csr_reset_n,
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afi_reset_n,
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ctl_reset_n,
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avl_ready_0,
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avl_write_req_0,
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avl_read_req_0,
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avl_addr_0,
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avl_be_0,
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avl_wdata_0,
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avl_size_0,
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avl_burstbegin_0,
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avl_rdata_0,
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avl_rdata_valid_0,
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avl_ready_1,
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avl_write_req_1,
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avl_read_req_1,
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avl_addr_1,
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avl_be_1,
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avl_wdata_1,
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avl_size_1,
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avl_burstbegin_1,
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avl_rdata_1,
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avl_rdata_valid_1,
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avl_ready_2,
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avl_write_req_2,
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avl_read_req_2,
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avl_addr_2,
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avl_be_2,
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avl_wdata_2,
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avl_size_2,
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avl_burstbegin_2,
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avl_rdata_2,
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avl_rdata_valid_2,
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avl_ready_3,
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avl_write_req_3,
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avl_read_req_3,
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avl_addr_3,
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avl_be_3,
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avl_wdata_3,
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avl_size_3,
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avl_burstbegin_3,
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avl_rdata_3,
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avl_rdata_valid_3,
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avl_ready_4,
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avl_write_req_4,
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avl_read_req_4,
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avl_addr_4,
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avl_be_4,
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avl_wdata_4,
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avl_size_4,
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avl_burstbegin_4,
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avl_rdata_4,
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avl_rdata_valid_4,
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avl_ready_5,
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avl_write_req_5,
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avl_read_req_5,
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avl_addr_5,
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avl_be_5,
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avl_wdata_5,
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avl_size_5,
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avl_burstbegin_5,
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avl_rdata_5,
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avl_rdata_valid_5,
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afi_rst_n,
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afi_cs_n,
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afi_cke,
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afi_odt,
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afi_addr,
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afi_ba,
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afi_ras_n,
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afi_cas_n,
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afi_we_n,
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afi_dqs_burst,
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afi_wdata_valid,
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afi_wdata,
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afi_dm,
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afi_wlat,
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afi_rdata_en,
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afi_rdata_en_full,
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afi_rdata,
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afi_rdata_valid,
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afi_rlat,
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afi_cal_success,
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afi_mem_clk_disable,
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afi_ctl_refresh_done,
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afi_seq_busy,
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afi_ctl_long_idle,
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afi_cal_fail,
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afi_cal_req,
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afi_init_req,
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cfg_dramconfig,
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cfg_caswrlat,
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cfg_addlat,
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cfg_tcl,
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cfg_trfc,
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cfg_trefi,
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cfg_twr,
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cfg_tmrd,
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cfg_coladdrwidth,
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cfg_rowaddrwidth,
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cfg_bankaddrwidth,
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cfg_csaddrwidth,
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cfg_interfacewidth,
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cfg_devicewidth,
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local_refresh_ack,
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local_powerdn_ack,
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local_self_rfsh_ack,
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local_deep_powerdn_ack,
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local_refresh_req,
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local_refresh_chip,
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local_self_rfsh_req,
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local_self_rfsh_chip,
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local_deep_powerdn_req,
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local_deep_powerdn_chip,
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local_multicast,
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local_priority,
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local_init_done,
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local_cal_success,
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local_cal_fail,
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csr_read_req,
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csr_write_req,
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csr_addr,
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csr_wdata,
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csr_rdata,
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csr_be,
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csr_rdata_valid,
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csr_waitrequest,
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bonding_out_1,
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bonding_in_1,
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bonding_out_2,
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bonding_in_2,
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bonding_out_3,
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bonding_in_3,
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io_intaficalfail,
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ctl_init_req,
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local_sts_ctl_empty,
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io_intaficalsuccess
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);
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//////////////////////////////////////////////////////////////////////////////
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// BEGIN PARAMETER SECTION
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// Existing SIP parameters
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parameter AVL_SIZE_WIDTH = 0;
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parameter AVL_ADDR_WIDTH = 0;
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parameter AVL_DATA_WIDTH = 0;
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parameter MEM_IF_CLK_PAIR_COUNT = 0;
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parameter MEM_IF_CS_WIDTH = 0;
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parameter MEM_IF_DQS_WIDTH = 0;
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parameter MEM_IF_CHIP_BITS = 0;
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parameter AFI_ADDR_WIDTH = 0;
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parameter AFI_BANKADDR_WIDTH = 0;
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parameter AFI_CONTROL_WIDTH = 0;
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parameter AFI_CS_WIDTH = 0;
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parameter AFI_ODT_WIDTH = 0;
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parameter AFI_DM_WIDTH = 0;
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parameter AFI_DQ_WIDTH = 0;
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parameter AFI_WRITE_DQS_WIDTH = 0;
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parameter AFI_RATE_RATIO = 0;
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parameter AFI_WLAT_WIDTH = 0;
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parameter AFI_RLAT_WIDTH = 0;
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parameter CSR_BE_WIDTH = 0;
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parameter CSR_ADDR_WIDTH = 0;
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parameter CSR_DATA_WIDTH = 0;
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// New parameters for HMC
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parameter AVL_DATA_WIDTH_PORT_0 = 0;
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parameter AVL_DATA_WIDTH_PORT_1 = 0;
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parameter AVL_DATA_WIDTH_PORT_2 = 0;
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parameter AVL_DATA_WIDTH_PORT_3 = 0;
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parameter AVL_DATA_WIDTH_PORT_4 = 0;
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parameter AVL_DATA_WIDTH_PORT_5 = 0;
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parameter AVL_ADDR_WIDTH_PORT_0 = 0;
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parameter AVL_ADDR_WIDTH_PORT_1 = 0;
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parameter AVL_ADDR_WIDTH_PORT_2 = 0;
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parameter AVL_ADDR_WIDTH_PORT_3 = 0;
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parameter AVL_ADDR_WIDTH_PORT_4 = 0;
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parameter AVL_ADDR_WIDTH_PORT_5 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_0 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_1 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_2 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_3 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_4 = 0;
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parameter AVL_NUM_SYMBOLS_PORT_5 = 0;
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parameter LSB_WFIFO_PORT_0 = 5;
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parameter MSB_WFIFO_PORT_0 = 5;
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parameter LSB_RFIFO_PORT_0 = 5;
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parameter MSB_RFIFO_PORT_0 = 5;
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parameter LSB_WFIFO_PORT_1 = 5;
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parameter MSB_WFIFO_PORT_1 = 5;
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parameter LSB_RFIFO_PORT_1 = 5;
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parameter MSB_RFIFO_PORT_1 = 5;
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parameter LSB_WFIFO_PORT_2 = 5;
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parameter MSB_WFIFO_PORT_2 = 5;
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parameter LSB_RFIFO_PORT_2 = 5;
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parameter MSB_RFIFO_PORT_2 = 5;
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parameter LSB_WFIFO_PORT_3 = 5;
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parameter MSB_WFIFO_PORT_3 = 5;
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parameter LSB_RFIFO_PORT_3 = 5;
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parameter MSB_RFIFO_PORT_3 = 5;
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parameter LSB_WFIFO_PORT_4 = 5;
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parameter MSB_WFIFO_PORT_4 = 5;
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parameter LSB_RFIFO_PORT_4 = 5;
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parameter MSB_RFIFO_PORT_4 = 5;
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parameter LSB_WFIFO_PORT_5 = 5;
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parameter MSB_WFIFO_PORT_5 = 5;
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parameter LSB_RFIFO_PORT_5 = 5;
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parameter MSB_RFIFO_PORT_5 = 5;
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parameter HARD_PHY = 0;
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// Atom defparam
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// Those that mark with // SYTH & SIM is used to force MMR signals in simulation
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// Those that mark with // SYTH ONLY is only used for Quartus sythesis
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parameter ENUM_ATTR_COUNTER_ONE_RESET = "DISABLED"; //SYTH & SIM
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parameter ENUM_ATTR_COUNTER_ZERO_RESET = "DISABLED"; //SYTH & SIM
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parameter ENUM_ATTR_STATIC_CONFIG_VALID = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_0 = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_1 = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_2 = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_3 = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_4 = "DISABLED"; //SYTH & SIM
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parameter ENUM_AUTO_PCH_ENABLE_5 = "DISABLED"; //SYTH & SIM
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parameter ENUM_CAL_REQ = "DISABLED"; //SYTH & SIM
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parameter ENUM_CFG_BURST_LENGTH = "BL_8"; //SYTH & SIM
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parameter ENUM_CFG_INTERFACE_WIDTH = "DWIDTH_32"; //SYTH & SIM
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parameter ENUM_CFG_SELF_RFSH_EXIT_CYCLES = "SELF_RFSH_EXIT_CYCLES_512"; //SYTH & SIM
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parameter ENUM_CFG_STARVE_LIMIT = "STARVE_LIMIT_32"; //SYTH & SIM
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parameter ENUM_CFG_TYPE = "DDR3"; //SYTH & SIM
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parameter ENUM_CLOCK_OFF_0 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLOCK_OFF_1 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLOCK_OFF_2 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLOCK_OFF_3 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLOCK_OFF_4 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLOCK_OFF_5 = "DISABLED"; //SIM ONLY
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parameter ENUM_CLR_INTR = "NO_CLR_INTR"; //SIM ONLY
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parameter ENUM_CMD_PORT_IN_USE_0 = "FALSE"; //SYTH ONLY
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parameter ENUM_CMD_PORT_IN_USE_1 = "FALSE"; //SYTH ONLY
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parameter ENUM_CMD_PORT_IN_USE_2 = "FALSE"; //SYTH ONLY
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parameter ENUM_CMD_PORT_IN_USE_3 = "FALSE"; //SYTH ONLY
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parameter ENUM_CMD_PORT_IN_USE_4 = "FALSE"; //SYTH ONLY
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parameter ENUM_CMD_PORT_IN_USE_5 = "FALSE"; //SYTH ONLY
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parameter ENUM_CPORT0_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
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parameter ENUM_CPORT0_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT0_TYPE = "DISABLE"; //SYTH & SIM
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parameter ENUM_CPORT0_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT1_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
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parameter ENUM_CPORT1_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT1_TYPE = "DISABLE"; //SYTH & SIM
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parameter ENUM_CPORT1_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT2_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
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parameter ENUM_CPORT2_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT2_TYPE = "DISABLE"; //SYTH & SIM
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parameter ENUM_CPORT2_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
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parameter ENUM_CPORT3_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 305 |
|
|
parameter ENUM_CPORT3_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 306 |
|
|
parameter ENUM_CPORT3_TYPE = "DISABLE"; //SYTH & SIM
|
| 307 |
|
|
parameter ENUM_CPORT3_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 308 |
|
|
parameter ENUM_CPORT4_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 309 |
|
|
parameter ENUM_CPORT4_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 310 |
|
|
parameter ENUM_CPORT4_TYPE = "DISABLE"; //SYTH & SIM
|
| 311 |
|
|
parameter ENUM_CPORT4_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 312 |
|
|
parameter ENUM_CPORT5_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 313 |
|
|
parameter ENUM_CPORT5_RFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 314 |
|
|
parameter ENUM_CPORT5_TYPE = "DISABLE"; //SYTH & SIM
|
| 315 |
|
|
parameter ENUM_CPORT5_WFIFO_MAP = "FIFO_0"; //SYTH & SIM
|
| 316 |
|
|
parameter ENUM_CTL_ADDR_ORDER = "CHIP_BANK_ROW_COL"; //SYTH & SIM
|
| 317 |
|
|
parameter ENUM_CTL_ECC_ENABLED = "CTL_ECC_DISABLED"; //SYTH & SIM
|
| 318 |
|
|
parameter ENUM_CTL_ECC_RMW_ENABLED = "CTL_ECC_RMW_DISABLED"; //SYTH & SIM
|
| 319 |
|
|
parameter ENUM_CTL_REGDIMM_ENABLED = "REGDIMM_DISABLED"; //SIM ONLY
|
| 320 |
|
|
parameter ENUM_CTL_USR_REFRESH = "CTL_USR_REFRESH_DISABLED"; //SYTH & SIM
|
| 321 |
|
|
parameter ENUM_CTRL_WIDTH = "DATA_WIDTH_64_BIT"; //SYTH & SIM
|
| 322 |
|
|
parameter ENUM_DELAY_BONDING = "BONDING_LATENCY_0"; //SYTH & SIM
|
| 323 |
|
|
parameter ENUM_DFX_BYPASS_ENABLE = "DFX_BYPASS_DISABLED"; //SYTH & SIM
|
| 324 |
|
|
parameter ENUM_DISABLE_MERGING = "MERGING_ENABLED"; //SIM ONLY
|
| 325 |
|
|
parameter ENUM_ECC_DQ_WIDTH = "ECC_DQ_WIDTH_0"; //SYTH ONLY
|
| 326 |
|
|
parameter ENUM_ENABLE_ATPG = "DISABLED"; //SYTH & SIM
|
| 327 |
|
|
parameter ENUM_ENABLE_BONDING_0 = "DISABLED"; //SYTH & SIM
|
| 328 |
|
|
parameter ENUM_ENABLE_BONDING_1 = "DISABLED"; //SYTH & SIM
|
| 329 |
|
|
parameter ENUM_ENABLE_BONDING_2 = "DISABLED"; //SYTH & SIM
|
| 330 |
|
|
parameter ENUM_ENABLE_BONDING_3 = "DISABLED"; //SYTH & SIM
|
| 331 |
|
|
parameter ENUM_ENABLE_BONDING_4 = "DISABLED"; //SYTH & SIM
|
| 332 |
|
|
parameter ENUM_ENABLE_BONDING_5 = "DISABLED"; //SYTH & SIM
|
| 333 |
|
|
parameter ENUM_ENABLE_BONDING_WRAPBACK = "DISABLED"; //SYTH & SIM
|
| 334 |
|
|
parameter ENUM_ENABLE_DQS_TRACKING = "DISABLED"; //SYTH & SIM
|
| 335 |
|
|
parameter ENUM_ENABLE_ECC_CODE_OVERWRITES = "DISABLED"; //SYTH & SIM
|
| 336 |
|
|
parameter ENUM_ENABLE_FAST_EXIT_PPD = "DISABLED"; //SYTH ONLY
|
| 337 |
|
|
parameter ENUM_ENABLE_INTR = "DISABLED"; //SYTH & SIM
|
| 338 |
|
|
parameter ENUM_ENABLE_NO_DM = "DISABLED"; //SYTH & SIM
|
| 339 |
|
|
parameter ENUM_ENABLE_PIPELINEGLOBAL = "DISABLED"; //SYTH & SIM
|
| 340 |
|
|
parameter ENUM_GANGED_ARF = "DISABLED"; //SIM ONLY
|
| 341 |
|
|
parameter ENUM_GEN_DBE = "GEN_DBE_DISABLED"; //SIM ONLY
|
| 342 |
|
|
parameter ENUM_GEN_SBE = "GEN_SBE_DISABLED"; //SIM ONLY
|
| 343 |
|
|
parameter ENUM_INC_SYNC = "FIFO_SET_2"; //SYTH & SIM
|
| 344 |
|
|
parameter ENUM_LOCAL_IF_CS_WIDTH = "ADDR_WIDTH_2"; //SYTH & SIM
|
| 345 |
|
|
parameter ENUM_MASK_CORR_DROPPED_INTR = "DISABLED"; //SYTH & SIM
|
| 346 |
|
|
parameter ENUM_MASK_DBE_INTR = "DISABLED"; //SYTH & SIM
|
| 347 |
|
|
parameter ENUM_MASK_SBE_INTR = "DISABLED"; //SYTH & SIM
|
| 348 |
|
|
parameter ENUM_MEM_IF_AL = "AL_0"; //SYTH & SIM
|
| 349 |
|
|
parameter ENUM_MEM_IF_BANKADDR_WIDTH = "ADDR_WIDTH_3"; //SYTH & SIM
|
| 350 |
|
|
parameter ENUM_MEM_IF_BURSTLENGTH = "MEM_IF_BURSTLENGTH_8"; //SYTH ONLY
|
| 351 |
|
|
parameter ENUM_MEM_IF_COLADDR_WIDTH = "ADDR_WIDTH_12"; //SYTH & SIM
|
| 352 |
|
|
parameter ENUM_MEM_IF_CS_PER_RANK = "MEM_IF_CS_PER_RANK_1"; //SYTH ONLY
|
| 353 |
|
|
parameter ENUM_MEM_IF_CS_WIDTH = "MEM_IF_CS_WIDTH_1"; //SYTH ONLY
|
| 354 |
|
|
parameter ENUM_MEM_IF_DQ_PER_CHIP = "MEM_IF_DQ_PER_CHIP_8"; //SYTH ONLY
|
| 355 |
|
|
parameter ENUM_MEM_IF_DQS_WIDTH = "DQS_WIDTH_4"; //SYTH & SIM
|
| 356 |
|
|
parameter ENUM_MEM_IF_DWIDTH = "MEM_IF_DWIDTH_32"; //SYTH ONLY
|
| 357 |
|
|
parameter ENUM_MEM_IF_MEMTYPE = "DDR3_SDRAM"; //SYTH ONLY
|
| 358 |
|
|
parameter ENUM_MEM_IF_ROWADDR_WIDTH = "ADDR_WIDTH_16"; //SYTH & SIM
|
| 359 |
|
|
parameter ENUM_MEM_IF_SPEEDBIN = "DDR3_1066_6_6_6"; //SYTH ONLY
|
| 360 |
|
|
parameter ENUM_MEM_IF_TCCD = "TCCD_4"; //SYTH & SIM
|
| 361 |
|
|
parameter ENUM_MEM_IF_TCL = "TCL_6"; //SYTH & SIM
|
| 362 |
|
|
parameter ENUM_MEM_IF_TCWL = "TCWL_5"; //SYTH & SIM
|
| 363 |
|
|
parameter ENUM_MEM_IF_TFAW = "TFAW_16"; //SYTH & SIM
|
| 364 |
|
|
parameter ENUM_MEM_IF_TMRD = "TMRD_4"; //SYTH & SIM
|
| 365 |
|
|
parameter ENUM_MEM_IF_TRAS = "TRAS_16"; //SYTH & SIM
|
| 366 |
|
|
parameter ENUM_MEM_IF_TRC = "TRC_22"; //SYTH & SIM
|
| 367 |
|
|
parameter ENUM_MEM_IF_TRCD = "TRCD_6"; //SYTH & SIM
|
| 368 |
|
|
parameter ENUM_MEM_IF_TRP = "TRP_6"; //SYTH & SIM
|
| 369 |
|
|
parameter ENUM_MEM_IF_TRRD = "TRRD_4"; //SYTH & SIM
|
| 370 |
|
|
parameter ENUM_MEM_IF_TRTP = "TRTP_4"; //SYTH & SIM
|
| 371 |
|
|
parameter ENUM_MEM_IF_TWR = "TWR_6"; //SYTH & SIM
|
| 372 |
|
|
parameter ENUM_MEM_IF_TWTR = "TWTR_4"; //SYTH & SIM
|
| 373 |
|
|
parameter ENUM_MMR_CFG_MEM_BL = "MP_BL_8"; //SYTH & SIM
|
| 374 |
|
|
parameter ENUM_OUTPUT_REGD = "DISABLED"; //SYTH & SIM
|
| 375 |
|
|
parameter ENUM_PDN_EXIT_CYCLES = "SLOW_EXIT"; //SYTH & SIM
|
| 376 |
|
|
parameter ENUM_PORT0_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 377 |
|
|
parameter ENUM_PORT1_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 378 |
|
|
parameter ENUM_PORT2_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 379 |
|
|
parameter ENUM_PORT3_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 380 |
|
|
parameter ENUM_PORT4_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 381 |
|
|
parameter ENUM_PORT5_WIDTH = "PORT_64_BIT"; //SYTH & SIM
|
| 382 |
|
|
parameter ENUM_PRIORITY_0_0 = "WEIGHT_0"; //SYTH ONLY
|
| 383 |
|
|
parameter ENUM_PRIORITY_0_1 = "WEIGHT_0"; //SYTH ONLY
|
| 384 |
|
|
parameter ENUM_PRIORITY_0_2 = "WEIGHT_0"; //SYTH ONLY
|
| 385 |
|
|
parameter ENUM_PRIORITY_0_3 = "WEIGHT_0"; //SYTH ONLY
|
| 386 |
|
|
parameter ENUM_PRIORITY_0_4 = "WEIGHT_0"; //SYTH ONLY
|
| 387 |
|
|
parameter ENUM_PRIORITY_0_5 = "WEIGHT_0"; //SYTH ONLY
|
| 388 |
|
|
parameter ENUM_PRIORITY_1_0 = "WEIGHT_0"; //SYTH ONLY
|
| 389 |
|
|
parameter ENUM_PRIORITY_1_1 = "WEIGHT_0"; //SYTH ONLY
|
| 390 |
|
|
parameter ENUM_PRIORITY_1_2 = "WEIGHT_0"; //SYTH ONLY
|
| 391 |
|
|
parameter ENUM_PRIORITY_1_3 = "WEIGHT_0"; //SYTH ONLY
|
| 392 |
|
|
parameter ENUM_PRIORITY_1_4 = "WEIGHT_0"; //SYTH ONLY
|
| 393 |
|
|
parameter ENUM_PRIORITY_1_5 = "WEIGHT_0"; //SYTH ONLY
|
| 394 |
|
|
parameter ENUM_PRIORITY_2_0 = "WEIGHT_0"; //SYTH ONLY
|
| 395 |
|
|
parameter ENUM_PRIORITY_2_1 = "WEIGHT_0"; //SYTH ONLY
|
| 396 |
|
|
parameter ENUM_PRIORITY_2_2 = "WEIGHT_0"; //SYTH ONLY
|
| 397 |
|
|
parameter ENUM_PRIORITY_2_3 = "WEIGHT_0"; //SYTH ONLY
|
| 398 |
|
|
parameter ENUM_PRIORITY_2_4 = "WEIGHT_0"; //SYTH ONLY
|
| 399 |
|
|
parameter ENUM_PRIORITY_2_5 = "WEIGHT_0"; //SYTH ONLY
|
| 400 |
|
|
parameter ENUM_PRIORITY_3_0 = "WEIGHT_0"; //SYTH ONLY
|
| 401 |
|
|
parameter ENUM_PRIORITY_3_1 = "WEIGHT_0"; //SYTH ONLY
|
| 402 |
|
|
parameter ENUM_PRIORITY_3_2 = "WEIGHT_0"; //SYTH ONLY
|
| 403 |
|
|
parameter ENUM_PRIORITY_3_3 = "WEIGHT_0"; //SYTH ONLY
|
| 404 |
|
|
parameter ENUM_PRIORITY_3_4 = "WEIGHT_0"; //SYTH ONLY
|
| 405 |
|
|
parameter ENUM_PRIORITY_3_5 = "WEIGHT_0"; //SYTH ONLY
|
| 406 |
|
|
parameter ENUM_PRIORITY_4_0 = "WEIGHT_0"; //SYTH ONLY
|
| 407 |
|
|
parameter ENUM_PRIORITY_4_1 = "WEIGHT_0"; //SYTH ONLY
|
| 408 |
|
|
parameter ENUM_PRIORITY_4_2 = "WEIGHT_0"; //SYTH ONLY
|
| 409 |
|
|
parameter ENUM_PRIORITY_4_3 = "WEIGHT_0"; //SYTH ONLY
|
| 410 |
|
|
parameter ENUM_PRIORITY_4_4 = "WEIGHT_0"; //SYTH ONLY
|
| 411 |
|
|
parameter ENUM_PRIORITY_4_5 = "WEIGHT_0"; //SYTH ONLY
|
| 412 |
|
|
parameter ENUM_PRIORITY_5_0 = "WEIGHT_0"; //SYTH ONLY
|
| 413 |
|
|
parameter ENUM_PRIORITY_5_1 = "WEIGHT_0"; //SYTH ONLY
|
| 414 |
|
|
parameter ENUM_PRIORITY_5_2 = "WEIGHT_0"; //SYTH ONLY
|
| 415 |
|
|
parameter ENUM_PRIORITY_5_3 = "WEIGHT_0"; //SYTH ONLY
|
| 416 |
|
|
parameter ENUM_PRIORITY_5_4 = "WEIGHT_0"; //SYTH ONLY
|
| 417 |
|
|
parameter ENUM_PRIORITY_5_5 = "WEIGHT_0"; //SYTH ONLY
|
| 418 |
|
|
parameter ENUM_PRIORITY_6_0 = "WEIGHT_0"; //SYTH ONLY
|
| 419 |
|
|
parameter ENUM_PRIORITY_6_1 = "WEIGHT_0"; //SYTH ONLY
|
| 420 |
|
|
parameter ENUM_PRIORITY_6_2 = "WEIGHT_0"; //SYTH ONLY
|
| 421 |
|
|
parameter ENUM_PRIORITY_6_3 = "WEIGHT_0"; //SYTH ONLY
|
| 422 |
|
|
parameter ENUM_PRIORITY_6_4 = "WEIGHT_0"; //SYTH ONLY
|
| 423 |
|
|
parameter ENUM_PRIORITY_6_5 = "WEIGHT_0"; //SYTH ONLY
|
| 424 |
|
|
parameter ENUM_PRIORITY_7_0 = "WEIGHT_0"; //SYTH ONLY
|
| 425 |
|
|
parameter ENUM_PRIORITY_7_1 = "WEIGHT_0"; //SYTH ONLY
|
| 426 |
|
|
parameter ENUM_PRIORITY_7_2 = "WEIGHT_0"; //SYTH ONLY
|
| 427 |
|
|
parameter ENUM_PRIORITY_7_3 = "WEIGHT_0"; //SYTH ONLY
|
| 428 |
|
|
parameter ENUM_PRIORITY_7_4 = "WEIGHT_0"; //SYTH ONLY
|
| 429 |
|
|
parameter ENUM_PRIORITY_7_5 = "WEIGHT_0"; //SYTH ONLY
|
| 430 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_0 = "WEIGHT_0"; //SYTH & SIM
|
| 431 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_1 = "WEIGHT_0"; //SYTH & SIM
|
| 432 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_2 = "WEIGHT_0"; //SYTH & SIM
|
| 433 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_3 = "WEIGHT_0"; //SYTH & SIM
|
| 434 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_4 = "WEIGHT_0"; //SYTH & SIM
|
| 435 |
|
|
parameter ENUM_RCFG_STATIC_WEIGHT_5 = "WEIGHT_0"; //SYTH & SIM
|
| 436 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_0 = "PRIORITY_0"; //SYTH & SIM
|
| 437 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_1 = "PRIORITY_0"; //SYTH & SIM
|
| 438 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_2 = "PRIORITY_0"; //SYTH & SIM
|
| 439 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_3 = "PRIORITY_0"; //SYTH & SIM
|
| 440 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_4 = "PRIORITY_0"; //SYTH & SIM
|
| 441 |
|
|
parameter ENUM_RCFG_USER_PRIORITY_5 = "PRIORITY_0"; //SYTH & SIM
|
| 442 |
|
|
parameter ENUM_RD_DWIDTH_0 = "DWIDTH_0"; //SYTH ONLY
|
| 443 |
|
|
parameter ENUM_RD_DWIDTH_1 = "DWIDTH_0"; //SYTH ONLY
|
| 444 |
|
|
parameter ENUM_RD_DWIDTH_2 = "DWIDTH_0"; //SYTH ONLY
|
| 445 |
|
|
parameter ENUM_RD_DWIDTH_3 = "DWIDTH_0"; //SYTH ONLY
|
| 446 |
|
|
parameter ENUM_RD_DWIDTH_4 = "DWIDTH_0"; //SYTH ONLY
|
| 447 |
|
|
parameter ENUM_RD_DWIDTH_5 = "DWIDTH_0"; //SYTH ONLY
|
| 448 |
|
|
parameter ENUM_RD_FIFO_IN_USE_0 = "FALSE"; //SYTH ONLY
|
| 449 |
|
|
parameter ENUM_RD_FIFO_IN_USE_1 = "FALSE"; //SYTH ONLY
|
| 450 |
|
|
parameter ENUM_RD_FIFO_IN_USE_2 = "FALSE"; //SYTH ONLY
|
| 451 |
|
|
parameter ENUM_RD_FIFO_IN_USE_3 = "FALSE"; //SYTH ONLY
|
| 452 |
|
|
parameter ENUM_RD_PORT_INFO_0 = "USE_NO"; //SYTH ONLY
|
| 453 |
|
|
parameter ENUM_RD_PORT_INFO_1 = "USE_NO"; //SYTH ONLY
|
| 454 |
|
|
parameter ENUM_RD_PORT_INFO_2 = "USE_NO"; //SYTH ONLY
|
| 455 |
|
|
parameter ENUM_RD_PORT_INFO_3 = "USE_NO"; //SYTH ONLY
|
| 456 |
|
|
parameter ENUM_RD_PORT_INFO_4 = "USE_NO"; //SYTH ONLY
|
| 457 |
|
|
parameter ENUM_RD_PORT_INFO_5 = "USE_NO"; //SYTH ONLY
|
| 458 |
|
|
parameter ENUM_READ_ODT_CHIP = "ODT_DISABLED"; //SYTH & SIM
|
| 459 |
|
|
parameter ENUM_REORDER_DATA = "DATA_REORDERING"; //SYTH & SIM
|
| 460 |
|
|
parameter ENUM_RFIFO0_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 461 |
|
|
parameter ENUM_RFIFO1_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 462 |
|
|
parameter ENUM_RFIFO2_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 463 |
|
|
parameter ENUM_RFIFO3_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 464 |
|
|
parameter ENUM_SINGLE_READY_0 = "CONCATENATE_RDY"; //SYTH & SIM
|
| 465 |
|
|
parameter ENUM_SINGLE_READY_1 = "CONCATENATE_RDY"; //SYTH & SIM
|
| 466 |
|
|
parameter ENUM_SINGLE_READY_2 = "CONCATENATE_RDY"; //SYTH & SIM
|
| 467 |
|
|
parameter ENUM_SINGLE_READY_3 = "CONCATENATE_RDY"; //SYTH & SIM
|
| 468 |
|
|
parameter ENUM_STATIC_WEIGHT_0 = "WEIGHT_0"; //SYTH ONLY
|
| 469 |
|
|
parameter ENUM_STATIC_WEIGHT_1 = "WEIGHT_0"; //SYTH ONLY
|
| 470 |
|
|
parameter ENUM_STATIC_WEIGHT_2 = "WEIGHT_0"; //SYTH ONLY
|
| 471 |
|
|
parameter ENUM_STATIC_WEIGHT_3 = "WEIGHT_0"; //SYTH ONLY
|
| 472 |
|
|
parameter ENUM_STATIC_WEIGHT_4 = "WEIGHT_0"; //SYTH ONLY
|
| 473 |
|
|
parameter ENUM_STATIC_WEIGHT_5 = "WEIGHT_0"; //SYTH ONLY
|
| 474 |
|
|
parameter ENUM_SYNC_MODE_0 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 475 |
|
|
parameter ENUM_SYNC_MODE_1 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 476 |
|
|
parameter ENUM_SYNC_MODE_2 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 477 |
|
|
parameter ENUM_SYNC_MODE_3 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 478 |
|
|
parameter ENUM_SYNC_MODE_4 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 479 |
|
|
parameter ENUM_SYNC_MODE_5 = "ASYNCHRONOUS"; //SYTH & SIM
|
| 480 |
|
|
parameter ENUM_TEST_MODE = "NORMAL_MODE"; //SYTH & SIM
|
| 481 |
|
|
parameter ENUM_THLD_JAR1_0 = "THRESHOLD_32"; //SYTH & SIM
|
| 482 |
|
|
parameter ENUM_THLD_JAR1_1 = "THRESHOLD_32"; //SYTH & SIM
|
| 483 |
|
|
parameter ENUM_THLD_JAR1_2 = "THRESHOLD_32"; //SYTH & SIM
|
| 484 |
|
|
parameter ENUM_THLD_JAR1_3 = "THRESHOLD_32"; //SYTH & SIM
|
| 485 |
|
|
parameter ENUM_THLD_JAR1_4 = "THRESHOLD_32"; //SYTH & SIM
|
| 486 |
|
|
parameter ENUM_THLD_JAR1_5 = "THRESHOLD_32"; //SYTH & SIM
|
| 487 |
|
|
parameter ENUM_THLD_JAR2_0 = "THRESHOLD_16"; //SYTH & SIM
|
| 488 |
|
|
parameter ENUM_THLD_JAR2_1 = "THRESHOLD_16"; //SYTH & SIM
|
| 489 |
|
|
parameter ENUM_THLD_JAR2_2 = "THRESHOLD_16"; //SYTH & SIM
|
| 490 |
|
|
parameter ENUM_THLD_JAR2_3 = "THRESHOLD_16"; //SYTH & SIM
|
| 491 |
|
|
parameter ENUM_THLD_JAR2_4 = "THRESHOLD_16"; //SYTH & SIM
|
| 492 |
|
|
parameter ENUM_THLD_JAR2_5 = "THRESHOLD_16"; //SYTH & SIM
|
| 493 |
|
|
parameter ENUM_USE_ALMOST_EMPTY_0 = "EMPTY"; //SYTH & SIM
|
| 494 |
|
|
parameter ENUM_USE_ALMOST_EMPTY_1 = "EMPTY"; //SYTH & SIM
|
| 495 |
|
|
parameter ENUM_USE_ALMOST_EMPTY_2 = "EMPTY"; //SYTH & SIM
|
| 496 |
|
|
parameter ENUM_USE_ALMOST_EMPTY_3 = "EMPTY"; //SYTH & SIM
|
| 497 |
|
|
parameter ENUM_USER_ECC_EN = "DISABLE"; //SYTH & SIM
|
| 498 |
|
|
parameter ENUM_USER_PRIORITY_0 = "PRIORITY_0"; //SYTH ONLY
|
| 499 |
|
|
parameter ENUM_USER_PRIORITY_1 = "PRIORITY_0"; //SYTH ONLY
|
| 500 |
|
|
parameter ENUM_USER_PRIORITY_2 = "PRIORITY_0"; //SYTH ONLY
|
| 501 |
|
|
parameter ENUM_USER_PRIORITY_3 = "PRIORITY_0"; //SYTH ONLY
|
| 502 |
|
|
parameter ENUM_USER_PRIORITY_4 = "PRIORITY_0"; //SYTH ONLY
|
| 503 |
|
|
parameter ENUM_USER_PRIORITY_5 = "PRIORITY_0"; //SYTH ONLY
|
| 504 |
|
|
parameter ENUM_WFIFO0_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 505 |
|
|
parameter ENUM_WFIFO0_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 506 |
|
|
parameter ENUM_WFIFO1_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 507 |
|
|
parameter ENUM_WFIFO1_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 508 |
|
|
parameter ENUM_WFIFO2_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 509 |
|
|
parameter ENUM_WFIFO2_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 510 |
|
|
parameter ENUM_WFIFO3_CPORT_MAP = "CMD_PORT_0"; //SYTH & SIM
|
| 511 |
|
|
parameter ENUM_WFIFO3_RDY_ALMOST_FULL = "NOT_FULL"; //SYTH & SIM
|
| 512 |
|
|
parameter ENUM_WR_DWIDTH_0 = "DWIDTH_0"; //SYTH ONLY
|
| 513 |
|
|
parameter ENUM_WR_DWIDTH_1 = "DWIDTH_0"; //SYTH ONLY
|
| 514 |
|
|
parameter ENUM_WR_DWIDTH_2 = "DWIDTH_0"; //SYTH ONLY
|
| 515 |
|
|
parameter ENUM_WR_DWIDTH_3 = "DWIDTH_0"; //SYTH ONLY
|
| 516 |
|
|
parameter ENUM_WR_DWIDTH_4 = "DWIDTH_0"; //SYTH ONLY
|
| 517 |
|
|
parameter ENUM_WR_DWIDTH_5 = "DWIDTH_0"; //SYTH ONLY
|
| 518 |
|
|
parameter ENUM_WR_FIFO_IN_USE_0 = "FALSE"; //SYTH ONLY
|
| 519 |
|
|
parameter ENUM_WR_FIFO_IN_USE_1 = "FALSE"; //SYTH ONLY
|
| 520 |
|
|
parameter ENUM_WR_FIFO_IN_USE_2 = "FALSE"; //SYTH ONLY
|
| 521 |
|
|
parameter ENUM_WR_FIFO_IN_USE_3 = "FALSE"; //SYTH ONLY
|
| 522 |
|
|
parameter ENUM_WR_PORT_INFO_0 = "USE_NO"; //SYTH ONLY
|
| 523 |
|
|
parameter ENUM_WR_PORT_INFO_1 = "USE_NO"; //SYTH ONLY
|
| 524 |
|
|
parameter ENUM_WR_PORT_INFO_2 = "USE_NO"; //SYTH ONLY
|
| 525 |
|
|
parameter ENUM_WR_PORT_INFO_3 = "USE_NO"; //SYTH ONLY
|
| 526 |
|
|
parameter ENUM_WR_PORT_INFO_4 = "USE_NO"; //SYTH ONLY
|
| 527 |
|
|
parameter ENUM_WR_PORT_INFO_5 = "USE_NO"; //SYTH ONLY
|
| 528 |
|
|
parameter ENUM_WRITE_ODT_CHIP = "ODT_DISABLED"; //SYTH & SIM
|
| 529 |
|
|
parameter ENUM_ENABLE_BURST_INTERRUPT = "DISABLED"; //SYTH & SIM
|
| 530 |
|
|
parameter ENUM_ENABLE_BURST_TERMINATE = "DISABLED"; //SYTH & SIM
|
| 531 |
|
|
parameter INTG_POWER_SAVING_EXIT_CYCLES = 5; //SYTH & SIM
|
| 532 |
|
|
parameter INTG_MEM_CLK_ENTRY_CYCLES = 10; //SYTH & SIM
|
| 533 |
|
|
parameter INTG_PRIORITY_REMAP = 0; //SYTH & SIM
|
| 534 |
|
|
parameter INTG_MEM_AUTO_PD_CYCLES = 0; //SYTH & SIM
|
| 535 |
|
|
parameter INTG_CYC_TO_RLD_JARS_0 = 128; //SYTH & SIM
|
| 536 |
|
|
parameter INTG_CYC_TO_RLD_JARS_1 = 128; //SYTH & SIM
|
| 537 |
|
|
parameter INTG_CYC_TO_RLD_JARS_2 = 128; //SYTH & SIM
|
| 538 |
|
|
parameter INTG_CYC_TO_RLD_JARS_3 = 128; //SYTH & SIM
|
| 539 |
|
|
parameter INTG_CYC_TO_RLD_JARS_4 = 128; //SYTH & SIM
|
| 540 |
|
|
parameter INTG_CYC_TO_RLD_JARS_5 = 128; //SYTH & SIM
|
| 541 |
|
|
parameter INTG_EXTRA_CTL_CLK_ACT_TO_ACT = 0; //SYTH & SIM
|
| 542 |
|
|
parameter INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0; //SYTH & SIM
|
| 543 |
|
|
parameter INTG_EXTRA_CTL_CLK_ACT_TO_PCH = 0; //SYTH & SIM
|
| 544 |
|
|
parameter INTG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0; //SYTH & SIM
|
| 545 |
|
|
parameter INTG_EXTRA_CTL_CLK_ARF_PERIOD = 0; //SYTH & SIM
|
| 546 |
|
|
parameter INTG_EXTRA_CTL_CLK_ARF_TO_VALID = 0; //SYTH & SIM
|
| 547 |
|
|
parameter INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0; //SYTH & SIM
|
| 548 |
|
|
parameter INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0; //SYTH & SIM
|
| 549 |
|
|
parameter INTG_EXTRA_CTL_CLK_PCH_TO_VALID = 0; //SYTH & SIM
|
| 550 |
|
|
parameter INTG_EXTRA_CTL_CLK_PDN_PERIOD = 0; //SYTH & SIM
|
| 551 |
|
|
parameter INTG_EXTRA_CTL_CLK_PDN_TO_VALID = 0; //SYTH & SIM
|
| 552 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0; //SYTH & SIM
|
| 553 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_PCH = 0; //SYTH & SIM
|
| 554 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_RD = 0; //SYTH & SIM
|
| 555 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0; //SYTH & SIM
|
| 556 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_WR = 0; //SYTH & SIM
|
| 557 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0; //SYTH & SIM
|
| 558 |
|
|
parameter INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0; //SYTH & SIM
|
| 559 |
|
|
parameter INTG_EXTRA_CTL_CLK_SRF_TO_VALID = 0; //SYTH & SIM
|
| 560 |
|
|
parameter INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0; //SYTH & SIM
|
| 561 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0; //SYTH & SIM
|
| 562 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_PCH = 0; //SYTH & SIM
|
| 563 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_RD = 0; //SYTH & SIM
|
| 564 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0; //SYTH & SIM
|
| 565 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0; //SYTH & SIM
|
| 566 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_WR = 0; //SYTH & SIM
|
| 567 |
|
|
parameter INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0; //SYTH & SIM
|
| 568 |
|
|
parameter INTG_MEM_IF_TREFI = 3120; //SYTH & SIM
|
| 569 |
|
|
parameter INTG_MEM_IF_TRFC = 34; //SYTH & SIM
|
| 570 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_0 = 0; //SYTH & SIM
|
| 571 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_1 = 0; //SYTH & SIM
|
| 572 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_2 = 0; //SYTH & SIM
|
| 573 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_3 = 0; //SYTH & SIM
|
| 574 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_4 = 0; //SYTH & SIM
|
| 575 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_5 = 0; //SYTH & SIM
|
| 576 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_6 = 0; //SYTH & SIM
|
| 577 |
|
|
parameter INTG_RCFG_SUM_WT_PRIORITY_7 = 0; //SYTH & SIM
|
| 578 |
|
|
parameter INTG_SUM_WT_PRIORITY_0 = 0; //SYTH ONLY
|
| 579 |
|
|
parameter INTG_SUM_WT_PRIORITY_1 = 0; //SYTH ONLY
|
| 580 |
|
|
parameter INTG_SUM_WT_PRIORITY_2 = 0; //SYTH ONLY
|
| 581 |
|
|
parameter INTG_SUM_WT_PRIORITY_3 = 0; //SYTH ONLY
|
| 582 |
|
|
parameter INTG_SUM_WT_PRIORITY_4 = 0; //SYTH ONLY
|
| 583 |
|
|
parameter INTG_SUM_WT_PRIORITY_5 = 0; //SYTH ONLY
|
| 584 |
|
|
parameter INTG_SUM_WT_PRIORITY_6 = 0; //SYTH ONLY
|
| 585 |
|
|
parameter INTG_SUM_WT_PRIORITY_7 = 0; //SYTH ONLY
|
| 586 |
|
|
parameter VECT_ATTR_COUNTER_ONE_MASK = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM
|
| 587 |
|
|
parameter VECT_ATTR_COUNTER_ONE_MATCH = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM
|
| 588 |
|
|
parameter VECT_ATTR_COUNTER_ZERO_MASK = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM
|
| 589 |
|
|
parameter VECT_ATTR_COUNTER_ZERO_MATCH = 64'b0000000000000000000000000000000000000000000000000000000000000000; //SYTH & SIM
|
| 590 |
|
|
parameter VECT_ATTR_DEBUG_SELECT_BYTE = 32'b00000000000000000000000000000000; //SYTH & SIM
|
| 591 |
|
|
|
| 592 |
|
|
// END PARAMETER SECTION
|
| 593 |
|
|
//////////////////////////////////////////////////////////////////////////////
|
| 594 |
|
|
|
| 595 |
|
|
//////////////////////////////////////////////////////////////////////////////
|
| 596 |
|
|
// START LOCALPARAM
|
| 597 |
|
|
|
| 598 |
|
|
// WIRE
|
| 599 |
|
|
localparam CFG_CFG_AVALON_DATA_BYTES = 'd1;
|
| 600 |
|
|
localparam CFG_CFG_AVALON_ADDR_WIDTH = 'd10;
|
| 601 |
|
|
localparam MAX_CMD_PT_NUM = 6;
|
| 602 |
|
|
localparam MAX_FIFO_NUM = 4;
|
| 603 |
|
|
localparam RD_FIFO_WIDTH = 80;
|
| 604 |
|
|
localparam WR_FIFO_WIDTH = 90;
|
| 605 |
|
|
localparam MAX_PORT_BL = 255;
|
| 606 |
|
|
localparam MAX_PORT_CMD_WIDTH = 2;
|
| 607 |
|
|
localparam MAX_PORT_PRI_WIDTH = 0;
|
| 608 |
|
|
localparam MAX_PORT_ADDR_WIDTH = 32;
|
| 609 |
|
|
localparam MAX_PORT_BL_WIDTH = 8;
|
| 610 |
|
|
localparam MAX_PORT_TID_WIDTH = 0;
|
| 611 |
|
|
localparam MAX_PORT_CMDE_WIDTH = 0;
|
| 612 |
|
|
localparam CMD_FIFO_DWIDTH = (MAX_PORT_CMDE_WIDTH + MAX_PORT_TID_WIDTH + MAX_PORT_BL_WIDTH + MAX_PORT_ADDR_WIDTH + MAX_PORT_PRI_WIDTH + MAX_PORT_CMD_WIDTH);
|
| 613 |
|
|
localparam CFG_MEM_IF_CHIP = 1;
|
| 614 |
|
|
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
|
| 615 |
|
|
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 8;
|
| 616 |
|
|
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 8;
|
| 617 |
|
|
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 8;
|
| 618 |
|
|
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 8;
|
| 619 |
|
|
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 8;
|
| 620 |
|
|
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 8;
|
| 621 |
|
|
localparam CFG_PORT_WIDTH_ADD_LAT = 8;
|
| 622 |
|
|
localparam CFG_PORT_WIDTH_TCL = 8;
|
| 623 |
|
|
localparam CFG_PORT_WIDTH_TRFC = 8;
|
| 624 |
|
|
localparam CFG_PORT_WIDTH_TREFI = 16;
|
| 625 |
|
|
localparam CFG_PORT_WIDTH_TWR = 8;
|
| 626 |
|
|
localparam CFG_PORT_WIDTH_TMRD = 8;
|
| 627 |
|
|
|
| 628 |
|
|
localparam HARDIP_AFI_ADDR_WIDTH = 20;
|
| 629 |
|
|
localparam HARDIP_AFI_BANKADDR_WIDTH = 3 ;
|
| 630 |
|
|
localparam HARDIP_AFI_CONTROL_WIDTH = 1 ;
|
| 631 |
|
|
localparam HARDIP_AFI_CS_WIDTH = 2 ;
|
| 632 |
|
|
localparam HARDIP_AFI_ODT_WIDTH = 2 ;
|
| 633 |
|
|
localparam HARDIP_AFI_DM_WIDTH = 10;
|
| 634 |
|
|
localparam HARDIP_AFI_DQ_WIDTH = 80;
|
| 635 |
|
|
localparam HARDIP_AFI_WRITE_DQS_WIDTH = 5 ;
|
| 636 |
|
|
// HARDIP_AFI_RATE_RATIO doesn't make sense as a normal rate ratio,
|
| 637 |
|
|
// but it does make the correct size of the afi_rdata_en and afi_rdata_en_full signals
|
| 638 |
|
|
localparam HARDIP_AFI_RATE_RATIO = 5 ;
|
| 639 |
|
|
localparam HARDIP_AFI_WLAT_WIDTH = 4 ;
|
| 640 |
|
|
localparam HARDIP_AFI_RLAT_WIDTH = 5 ;
|
| 641 |
|
|
localparam HARDIP_TRACKING_WIDTH = 2 ;
|
| 642 |
|
|
|
| 643 |
|
|
localparam INT_AFI_ADDR_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_ADDR_WIDTH : AFI_ADDR_WIDTH ;
|
| 644 |
|
|
localparam INT_AFI_BANKADDR_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_BANKADDR_WIDTH : AFI_BANKADDR_WIDTH ;
|
| 645 |
|
|
localparam INT_AFI_CONTROL_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_CONTROL_WIDTH : AFI_CONTROL_WIDTH ;
|
| 646 |
|
|
localparam INT_AFI_CS_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_CS_WIDTH : AFI_CS_WIDTH ;
|
| 647 |
|
|
localparam INT_AFI_ODT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_ODT_WIDTH : AFI_ODT_WIDTH ;
|
| 648 |
|
|
localparam INT_AFI_DM_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_DM_WIDTH : AFI_DM_WIDTH ;
|
| 649 |
|
|
localparam INT_AFI_DQ_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_DQ_WIDTH : AFI_DQ_WIDTH ;
|
| 650 |
|
|
localparam INT_AFI_WRITE_DQS_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_WRITE_DQS_WIDTH : AFI_WRITE_DQS_WIDTH;
|
| 651 |
|
|
localparam INT_AFI_RATE_RATIO = (HARD_PHY == 1) ? HARDIP_AFI_RATE_RATIO : AFI_RATE_RATIO ;
|
| 652 |
|
|
localparam INT_AFI_WLAT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_WLAT_WIDTH : AFI_WLAT_WIDTH ;
|
| 653 |
|
|
localparam INT_AFI_RLAT_WIDTH = (HARD_PHY == 1) ? HARDIP_AFI_RLAT_WIDTH : AFI_RLAT_WIDTH ;
|
| 654 |
|
|
|
| 655 |
|
|
localparam ZERO_PAD_WIDTH_BE_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 2 : 6;
|
| 656 |
|
|
localparam ZERO_PAD_WIDTH_BE_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 0 : 2;
|
| 657 |
|
|
localparam ZERO_PAD_WIDTH_DT_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 32 : 48;
|
| 658 |
|
|
localparam ZERO_PAD_WIDTH_DT_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 0 : 16;
|
| 659 |
|
|
localparam BE_WIDTH_FIFO0_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 6 : 4;
|
| 660 |
|
|
localparam BE_WIDTH_FIFO0_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 10 : 8;
|
| 661 |
|
|
localparam BE_WIDTH_FIFO1_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 20 : 16;
|
| 662 |
|
|
localparam BE_WIDTH_FIFO2_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 30 : 24;
|
| 663 |
|
|
localparam BE_WIDTH_FIFO3_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 40 : 32;
|
| 664 |
|
|
localparam DATA_WIDTH_FIFO0_32 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 48 : 32;
|
| 665 |
|
|
localparam DATA_WIDTH_FIFO0_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 80 : 64;
|
| 666 |
|
|
localparam DATA_WIDTH_FIFO1_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 160 :128;
|
| 667 |
|
|
localparam DATA_WIDTH_FIFO2_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 240 :192;
|
| 668 |
|
|
localparam DATA_WIDTH_FIFO3_64 = (ENUM_USER_ECC_EN == "ENABLE" ) ? 320 :256;
|
| 669 |
|
|
|
| 670 |
|
|
// END LOCALPARAM
|
| 671 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 672 |
|
|
|
| 673 |
|
|
// END LOCALPARAM
|
| 674 |
|
|
//////////////////////////////////////////////////////////////////////////////
|
| 675 |
|
|
|
| 676 |
|
|
//////////////////////////////////////////////////////////////////////////////
|
| 677 |
|
|
// BEGIN PORT SECTION
|
| 678 |
|
|
|
| 679 |
|
|
// Clock and reset interface
|
| 680 |
|
|
input afi_clk;
|
| 681 |
|
|
input afi_half_clk;
|
| 682 |
|
|
input afi_reset_n;
|
| 683 |
|
|
input ctl_clk;
|
| 684 |
|
|
input ctl_reset_n;
|
| 685 |
|
|
input mp_cmd_clk_0;
|
| 686 |
|
|
input mp_cmd_clk_1;
|
| 687 |
|
|
input mp_cmd_clk_2;
|
| 688 |
|
|
input mp_cmd_clk_3;
|
| 689 |
|
|
input mp_cmd_clk_4;
|
| 690 |
|
|
input mp_cmd_clk_5;
|
| 691 |
|
|
input mp_cmd_reset_n_0;
|
| 692 |
|
|
input mp_cmd_reset_n_1;
|
| 693 |
|
|
input mp_cmd_reset_n_2;
|
| 694 |
|
|
input mp_cmd_reset_n_3;
|
| 695 |
|
|
input mp_cmd_reset_n_4;
|
| 696 |
|
|
input mp_cmd_reset_n_5;
|
| 697 |
|
|
input mp_rfifo_clk_0;
|
| 698 |
|
|
input mp_rfifo_clk_1;
|
| 699 |
|
|
input mp_rfifo_clk_2;
|
| 700 |
|
|
input mp_rfifo_clk_3;
|
| 701 |
|
|
input mp_rfifo_reset_n_0;
|
| 702 |
|
|
input mp_rfifo_reset_n_1;
|
| 703 |
|
|
input mp_rfifo_reset_n_2;
|
| 704 |
|
|
input mp_rfifo_reset_n_3;
|
| 705 |
|
|
input mp_wfifo_clk_0;
|
| 706 |
|
|
input mp_wfifo_clk_1;
|
| 707 |
|
|
input mp_wfifo_clk_2;
|
| 708 |
|
|
input mp_wfifo_clk_3;
|
| 709 |
|
|
input mp_wfifo_reset_n_0;
|
| 710 |
|
|
input mp_wfifo_reset_n_1;
|
| 711 |
|
|
input mp_wfifo_reset_n_2;
|
| 712 |
|
|
input mp_wfifo_reset_n_3;
|
| 713 |
|
|
input csr_clk;
|
| 714 |
|
|
input csr_reset_n;
|
| 715 |
|
|
|
| 716 |
|
|
// Avalon data slave interface
|
| 717 |
|
|
output avl_ready_0;
|
| 718 |
|
|
input avl_write_req_0;
|
| 719 |
|
|
input avl_read_req_0;
|
| 720 |
|
|
input [AVL_ADDR_WIDTH_PORT_0 - 1 : 0] avl_addr_0;
|
| 721 |
|
|
input [AVL_NUM_SYMBOLS_PORT_0 - 1 : 0] avl_be_0;
|
| 722 |
|
|
input [AVL_DATA_WIDTH_PORT_0 - 1 : 0] avl_wdata_0;
|
| 723 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_0;
|
| 724 |
|
|
input avl_burstbegin_0;
|
| 725 |
|
|
output [AVL_DATA_WIDTH_PORT_0 - 1 : 0] avl_rdata_0;
|
| 726 |
|
|
output avl_rdata_valid_0;
|
| 727 |
|
|
output avl_ready_1;
|
| 728 |
|
|
input avl_write_req_1;
|
| 729 |
|
|
input avl_read_req_1;
|
| 730 |
|
|
input [AVL_ADDR_WIDTH_PORT_1 - 1 : 0] avl_addr_1;
|
| 731 |
|
|
input [AVL_NUM_SYMBOLS_PORT_1 - 1 : 0] avl_be_1;
|
| 732 |
|
|
input [AVL_DATA_WIDTH_PORT_1 - 1 : 0] avl_wdata_1;
|
| 733 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_1;
|
| 734 |
|
|
input avl_burstbegin_1;
|
| 735 |
|
|
output [AVL_DATA_WIDTH_PORT_1 - 1 : 0] avl_rdata_1;
|
| 736 |
|
|
output avl_rdata_valid_1;
|
| 737 |
|
|
output avl_ready_2;
|
| 738 |
|
|
input avl_write_req_2;
|
| 739 |
|
|
input avl_read_req_2;
|
| 740 |
|
|
input [AVL_ADDR_WIDTH_PORT_2 - 1 : 0] avl_addr_2;
|
| 741 |
|
|
input [AVL_NUM_SYMBOLS_PORT_2 - 1 : 0] avl_be_2;
|
| 742 |
|
|
input [AVL_DATA_WIDTH_PORT_2 - 1 : 0] avl_wdata_2;
|
| 743 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_2;
|
| 744 |
|
|
input avl_burstbegin_2;
|
| 745 |
|
|
output [AVL_DATA_WIDTH_PORT_2 - 1 : 0] avl_rdata_2;
|
| 746 |
|
|
output avl_rdata_valid_2;
|
| 747 |
|
|
output avl_ready_3;
|
| 748 |
|
|
input avl_write_req_3;
|
| 749 |
|
|
input avl_read_req_3;
|
| 750 |
|
|
input [AVL_ADDR_WIDTH_PORT_3 - 1 : 0] avl_addr_3;
|
| 751 |
|
|
input [AVL_NUM_SYMBOLS_PORT_3 - 1 : 0] avl_be_3;
|
| 752 |
|
|
input [AVL_DATA_WIDTH_PORT_3 - 1 : 0] avl_wdata_3;
|
| 753 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_3;
|
| 754 |
|
|
input avl_burstbegin_3;
|
| 755 |
|
|
output [AVL_DATA_WIDTH_PORT_3 - 1 : 0] avl_rdata_3;
|
| 756 |
|
|
output avl_rdata_valid_3;
|
| 757 |
|
|
output avl_ready_4;
|
| 758 |
|
|
input avl_write_req_4;
|
| 759 |
|
|
input avl_read_req_4;
|
| 760 |
|
|
input [AVL_ADDR_WIDTH_PORT_4 - 1 : 0] avl_addr_4;
|
| 761 |
|
|
input [AVL_NUM_SYMBOLS_PORT_4 - 1 : 0] avl_be_4;
|
| 762 |
|
|
input [AVL_DATA_WIDTH_PORT_4 - 1 : 0] avl_wdata_4;
|
| 763 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_4;
|
| 764 |
|
|
input avl_burstbegin_4;
|
| 765 |
|
|
output [AVL_DATA_WIDTH_PORT_4 - 1 : 0] avl_rdata_4;
|
| 766 |
|
|
output avl_rdata_valid_4;
|
| 767 |
|
|
output avl_ready_5;
|
| 768 |
|
|
input avl_write_req_5;
|
| 769 |
|
|
input avl_read_req_5;
|
| 770 |
|
|
input [AVL_ADDR_WIDTH_PORT_5 - 1 : 0] avl_addr_5;
|
| 771 |
|
|
input [AVL_NUM_SYMBOLS_PORT_5 - 1 : 0] avl_be_5;
|
| 772 |
|
|
input [AVL_DATA_WIDTH_PORT_5 - 1 : 0] avl_wdata_5;
|
| 773 |
|
|
input [AVL_SIZE_WIDTH - 1 : 0] avl_size_5;
|
| 774 |
|
|
input avl_burstbegin_5;
|
| 775 |
|
|
output [AVL_DATA_WIDTH_PORT_5 - 1 : 0] avl_rdata_5;
|
| 776 |
|
|
output avl_rdata_valid_5;
|
| 777 |
|
|
|
| 778 |
|
|
// AFI signals
|
| 779 |
|
|
output [INT_AFI_CS_WIDTH - 1 : 0] afi_cs_n;
|
| 780 |
|
|
output [INT_AFI_CS_WIDTH - 1 : 0] afi_cke;
|
| 781 |
|
|
output [INT_AFI_ODT_WIDTH - 1 : 0] afi_odt;
|
| 782 |
|
|
output [INT_AFI_ADDR_WIDTH - 1 : 0] afi_addr;
|
| 783 |
|
|
output [INT_AFI_BANKADDR_WIDTH - 1 : 0] afi_ba;
|
| 784 |
|
|
output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_ras_n;
|
| 785 |
|
|
output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_cas_n;
|
| 786 |
|
|
output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_we_n;
|
| 787 |
|
|
output [INT_AFI_CONTROL_WIDTH - 1 : 0] afi_rst_n;
|
| 788 |
|
|
output [INT_AFI_WRITE_DQS_WIDTH - 1 : 0] afi_dqs_burst;
|
| 789 |
|
|
output [INT_AFI_WRITE_DQS_WIDTH - 1 : 0] afi_wdata_valid;
|
| 790 |
|
|
output [INT_AFI_DQ_WIDTH - 1 : 0] afi_wdata;
|
| 791 |
|
|
output [INT_AFI_DM_WIDTH - 1 : 0] afi_dm;
|
| 792 |
|
|
input [INT_AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
|
| 793 |
|
|
output [INT_AFI_RATE_RATIO - 1 : 0] afi_rdata_en;
|
| 794 |
|
|
output [INT_AFI_RATE_RATIO - 1 : 0] afi_rdata_en_full;
|
| 795 |
|
|
input [INT_AFI_DQ_WIDTH - 1 : 0] afi_rdata;
|
| 796 |
|
|
input [1 - 1 : 0] afi_rdata_valid;
|
| 797 |
|
|
input [INT_AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
|
| 798 |
|
|
input afi_cal_success;
|
| 799 |
|
|
input afi_cal_fail;
|
| 800 |
|
|
output afi_cal_req;
|
| 801 |
|
|
output afi_init_req;
|
| 802 |
|
|
|
| 803 |
|
|
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] afi_mem_clk_disable;
|
| 804 |
|
|
|
| 805 |
|
|
// disable unused AFI signals
|
| 806 |
|
|
|
| 807 |
|
|
wire [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1 : 0] afi_cal_byte_lane_sel_n;
|
| 808 |
|
|
output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_refresh_done;
|
| 809 |
|
|
input [MEM_IF_CS_WIDTH - 1 : 0] afi_seq_busy;
|
| 810 |
|
|
output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_long_idle;
|
| 811 |
|
|
|
| 812 |
|
|
// Sideband signals
|
| 813 |
|
|
output local_refresh_ack;
|
| 814 |
|
|
output local_powerdn_ack;
|
| 815 |
|
|
output local_self_rfsh_ack;
|
| 816 |
|
|
output local_deep_powerdn_ack;
|
| 817 |
|
|
input local_refresh_req;
|
| 818 |
|
|
input [MEM_IF_CS_WIDTH - 1 : 0] local_refresh_chip;
|
| 819 |
|
|
|
| 820 |
|
|
//Ahmed: do we need this?
|
| 821 |
|
|
//input local_powerdn_req;
|
| 822 |
|
|
input local_self_rfsh_req;
|
| 823 |
|
|
input [MEM_IF_CS_WIDTH - 1 : 0] local_self_rfsh_chip;
|
| 824 |
|
|
input local_deep_powerdn_req;
|
| 825 |
|
|
input [MEM_IF_CS_WIDTH - 1 : 0] local_deep_powerdn_chip;
|
| 826 |
|
|
input local_multicast;
|
| 827 |
|
|
input local_priority;
|
| 828 |
|
|
|
| 829 |
|
|
output local_init_done;
|
| 830 |
|
|
output local_cal_success;
|
| 831 |
|
|
output local_cal_fail;
|
| 832 |
|
|
|
| 833 |
|
|
// Csr & ecc signals
|
| 834 |
|
|
input csr_read_req;
|
| 835 |
|
|
input csr_write_req;
|
| 836 |
|
|
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
|
| 837 |
|
|
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
|
| 838 |
|
|
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
|
| 839 |
|
|
input [CSR_BE_WIDTH - 1 : 0] csr_be;
|
| 840 |
|
|
output csr_rdata_valid;
|
| 841 |
|
|
output csr_waitrequest;
|
| 842 |
|
|
|
| 843 |
|
|
// Cfg signal to Phy
|
| 844 |
|
|
output [23:0] cfg_dramconfig;
|
| 845 |
|
|
output [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_caswrlat;
|
| 846 |
|
|
output [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_addlat;
|
| 847 |
|
|
output [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
|
| 848 |
|
|
output [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
|
| 849 |
|
|
output [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
|
| 850 |
|
|
output [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
|
| 851 |
|
|
output [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
|
| 852 |
|
|
output [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_coladdrwidth;
|
| 853 |
|
|
output [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_rowaddrwidth;
|
| 854 |
|
|
output [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bankaddrwidth;
|
| 855 |
|
|
output [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_csaddrwidth;
|
| 856 |
|
|
output [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interfacewidth;
|
| 857 |
|
|
output [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_devicewidth;
|
| 858 |
|
|
output ctl_init_req;
|
| 859 |
|
|
|
| 860 |
|
|
// Bonding signals
|
| 861 |
|
|
output [MAX_FIFO_NUM - 1 : 0] bonding_out_1;
|
| 862 |
|
|
input [MAX_FIFO_NUM - 1 : 0] bonding_in_1;
|
| 863 |
|
|
output [MAX_CMD_PT_NUM - 1 : 0] bonding_out_2;
|
| 864 |
|
|
input [MAX_CMD_PT_NUM - 1 : 0] bonding_in_2;
|
| 865 |
|
|
output [MAX_CMD_PT_NUM - 1 : 0] bonding_out_3;
|
| 866 |
|
|
input [MAX_CMD_PT_NUM - 1 : 0] bonding_in_3;
|
| 867 |
|
|
|
| 868 |
|
|
// IO_INT interface from HPHY
|
| 869 |
|
|
input io_intaficalfail;
|
| 870 |
|
|
input io_intaficalsuccess;
|
| 871 |
|
|
|
| 872 |
|
|
// Connect to user logic
|
| 873 |
|
|
output local_sts_ctl_empty;
|
| 874 |
|
|
|
| 875 |
|
|
// END PORT SECTION
|
| 876 |
|
|
//////////////////////////////////////////////////////////////////////////////
|
| 877 |
|
|
|
| 878 |
|
|
wire i_avst_cmd_reset_n_0;
|
| 879 |
|
|
wire i_avst_cmd_reset_n_1;
|
| 880 |
|
|
wire i_avst_cmd_reset_n_2;
|
| 881 |
|
|
wire i_avst_cmd_reset_n_3;
|
| 882 |
|
|
wire i_avst_cmd_reset_n_4;
|
| 883 |
|
|
wire i_avst_cmd_reset_n_5;
|
| 884 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_0;
|
| 885 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_1;
|
| 886 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_2;
|
| 887 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_3;
|
| 888 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_4;
|
| 889 |
|
|
wire [CMD_FIFO_DWIDTH -1:0] i_avst_cmd_data_5;
|
| 890 |
|
|
wire o_a_mm_ready_0;
|
| 891 |
|
|
wire o_a_mm_ready_1;
|
| 892 |
|
|
wire o_a_mm_ready_2;
|
| 893 |
|
|
wire o_a_mm_ready_3;
|
| 894 |
|
|
wire o_a_mm_ready_4;
|
| 895 |
|
|
wire o_a_mm_ready_5;
|
| 896 |
|
|
wire i_avst_wrack_ready_0;
|
| 897 |
|
|
wire i_avst_wrack_ready_1;
|
| 898 |
|
|
wire i_avst_wrack_ready_2;
|
| 899 |
|
|
wire i_avst_wrack_ready_3;
|
| 900 |
|
|
wire i_avst_wrack_ready_4;
|
| 901 |
|
|
wire i_avst_wrack_ready_5;
|
| 902 |
|
|
wire o_wrack_avst_valid_0;
|
| 903 |
|
|
wire o_wrack_avst_valid_1;
|
| 904 |
|
|
wire o_wrack_avst_valid_2;
|
| 905 |
|
|
wire o_wrack_avst_valid_3;
|
| 906 |
|
|
wire o_wrack_avst_valid_4;
|
| 907 |
|
|
wire o_wrack_avst_valid_5;
|
| 908 |
|
|
wire o_wrack_avst_data_0;
|
| 909 |
|
|
wire o_wrack_avst_data_1;
|
| 910 |
|
|
wire o_wrack_avst_data_2;
|
| 911 |
|
|
wire o_wrack_avst_data_3;
|
| 912 |
|
|
wire o_wrack_avst_data_4;
|
| 913 |
|
|
wire o_wrack_avst_data_5;
|
| 914 |
|
|
wire i_avst_rd_clk_0;
|
| 915 |
|
|
wire i_avst_rd_clk_1;
|
| 916 |
|
|
wire i_avst_rd_clk_2;
|
| 917 |
|
|
wire i_avst_rd_clk_3;
|
| 918 |
|
|
wire i_avst_rd_reset_n_0;
|
| 919 |
|
|
wire i_avst_rd_reset_n_1;
|
| 920 |
|
|
wire i_avst_rd_reset_n_2;
|
| 921 |
|
|
wire i_avst_rd_reset_n_3;
|
| 922 |
|
|
wire o_rd_avst_valid_0;
|
| 923 |
|
|
wire o_rd_avst_valid_1;
|
| 924 |
|
|
wire o_rd_avst_valid_2;
|
| 925 |
|
|
wire o_rd_avst_valid_3;
|
| 926 |
|
|
wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_0;
|
| 927 |
|
|
wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_1;
|
| 928 |
|
|
wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_2;
|
| 929 |
|
|
wire [RD_FIFO_WIDTH -1:0] o_rd_avst_data_3;
|
| 930 |
|
|
wire i_avst_rd_ready_0;
|
| 931 |
|
|
wire i_avst_rd_ready_1;
|
| 932 |
|
|
wire i_avst_rd_ready_2;
|
| 933 |
|
|
wire i_avst_rd_ready_3;
|
| 934 |
|
|
wire i_avst_wr_clk_0;
|
| 935 |
|
|
wire i_avst_wr_clk_1;
|
| 936 |
|
|
wire i_avst_wr_clk_2;
|
| 937 |
|
|
wire i_avst_wr_clk_3;
|
| 938 |
|
|
wire i_avst_wr_reset_n_0;
|
| 939 |
|
|
wire i_avst_wr_reset_n_1;
|
| 940 |
|
|
wire i_avst_wr_reset_n_2;
|
| 941 |
|
|
wire i_avst_wr_reset_n_3;
|
| 942 |
|
|
wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_0;
|
| 943 |
|
|
wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_1;
|
| 944 |
|
|
wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_2;
|
| 945 |
|
|
wire [WR_FIFO_WIDTH -1:0] i_avst_wr_data_3;
|
| 946 |
|
|
wire [MAX_FIFO_NUM -1:0] bonding_out_1;
|
| 947 |
|
|
wire [MAX_FIFO_NUM -1:0] bonding_in_1;
|
| 948 |
|
|
wire [MAX_CMD_PT_NUM -1:0] bonding_out_2;
|
| 949 |
|
|
wire [MAX_CMD_PT_NUM -1:0] bonding_in_2;
|
| 950 |
|
|
wire [MAX_CMD_PT_NUM -1:0] bonding_out_3;
|
| 951 |
|
|
wire [MAX_CMD_PT_NUM -1:0] bonding_in_3;
|
| 952 |
|
|
wire local_refresh_req;
|
| 953 |
|
|
wire [2 -1:0] local_refresh_chip_wire;
|
| 954 |
|
|
wire local_deep_powerdn_req;
|
| 955 |
|
|
wire [2 -1:0] local_deep_powerdn_chip_wire;
|
| 956 |
|
|
wire local_self_rfsh_req;
|
| 957 |
|
|
wire [2 -1:0] local_self_rfsh_chip_wire;
|
| 958 |
|
|
wire local_refresh_ack;
|
| 959 |
|
|
wire local_deep_powerdn_ack;
|
| 960 |
|
|
wire local_powerdn_ack;
|
| 961 |
|
|
wire local_self_rfsh_ack;
|
| 962 |
|
|
wire local_init_done;
|
| 963 |
|
|
wire local_sts_ctl_empty;
|
| 964 |
|
|
wire ctl_init_req;
|
| 965 |
|
|
wire mmr_clk;
|
| 966 |
|
|
wire mmr_reset_n;
|
| 967 |
|
|
wire mmr_read_req;
|
| 968 |
|
|
wire mmr_write_req;
|
| 969 |
|
|
wire [2 -1:0] mmr_burst_count;
|
| 970 |
|
|
wire mmr_burst_begin;
|
| 971 |
|
|
wire [CFG_CFG_AVALON_ADDR_WIDTH -1:0] mmr_addr;
|
| 972 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] mmr_wdata;
|
| 973 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES -1:0] mmr_be;
|
| 974 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] mmr_rdata;
|
| 975 |
|
|
wire mmr_rdata_valid;
|
| 976 |
|
|
wire mmr_waitrequest;
|
| 977 |
|
|
wire sc_clk;
|
| 978 |
|
|
wire sc_reset_n;
|
| 979 |
|
|
wire sc_read_req;
|
| 980 |
|
|
wire sc_write_req;
|
| 981 |
|
|
wire [2 -1:0] sc_burst_count;
|
| 982 |
|
|
wire sc_burst_begin;
|
| 983 |
|
|
wire [CFG_CFG_AVALON_ADDR_WIDTH -1:0] sc_addr;
|
| 984 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] sc_wdata;
|
| 985 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES -1:0] sc_be;
|
| 986 |
|
|
wire [CFG_CFG_AVALON_DATA_BYTES*8 -1:0] sc_rdata;
|
| 987 |
|
|
wire sc_rdata_valid;
|
| 988 |
|
|
wire sc_waitrequest;
|
| 989 |
|
|
wire [24 -1:0] cfg_dramconfig;
|
| 990 |
|
|
wire [CFG_PORT_WIDTH_CAS_WR_LAT -1:0] cfg_caswrlat;
|
| 991 |
|
|
wire [CFG_PORT_WIDTH_ADD_LAT -1:0] cfg_addlat;
|
| 992 |
|
|
wire [CFG_PORT_WIDTH_TCL -1:0] cfg_tcl;
|
| 993 |
|
|
wire [CFG_PORT_WIDTH_TRFC -1:0] cfg_trfc;
|
| 994 |
|
|
wire [CFG_PORT_WIDTH_TREFI -1:0] cfg_trefi;
|
| 995 |
|
|
wire [CFG_PORT_WIDTH_TWR -1:0] cfg_twr;
|
| 996 |
|
|
wire [CFG_PORT_WIDTH_TMRD -1:0] cfg_tmrd;
|
| 997 |
|
|
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH -1:0] cfg_coladdrwidth;
|
| 998 |
|
|
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH -1:0] cfg_rowaddrwidth;
|
| 999 |
|
|
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH -1:0] cfg_bankaddrwidth;
|
| 1000 |
|
|
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH -1:0] cfg_csaddrwidth;
|
| 1001 |
|
|
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH -1:0] cfg_interfacewidth;
|
| 1002 |
|
|
wire [CFG_PORT_WIDTH_DEVICE_WIDTH -1:0] cfg_devicewidth;
|
| 1003 |
|
|
wire csrdin;
|
| 1004 |
|
|
wire csrdout;
|
| 1005 |
|
|
wire csrclk;
|
| 1006 |
|
|
wire csren;
|
| 1007 |
|
|
wire scanenable;
|
| 1008 |
|
|
wire afi_clk;
|
| 1009 |
|
|
wire afi_reset_n;
|
| 1010 |
|
|
wire ctl_reset_n;
|
| 1011 |
|
|
wire [HARDIP_TRACKING_WIDTH -1:0] afi_seq_busy_int;
|
| 1012 |
|
|
|
| 1013 |
|
|
wire [24 -1:0] cfg_dramconfig_wire;
|
| 1014 |
|
|
wire [4 -1:0] cfg_caswrlat_wire;
|
| 1015 |
|
|
wire [5 -1:0] cfg_addlat_wire;
|
| 1016 |
|
|
wire [5 -1:0] cfg_tcl_wire;
|
| 1017 |
|
|
wire [8 -1:0] cfg_trfc_wire;
|
| 1018 |
|
|
wire [16 -1:0] cfg_trefi_wire;
|
| 1019 |
|
|
wire [4 -1:0] cfg_twr_wire;
|
| 1020 |
|
|
wire [4 -1:0] cfg_tmrd_wire;
|
| 1021 |
|
|
wire [5 -1:0] cfg_coladdrwidth_wire;
|
| 1022 |
|
|
wire [5 -1:0] cfg_rowaddrwidth_wire;
|
| 1023 |
|
|
wire [3 -1:0] cfg_bankaddrwidth_wire;
|
| 1024 |
|
|
wire [3 -1:0] cfg_csaddrwidth_wire;
|
| 1025 |
|
|
wire [8 -1:0] cfg_interfacewidth_wire;
|
| 1026 |
|
|
wire [4 -1:0] cfg_devicewidth_wire;
|
| 1027 |
|
|
|
| 1028 |
|
|
|
| 1029 |
|
|
|
| 1030 |
|
|
//USED WITHIN THE MAPPING
|
| 1031 |
|
|
|
| 1032 |
|
|
wire [256 -1:0] data_width[5:0];
|
| 1033 |
|
|
wire [32 -1:0] lsb_wfifo[5:0];
|
| 1034 |
|
|
wire [32 -1:0] msb_wfifo[5:0];
|
| 1035 |
|
|
wire [32 -1:0] lsb_rfifo[5:0];
|
| 1036 |
|
|
|
| 1037 |
|
|
wire [320 -1:0] avl_wdata_g[5:0];
|
| 1038 |
|
|
wire [40 -1:0] avl_be_g[5:0];
|
| 1039 |
|
|
reg [WR_FIFO_WIDTH -1:0] i_avst_wr_data_g [3:0];
|
| 1040 |
|
|
|
| 1041 |
|
|
reg avl_rdata_valid_g[5:0];
|
| 1042 |
|
|
reg [320 -1:0] avl_rdata_g[5:0];
|
| 1043 |
|
|
|
| 1044 |
|
|
reg [INT_AFI_DM_WIDTH -1:0] afi_dm;
|
| 1045 |
|
|
reg [INT_AFI_DQ_WIDTH -1:0] afi_wdata;
|
| 1046 |
|
|
reg [INT_AFI_DQ_WIDTH -1:0] afi_rdata;
|
| 1047 |
|
|
|
| 1048 |
|
|
reg [HARDIP_AFI_DM_WIDTH -1:0] afi_dm_int;
|
| 1049 |
|
|
reg [HARDIP_AFI_DQ_WIDTH -1:0] afi_wdata_int;
|
| 1050 |
|
|
reg [HARDIP_AFI_DQ_WIDTH -1:0] afi_rdata_int;
|
| 1051 |
|
|
|
| 1052 |
|
|
|
| 1053 |
|
|
//------------------------------------------------------------------------------
|
| 1054 |
|
|
// CFG Interface Assignments
|
| 1055 |
|
|
//------------------------------------------------------------------------------
|
| 1056 |
|
|
|
| 1057 |
|
|
assign cfg_dramconfig = cfg_dramconfig_wire;
|
| 1058 |
|
|
assign cfg_caswrlat = cfg_caswrlat_wire;
|
| 1059 |
|
|
assign cfg_addlat = cfg_addlat_wire;
|
| 1060 |
|
|
assign cfg_tcl = cfg_tcl_wire;
|
| 1061 |
|
|
assign cfg_trfc = cfg_trfc_wire;
|
| 1062 |
|
|
assign cfg_trefi = cfg_trefi_wire;
|
| 1063 |
|
|
assign cfg_twr = cfg_twr_wire;
|
| 1064 |
|
|
assign cfg_tmrd = cfg_tmrd_wire;
|
| 1065 |
|
|
assign cfg_coladdrwidth = cfg_coladdrwidth_wire;
|
| 1066 |
|
|
assign cfg_rowaddrwidth = cfg_rowaddrwidth_wire;
|
| 1067 |
|
|
assign cfg_bankaddrwidth = cfg_bankaddrwidth_wire;
|
| 1068 |
|
|
assign cfg_csaddrwidth = cfg_csaddrwidth_wire;
|
| 1069 |
|
|
assign cfg_interfacewidth = cfg_interfacewidth_wire;
|
| 1070 |
|
|
assign cfg_devicewidth = cfg_devicewidth_wire;
|
| 1071 |
|
|
|
| 1072 |
|
|
//------------------------------------------------------------------------------
|
| 1073 |
|
|
// Sideband
|
| 1074 |
|
|
//------------------------------------------------------------------------------
|
| 1075 |
|
|
assign local_refresh_chip_wire = {{2-MEM_IF_CS_WIDTH{local_refresh_chip}}, local_refresh_chip};
|
| 1076 |
|
|
assign local_self_rfsh_chip_wire = {{2-MEM_IF_CS_WIDTH{local_self_rfsh_chip}}, local_self_rfsh_chip};
|
| 1077 |
|
|
assign local_deep_powerdn_chip_wire = {{2-MEM_IF_CS_WIDTH{local_deep_powerdn_chip}}, local_deep_powerdn_chip};
|
| 1078 |
|
|
|
| 1079 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1080 |
|
|
// START HIP TO SIP MAPING
|
| 1081 |
|
|
|
| 1082 |
|
|
//------------------------------------------------------------------------------
|
| 1083 |
|
|
// Passing all ports parameters into same variable
|
| 1084 |
|
|
//------------------------------------------------------------------------------
|
| 1085 |
|
|
|
| 1086 |
|
|
assign data_width[0] = AVL_DATA_WIDTH_PORT_0;
|
| 1087 |
|
|
assign data_width[1] = AVL_DATA_WIDTH_PORT_1;
|
| 1088 |
|
|
assign data_width[2] = AVL_DATA_WIDTH_PORT_2;
|
| 1089 |
|
|
assign data_width[3] = AVL_DATA_WIDTH_PORT_3;
|
| 1090 |
|
|
assign data_width[4] = AVL_DATA_WIDTH_PORT_4;
|
| 1091 |
|
|
assign data_width[5] = AVL_DATA_WIDTH_PORT_5;
|
| 1092 |
|
|
|
| 1093 |
|
|
assign lsb_wfifo[0] = LSB_WFIFO_PORT_0;
|
| 1094 |
|
|
assign lsb_wfifo[1] = LSB_WFIFO_PORT_1;
|
| 1095 |
|
|
assign lsb_wfifo[2] = LSB_WFIFO_PORT_2;
|
| 1096 |
|
|
assign lsb_wfifo[3] = LSB_WFIFO_PORT_3;
|
| 1097 |
|
|
assign lsb_wfifo[4] = LSB_WFIFO_PORT_4;
|
| 1098 |
|
|
assign lsb_wfifo[5] = LSB_WFIFO_PORT_5;
|
| 1099 |
|
|
|
| 1100 |
|
|
assign msb_wfifo[0] = MSB_WFIFO_PORT_0;
|
| 1101 |
|
|
assign msb_wfifo[1] = MSB_WFIFO_PORT_1;
|
| 1102 |
|
|
assign msb_wfifo[2] = MSB_WFIFO_PORT_2;
|
| 1103 |
|
|
assign msb_wfifo[3] = MSB_WFIFO_PORT_3;
|
| 1104 |
|
|
assign msb_wfifo[4] = MSB_WFIFO_PORT_4;
|
| 1105 |
|
|
assign msb_wfifo[5] = MSB_WFIFO_PORT_5;
|
| 1106 |
|
|
|
| 1107 |
|
|
assign lsb_rfifo[0] = LSB_RFIFO_PORT_0;
|
| 1108 |
|
|
assign lsb_rfifo[1] = LSB_RFIFO_PORT_1;
|
| 1109 |
|
|
assign lsb_rfifo[2] = LSB_RFIFO_PORT_2;
|
| 1110 |
|
|
assign lsb_rfifo[3] = LSB_RFIFO_PORT_3;
|
| 1111 |
|
|
assign lsb_rfifo[4] = LSB_RFIFO_PORT_4;
|
| 1112 |
|
|
assign lsb_rfifo[5] = LSB_RFIFO_PORT_5;
|
| 1113 |
|
|
|
| 1114 |
|
|
//------------------------------------------------------------------------------
|
| 1115 |
|
|
// Command path
|
| 1116 |
|
|
//------------------------------------------------------------------------------
|
| 1117 |
|
|
|
| 1118 |
|
|
assign avl_ready_0 = o_a_mm_ready_0 ;
|
| 1119 |
|
|
assign avl_ready_1 = o_a_mm_ready_1 ;
|
| 1120 |
|
|
assign avl_ready_2 = o_a_mm_ready_2 ;
|
| 1121 |
|
|
assign avl_ready_3 = o_a_mm_ready_3 ;
|
| 1122 |
|
|
assign avl_ready_4 = o_a_mm_ready_4 ;
|
| 1123 |
|
|
assign avl_ready_5 = o_a_mm_ready_5 ;
|
| 1124 |
|
|
|
| 1125 |
|
|
assign i_avst_cmd_data_0 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_0,{34-AVL_ADDR_WIDTH_PORT_0-2{1'b0}},avl_addr_0,avl_write_req_0,avl_read_req_0};
|
| 1126 |
|
|
assign i_avst_cmd_data_1 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_1,{34-AVL_ADDR_WIDTH_PORT_1-2{1'b0}},avl_addr_1,avl_write_req_1,avl_read_req_1};
|
| 1127 |
|
|
assign i_avst_cmd_data_2 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_2,{34-AVL_ADDR_WIDTH_PORT_2-2{1'b0}},avl_addr_2,avl_write_req_2,avl_read_req_2};
|
| 1128 |
|
|
assign i_avst_cmd_data_3 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_3,{34-AVL_ADDR_WIDTH_PORT_3-2{1'b0}},avl_addr_3,avl_write_req_3,avl_read_req_3};
|
| 1129 |
|
|
assign i_avst_cmd_data_4 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_4,{34-AVL_ADDR_WIDTH_PORT_4-2{1'b0}},avl_addr_4,avl_write_req_4,avl_read_req_4};
|
| 1130 |
|
|
assign i_avst_cmd_data_5 = {{42-AVL_SIZE_WIDTH-34{1'b0}},avl_size_5,{34-AVL_ADDR_WIDTH_PORT_5-2{1'b0}},avl_addr_5,avl_write_req_5,avl_read_req_5};
|
| 1131 |
|
|
|
| 1132 |
|
|
//------------------------------------------------------------------------------
|
| 1133 |
|
|
// Write data path
|
| 1134 |
|
|
//------------------------------------------------------------------------------
|
| 1135 |
|
|
|
| 1136 |
|
|
assign i_avst_wr_data_0 = i_avst_wr_data_g[0];
|
| 1137 |
|
|
assign i_avst_wr_data_1 = i_avst_wr_data_g[1];
|
| 1138 |
|
|
assign i_avst_wr_data_2 = i_avst_wr_data_g[2];
|
| 1139 |
|
|
assign i_avst_wr_data_3 = i_avst_wr_data_g[3];
|
| 1140 |
|
|
|
| 1141 |
|
|
assign avl_wdata_g[0] = avl_wdata_0;
|
| 1142 |
|
|
assign avl_wdata_g[1] = avl_wdata_1;
|
| 1143 |
|
|
assign avl_wdata_g[2] = avl_wdata_2;
|
| 1144 |
|
|
assign avl_wdata_g[3] = avl_wdata_3;
|
| 1145 |
|
|
assign avl_wdata_g[4] = avl_wdata_4;
|
| 1146 |
|
|
assign avl_wdata_g[5] = avl_wdata_5;
|
| 1147 |
|
|
|
| 1148 |
|
|
assign avl_be_g[0] = avl_be_0;
|
| 1149 |
|
|
assign avl_be_g[1] = avl_be_1;
|
| 1150 |
|
|
assign avl_be_g[2] = avl_be_2;
|
| 1151 |
|
|
assign avl_be_g[3] = avl_be_3;
|
| 1152 |
|
|
assign avl_be_g[4] = avl_be_4;
|
| 1153 |
|
|
assign avl_be_g[5] = avl_be_5;
|
| 1154 |
|
|
|
| 1155 |
|
|
//------------------------------------------------------------------------------
|
| 1156 |
|
|
// Read data path
|
| 1157 |
|
|
//------------------------------------------------------------------------------
|
| 1158 |
|
|
|
| 1159 |
|
|
assign avl_rdata_valid_0 = avl_rdata_valid_g[0];
|
| 1160 |
|
|
assign avl_rdata_valid_1 = avl_rdata_valid_g[1];
|
| 1161 |
|
|
assign avl_rdata_valid_2 = avl_rdata_valid_g[2];
|
| 1162 |
|
|
assign avl_rdata_valid_3 = avl_rdata_valid_g[3];
|
| 1163 |
|
|
assign avl_rdata_valid_4 = avl_rdata_valid_g[4];
|
| 1164 |
|
|
assign avl_rdata_valid_5 = avl_rdata_valid_g[5];
|
| 1165 |
|
|
|
| 1166 |
|
|
assign avl_rdata_0 = avl_rdata_g[0];
|
| 1167 |
|
|
assign avl_rdata_1 = avl_rdata_g[1];
|
| 1168 |
|
|
assign avl_rdata_2 = avl_rdata_g[2];
|
| 1169 |
|
|
assign avl_rdata_3 = avl_rdata_g[3];
|
| 1170 |
|
|
assign avl_rdata_4 = avl_rdata_g[4];
|
| 1171 |
|
|
assign avl_rdata_5 = avl_rdata_g[5];
|
| 1172 |
|
|
|
| 1173 |
|
|
reg [6-1:0] multi_fact_cmd0[5:0];
|
| 1174 |
|
|
reg [6-1:0] multi_fact_cmd1[5:0];
|
| 1175 |
|
|
reg [6-1:0] multi_fact_cmd2[5:0];
|
| 1176 |
|
|
reg [6-1:0] multi_fact_cmd3[5:0];
|
| 1177 |
|
|
reg [6-1:0] multi_fact_cmd4[5:0];
|
| 1178 |
|
|
reg [6-1:0] multi_fact_cmd5[5:0];
|
| 1179 |
|
|
|
| 1180 |
|
|
integer total_used_fifo,port_i,fifo_i,idx_0,idx_1,idx_2,idx_3,idx_4,idx_5,idx_6;
|
| 1181 |
|
|
always_comb
|
| 1182 |
|
|
begin
|
| 1183 |
|
|
|
| 1184 |
|
|
for (port_i = 0; port_i < 6; port_i = port_i + 1'b1)
|
| 1185 |
|
|
begin : port_loop
|
| 1186 |
|
|
|
| 1187 |
|
|
//----------------------------------------------------------------------
|
| 1188 |
|
|
// Read data path
|
| 1189 |
|
|
//----------------------------------------------------------------------
|
| 1190 |
|
|
|
| 1191 |
|
|
if (lsb_rfifo[port_i] == 0)
|
| 1192 |
|
|
avl_rdata_valid_g[port_i] = o_rd_avst_valid_0;
|
| 1193 |
|
|
else if (lsb_rfifo[port_i] == 1)
|
| 1194 |
|
|
avl_rdata_valid_g[port_i] = o_rd_avst_valid_1;
|
| 1195 |
|
|
else if (lsb_rfifo[port_i] == 2)
|
| 1196 |
|
|
avl_rdata_valid_g[port_i] = o_rd_avst_valid_2;
|
| 1197 |
|
|
else if (lsb_rfifo[port_i] == 3)
|
| 1198 |
|
|
avl_rdata_valid_g[port_i] = o_rd_avst_valid_3;
|
| 1199 |
|
|
else
|
| 1200 |
|
|
avl_rdata_valid_g[port_i] = 0;
|
| 1201 |
|
|
|
| 1202 |
|
|
if ((data_width[port_i] == 32) || (data_width[port_i] == 48))
|
| 1203 |
|
|
if (lsb_rfifo[port_i] == 0)
|
| 1204 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_0[DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1205 |
|
|
else if (lsb_rfifo[port_i] == 1)
|
| 1206 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1207 |
|
|
else if (lsb_rfifo[port_i] == 2)
|
| 1208 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_2[DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1209 |
|
|
else if (lsb_rfifo[port_i] == 3)
|
| 1210 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_32){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1211 |
|
|
else
|
| 1212 |
|
|
avl_rdata_g[port_i] = 320'd0;
|
| 1213 |
|
|
else if ((data_width[port_i] == 64) || (data_width[port_i] == 80))
|
| 1214 |
|
|
if (lsb_rfifo[port_i] == 0)
|
| 1215 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1216 |
|
|
else if (lsb_rfifo[port_i] == 1)
|
| 1217 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1218 |
|
|
else if (lsb_rfifo[port_i] == 2)
|
| 1219 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1220 |
|
|
else if (lsb_rfifo[port_i] == 3)
|
| 1221 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1222 |
|
|
else
|
| 1223 |
|
|
avl_rdata_g[port_i] = 320'd0;
|
| 1224 |
|
|
else if ((data_width[port_i] == 128) || (data_width[port_i] == 160))
|
| 1225 |
|
|
if (lsb_rfifo[port_i] == 0)
|
| 1226 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 2){1'b0}},o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1227 |
|
|
else if (lsb_rfifo[port_i] == 2)
|
| 1228 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 2){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1229 |
|
|
else
|
| 1230 |
|
|
avl_rdata_g[port_i] = 320'd0;
|
| 1231 |
|
|
else if ((data_width[port_i] == 256) || (data_width[port_i] == 320))
|
| 1232 |
|
|
avl_rdata_g[port_i] = {{(320 - DATA_WIDTH_FIFO0_64 * 4){1'b0}},o_rd_avst_data_3[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_2[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_1[DATA_WIDTH_FIFO0_64 - 1 : 0],o_rd_avst_data_0[DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1233 |
|
|
else
|
| 1234 |
|
|
avl_rdata_g[port_i] = 320'd0;
|
| 1235 |
|
|
end
|
| 1236 |
|
|
|
| 1237 |
|
|
for (fifo_i = 0; fifo_i < 4; fifo_i = fifo_i + 1)
|
| 1238 |
|
|
begin : fifo_loop
|
| 1239 |
|
|
|
| 1240 |
|
|
//----------------------------------------------------------------------
|
| 1241 |
|
|
// Write data path
|
| 1242 |
|
|
//----------------------------------------------------------------------
|
| 1243 |
|
|
|
| 1244 |
|
|
if ((lsb_wfifo[0] <= fifo_i) && (msb_wfifo[0] >= fifo_i))
|
| 1245 |
|
|
if ((data_width[0] == 32) || (data_width[0] == 48))
|
| 1246 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[0][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1247 |
|
|
else if (fifo_i - lsb_wfifo[0] == 0)
|
| 1248 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1249 |
|
|
else if (fifo_i - lsb_wfifo[0] == 1)
|
| 1250 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1251 |
|
|
else if (fifo_i - lsb_wfifo[0] == 2)
|
| 1252 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1253 |
|
|
else if (fifo_i - lsb_wfifo[0] == 3)
|
| 1254 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[0][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[0][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1255 |
|
|
else
|
| 1256 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1257 |
|
|
else if ((lsb_wfifo[1] <= fifo_i) && (msb_wfifo[1] >= fifo_i))
|
| 1258 |
|
|
if ((data_width[1] == 32) || (data_width[1] == 48))
|
| 1259 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[1][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1260 |
|
|
else if (fifo_i - lsb_wfifo[1] == 0)
|
| 1261 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1262 |
|
|
else if (fifo_i - lsb_wfifo[1] == 1)
|
| 1263 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1264 |
|
|
else if (fifo_i - lsb_wfifo[1] == 2)
|
| 1265 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1266 |
|
|
else if (fifo_i - lsb_wfifo[1] == 3)
|
| 1267 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[1][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[1][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1268 |
|
|
else
|
| 1269 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1270 |
|
|
else if ((lsb_wfifo[2] <= fifo_i) && (msb_wfifo[2] >= fifo_i))
|
| 1271 |
|
|
if ((data_width[2] == 32) || (data_width[2] == 48))
|
| 1272 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[2][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1273 |
|
|
else if (fifo_i - lsb_wfifo[2] == 0)
|
| 1274 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1275 |
|
|
else if (fifo_i - lsb_wfifo[2] == 1)
|
| 1276 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1277 |
|
|
else if (fifo_i - lsb_wfifo[2] == 2)
|
| 1278 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1279 |
|
|
else if (fifo_i - lsb_wfifo[2] == 3)
|
| 1280 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[2][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[2][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1281 |
|
|
else
|
| 1282 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1283 |
|
|
else if ((lsb_wfifo[3] <= fifo_i) && (msb_wfifo[3] >= fifo_i))
|
| 1284 |
|
|
if ((data_width[3] == 32) || (data_width[3] == 48))
|
| 1285 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[3][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1286 |
|
|
else if (fifo_i - lsb_wfifo[3] == 0)
|
| 1287 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1288 |
|
|
else if (fifo_i - lsb_wfifo[3] == 1)
|
| 1289 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1290 |
|
|
else if (fifo_i - lsb_wfifo[3] == 2)
|
| 1291 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1292 |
|
|
else if (fifo_i - lsb_wfifo[3] == 3)
|
| 1293 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[3][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[3][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1294 |
|
|
else
|
| 1295 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1296 |
|
|
else if ((lsb_wfifo[4] <= fifo_i) && (msb_wfifo[4] >= fifo_i))
|
| 1297 |
|
|
if ((data_width[4] == 32) || (data_width[4] == 48))
|
| 1298 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[4][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1299 |
|
|
else if (fifo_i - lsb_wfifo[4] == 0)
|
| 1300 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1301 |
|
|
else if (fifo_i - lsb_wfifo[4] == 1)
|
| 1302 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1303 |
|
|
else if (fifo_i - lsb_wfifo[4] == 2)
|
| 1304 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1305 |
|
|
else if (fifo_i - lsb_wfifo[4] == 3)
|
| 1306 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[4][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[4][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1307 |
|
|
else
|
| 1308 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1309 |
|
|
else if ((lsb_wfifo[5] <= fifo_i) && (msb_wfifo[5] >= fifo_i))
|
| 1310 |
|
|
if ((data_width[5] == 32) || (data_width[5] == 48))
|
| 1311 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_32{1'b0}},avl_be_g[5][BE_WIDTH_FIFO0_32 - 1 : 0],{ZERO_PAD_WIDTH_DT_32{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO0_32 - 1 : 0]};
|
| 1312 |
|
|
else if (fifo_i - lsb_wfifo[5] == 0)
|
| 1313 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO0_64 - 1 : 0],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO0_64 - 1 : 0]};
|
| 1314 |
|
|
else if (fifo_i - lsb_wfifo[5] == 1)
|
| 1315 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO1_64 - 1 : BE_WIDTH_FIFO0_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO1_64 - 1 : DATA_WIDTH_FIFO0_64]};
|
| 1316 |
|
|
else if (fifo_i - lsb_wfifo[5] == 2)
|
| 1317 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO2_64 - 1 : BE_WIDTH_FIFO1_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO2_64 - 1 : DATA_WIDTH_FIFO1_64]};
|
| 1318 |
|
|
else if (fifo_i - lsb_wfifo[5] == 3)
|
| 1319 |
|
|
i_avst_wr_data_g[fifo_i] = {{ZERO_PAD_WIDTH_BE_64{1'b0}},avl_be_g[5][BE_WIDTH_FIFO3_64 - 1 : BE_WIDTH_FIFO2_64],{ZERO_PAD_WIDTH_DT_64{1'b0}},avl_wdata_g[5][DATA_WIDTH_FIFO3_64 - 1 : DATA_WIDTH_FIFO2_64]};
|
| 1320 |
|
|
else
|
| 1321 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1322 |
|
|
else
|
| 1323 |
|
|
i_avst_wr_data_g[fifo_i] = 90'd0;
|
| 1324 |
|
|
end
|
| 1325 |
|
|
|
| 1326 |
|
|
//----------------------------------------------------------------------
|
| 1327 |
|
|
// Afi
|
| 1328 |
|
|
//----------------------------------------------------------------------
|
| 1329 |
|
|
|
| 1330 |
|
|
if (HARD_PHY == 1)
|
| 1331 |
|
|
begin
|
| 1332 |
|
|
afi_rdata_int = afi_rdata;
|
| 1333 |
|
|
afi_wdata = afi_wdata_int;
|
| 1334 |
|
|
afi_dm = afi_dm_int;
|
| 1335 |
|
|
end
|
| 1336 |
|
|
else
|
| 1337 |
|
|
begin
|
| 1338 |
|
|
for (idx_4 = 0; idx_4 < HARDIP_AFI_DQ_WIDTH; idx_4 = idx_4 + 1'b1)
|
| 1339 |
|
|
begin : afi_rdata_hip_to_sip
|
| 1340 |
|
|
if (idx_4 < INT_AFI_DQ_WIDTH/2)
|
| 1341 |
|
|
afi_rdata_int[idx_4] = afi_rdata[idx_4];
|
| 1342 |
|
|
else if ((idx_4 > (HARDIP_AFI_DQ_WIDTH / 2 - 1)) && (idx_4 < (HARDIP_AFI_DQ_WIDTH / 2 + INT_AFI_DQ_WIDTH / 2)))
|
| 1343 |
|
|
afi_rdata_int[idx_4] = afi_rdata[idx_4 - ((HARDIP_AFI_DQ_WIDTH /2) - (INT_AFI_DQ_WIDTH / 2))];
|
| 1344 |
|
|
else
|
| 1345 |
|
|
afi_rdata_int[idx_4] = 1'b0;
|
| 1346 |
|
|
end
|
| 1347 |
|
|
|
| 1348 |
|
|
for (idx_5 = 0; idx_5 < INT_AFI_DQ_WIDTH; idx_5 = idx_5 + 1'b1)
|
| 1349 |
|
|
begin : afi_wdata_hip_to_sip
|
| 1350 |
|
|
if (idx_5 < (INT_AFI_DQ_WIDTH / 2))
|
| 1351 |
|
|
afi_wdata[idx_5] = afi_wdata_int[idx_5];
|
| 1352 |
|
|
else
|
| 1353 |
|
|
afi_wdata[idx_5] = afi_wdata_int[idx_5 + ((HARDIP_AFI_DQ_WIDTH / 2) - (INT_AFI_DQ_WIDTH / 2))];
|
| 1354 |
|
|
end
|
| 1355 |
|
|
|
| 1356 |
|
|
for (idx_6 = 0; idx_6 < INT_AFI_DM_WIDTH; idx_6 = idx_6 + 1'b1)
|
| 1357 |
|
|
begin : afi_dm_hip_to_sip
|
| 1358 |
|
|
if (idx_6 < (INT_AFI_DM_WIDTH / 2))
|
| 1359 |
|
|
afi_dm[idx_6] = afi_dm_int[idx_6];
|
| 1360 |
|
|
else
|
| 1361 |
|
|
afi_dm[idx_6] = afi_dm_int[idx_6 + ((HARDIP_AFI_DM_WIDTH / 2) - (INT_AFI_DM_WIDTH / 2))];
|
| 1362 |
|
|
end
|
| 1363 |
|
|
end
|
| 1364 |
|
|
end
|
| 1365 |
|
|
|
| 1366 |
|
|
// END HIP TO SIP MAPING
|
| 1367 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1368 |
|
|
|
| 1369 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1370 |
|
|
// START OTHERS ASSIGNMENT
|
| 1371 |
|
|
|
| 1372 |
|
|
assign local_cal_success = io_intaficalsuccess;
|
| 1373 |
|
|
assign local_cal_fail = io_intaficalfail;
|
| 1374 |
|
|
|
| 1375 |
|
|
assign afi_init_req = '0;
|
| 1376 |
|
|
assign afi_seq_busy_int = {HARDIP_TRACKING_WIDTH{afi_seq_busy[0]}};
|
| 1377 |
|
|
|
| 1378 |
|
|
// END OTHERS ASSIGNMENT
|
| 1379 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1380 |
|
|
|
| 1381 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1382 |
|
|
// START ATOM INSTANTIATION
|
| 1383 |
|
|
|
| 1384 |
|
|
// Those that mark with //HARD NET is harden wire between controller and phy.
|
| 1385 |
|
|
// ASM / Fitter will fail if they're not connected properly
|
| 1386 |
|
|
|
| 1387 |
|
|
cyclonev_hmc hmc_inst (
|
| 1388 |
|
|
.portclk0 ( mp_cmd_clk_0 ), //SOFT NET
|
| 1389 |
|
|
.portclk1 ( mp_cmd_clk_1 ), //SOFT NET
|
| 1390 |
|
|
.portclk2 ( mp_cmd_clk_2 ), //SOFT NET
|
| 1391 |
|
|
.portclk3 ( mp_cmd_clk_3 ), //SOFT NET
|
| 1392 |
|
|
.portclk4 ( mp_cmd_clk_4 ), //SOFT NET
|
| 1393 |
|
|
.portclk5 ( mp_cmd_clk_5 ), //SOFT NET
|
| 1394 |
|
|
.iavstcmdresetn0 ( mp_cmd_reset_n_0 ), //SOFT NET
|
| 1395 |
|
|
.iavstcmdresetn1 ( mp_cmd_reset_n_1 ), //SOFT NET
|
| 1396 |
|
|
.iavstcmdresetn2 ( mp_cmd_reset_n_2 ), //SOFT NET
|
| 1397 |
|
|
.iavstcmdresetn3 ( mp_cmd_reset_n_3 ), //SOFT NET
|
| 1398 |
|
|
.iavstcmdresetn4 ( mp_cmd_reset_n_4 ), //SOFT NET
|
| 1399 |
|
|
.iavstcmdresetn5 ( mp_cmd_reset_n_5 ), //SOFT NET
|
| 1400 |
|
|
.iavstcmddata0 ( i_avst_cmd_data_0 ), //SOFT NET
|
| 1401 |
|
|
.iavstcmddata1 ( i_avst_cmd_data_1 ), //SOFT NET
|
| 1402 |
|
|
.iavstcmddata2 ( i_avst_cmd_data_2 ), //SOFT NET
|
| 1403 |
|
|
.iavstcmddata3 ( i_avst_cmd_data_3 ), //SOFT NET
|
| 1404 |
|
|
.iavstcmddata4 ( i_avst_cmd_data_4 ), //SOFT NET
|
| 1405 |
|
|
.iavstcmddata5 ( i_avst_cmd_data_5 ), //SOFT NET
|
| 1406 |
|
|
.oammready0 ( o_a_mm_ready_0 ), //SOFT NET
|
| 1407 |
|
|
.oammready1 ( o_a_mm_ready_1 ), //SOFT NET
|
| 1408 |
|
|
.oammready2 ( o_a_mm_ready_2 ), //SOFT NET
|
| 1409 |
|
|
.oammready3 ( o_a_mm_ready_3 ), //SOFT NET
|
| 1410 |
|
|
.oammready4 ( o_a_mm_ready_4 ), //SOFT NET
|
| 1411 |
|
|
.oammready5 ( o_a_mm_ready_5 ), //SOFT NET
|
| 1412 |
|
|
.iavstwrackready0 ( 1'b1 ), //INTERNAL USE
|
| 1413 |
|
|
.iavstwrackready1 ( 1'b1 ), //INTERNAL USE
|
| 1414 |
|
|
.iavstwrackready2 ( 1'b1 ), //INTERNAL USE
|
| 1415 |
|
|
.iavstwrackready3 ( 1'b1 ), //INTERNAL USE
|
| 1416 |
|
|
.iavstwrackready4 ( 1'b1 ), //INTERNAL USE
|
| 1417 |
|
|
.iavstwrackready5 ( 1'b1 ), //INTERNAL USE
|
| 1418 |
|
|
.owrackavstvalid0 ( o_wrack_avst_valid_0 ), //SOFT NET
|
| 1419 |
|
|
.owrackavstvalid1 ( o_wrack_avst_valid_1 ), //SOFT NET
|
| 1420 |
|
|
.owrackavstvalid2 ( o_wrack_avst_valid_2 ), //SOFT NET
|
| 1421 |
|
|
.owrackavstvalid3 ( o_wrack_avst_valid_3 ), //SOFT NET
|
| 1422 |
|
|
.owrackavstvalid4 ( o_wrack_avst_valid_4 ), //SOFT NET
|
| 1423 |
|
|
.owrackavstvalid5 ( o_wrack_avst_valid_5 ), //SOFT NET
|
| 1424 |
|
|
.owrackavstdata0 ( o_wrack_avst_data_0 ), //SOFT NET
|
| 1425 |
|
|
.owrackavstdata1 ( o_wrack_avst_data_1 ), //SOFT NET
|
| 1426 |
|
|
.owrackavstdata2 ( o_wrack_avst_data_2 ), //SOFT NET
|
| 1427 |
|
|
.owrackavstdata3 ( o_wrack_avst_data_3 ), //SOFT NET
|
| 1428 |
|
|
.owrackavstdata4 ( o_wrack_avst_data_4 ), //SOFT NET
|
| 1429 |
|
|
.owrackavstdata5 ( o_wrack_avst_data_5 ), //SOFT NET
|
| 1430 |
|
|
.iavstrdclk0 ( mp_rfifo_clk_0 ), //SOFT NET
|
| 1431 |
|
|
.iavstrdclk1 ( mp_rfifo_clk_1 ), //SOFT NET
|
| 1432 |
|
|
.iavstrdclk2 ( mp_rfifo_clk_2 ), //SOFT NET
|
| 1433 |
|
|
.iavstrdclk3 ( mp_rfifo_clk_3 ), //SOFT NET
|
| 1434 |
|
|
.iavstrdresetn0 ( mp_rfifo_reset_n_0 ), //SOFT NET
|
| 1435 |
|
|
.iavstrdresetn1 ( mp_rfifo_reset_n_1 ), //SOFT NET
|
| 1436 |
|
|
.iavstrdresetn2 ( mp_rfifo_reset_n_2 ), //SOFT NET
|
| 1437 |
|
|
.iavstrdresetn3 ( mp_rfifo_reset_n_3 ), //SOFT NET
|
| 1438 |
|
|
.ordavstvalid0 ( o_rd_avst_valid_0 ), //SOFT NET
|
| 1439 |
|
|
.ordavstvalid1 ( o_rd_avst_valid_1 ), //SOFT NET
|
| 1440 |
|
|
.ordavstvalid2 ( o_rd_avst_valid_2 ), //SOFT NET
|
| 1441 |
|
|
.ordavstvalid3 ( o_rd_avst_valid_3 ), //SOFT NET
|
| 1442 |
|
|
.ordavstdata0 ( o_rd_avst_data_0 ), //SOFT NET
|
| 1443 |
|
|
.ordavstdata1 ( o_rd_avst_data_1 ), //SOFT NET
|
| 1444 |
|
|
.ordavstdata2 ( o_rd_avst_data_2 ), //SOFT NET
|
| 1445 |
|
|
.ordavstdata3 ( o_rd_avst_data_3 ), //SOFT NET
|
| 1446 |
|
|
.iavstrdready0 ( 1'b1 ), //INTERNAL USE
|
| 1447 |
|
|
.iavstrdready1 ( 1'b1 ), //INTERNAL USE
|
| 1448 |
|
|
.iavstrdready2 ( 1'b1 ), //INTERNAL USE
|
| 1449 |
|
|
.iavstrdready3 ( 1'b1 ), //INTERNAL USE
|
| 1450 |
|
|
.iavstwrclk0 ( mp_wfifo_clk_0 ), //SOFT NET
|
| 1451 |
|
|
.iavstwrclk1 ( mp_wfifo_clk_1 ), //SOFT NET
|
| 1452 |
|
|
.iavstwrclk2 ( mp_wfifo_clk_2 ), //SOFT NET
|
| 1453 |
|
|
.iavstwrclk3 ( mp_wfifo_clk_3 ), //SOFT NET
|
| 1454 |
|
|
.iavstwrresetn0 ( mp_wfifo_reset_n_0 ), //SOFT NET
|
| 1455 |
|
|
.iavstwrresetn1 ( mp_wfifo_reset_n_1 ), //SOFT NET
|
| 1456 |
|
|
.iavstwrresetn2 ( mp_wfifo_reset_n_2 ), //SOFT NET
|
| 1457 |
|
|
.iavstwrresetn3 ( mp_wfifo_reset_n_3 ), //SOFT NET
|
| 1458 |
|
|
.iavstwrdata0 ( i_avst_wr_data_0 ), //SOFT NET
|
| 1459 |
|
|
.iavstwrdata1 ( i_avst_wr_data_1 ), //SOFT NET
|
| 1460 |
|
|
.iavstwrdata2 ( i_avst_wr_data_2 ), //SOFT NET
|
| 1461 |
|
|
.iavstwrdata3 ( i_avst_wr_data_3 ), //SOFT NET
|
| 1462 |
|
|
.bondingout1 ( bonding_out_1 ), //SOFT NET
|
| 1463 |
|
|
.bondingin1 ( bonding_in_1 ), //SOFT NET
|
| 1464 |
|
|
.bondingout2 ( bonding_out_2 ), //SOFT NET
|
| 1465 |
|
|
.bondingin2 ( bonding_in_2 ), //SOFT NET
|
| 1466 |
|
|
.bondingout3 ( bonding_out_3 ), //SOFT NET
|
| 1467 |
|
|
.bondingin3 ( bonding_in_3 ), //SOFT NET
|
| 1468 |
|
|
.localrefreshreq ( local_refresh_req ), //SOFT NET
|
| 1469 |
|
|
.localrefreshchip ( local_refresh_chip_wire ), //SOFT NET
|
| 1470 |
|
|
.localdeeppowerdnreq ( local_deep_powerdn_req ), //SOFT NET
|
| 1471 |
|
|
.localdeeppowerdnchip ( local_deep_powerdn_chip_wire ), //SOFT NET
|
| 1472 |
|
|
.localselfrfshreq ( local_self_rfsh_req ), //SOFT NET
|
| 1473 |
|
|
.localselfrfshchip ( local_self_rfsh_chip_wire ), //SOFT NET
|
| 1474 |
|
|
.localrefreshack ( local_refresh_ack ), //SOFT NET
|
| 1475 |
|
|
.localdeeppowerdnack ( local_deep_powerdn_ack ), //SOFT NET
|
| 1476 |
|
|
.localpowerdownack ( local_powerdn_ack ), //SOFT NET
|
| 1477 |
|
|
.localselfrfshack ( local_self_rfsh_ack ), //SOFT NET
|
| 1478 |
|
|
.localstsctlempty ( local_sts_ctl_empty ),
|
| 1479 |
|
|
.ctlinitreq ( ctl_init_req ),
|
| 1480 |
|
|
.localinitdone ( local_init_done ), //SOFT NET
|
| 1481 |
|
|
.afirstn ( afi_rst_n ), //HARD NET
|
| 1482 |
|
|
.afiba ( afi_ba ), //HARD NET
|
| 1483 |
|
|
.afiaddr ( afi_addr ), //HARD NET
|
| 1484 |
|
|
.aficke ( afi_cke ), //HARD NET
|
| 1485 |
|
|
.aficsn ( afi_cs_n ), //HARD NET
|
| 1486 |
|
|
.afirasn ( afi_ras_n ), //HARD NET
|
| 1487 |
|
|
.aficasn ( afi_cas_n ), //HARD NET
|
| 1488 |
|
|
.afiwen ( afi_we_n ), //HARD NET
|
| 1489 |
|
|
.afiodt ( afi_odt ), //HARD NET
|
| 1490 |
|
|
.afiwlat ( afi_wlat ), //HARD NET
|
| 1491 |
|
|
.afidqsburst ( afi_dqs_burst ), //HARD NET
|
| 1492 |
|
|
.afidm ( afi_dm_int ), //HARD NET
|
| 1493 |
|
|
.afiwdata ( afi_wdata_int ), //HARD NET
|
| 1494 |
|
|
.afiwdatavalid ( afi_wdata_valid ), //HARD NET
|
| 1495 |
|
|
.afirdataen ( afi_rdata_en ), //HARD NET
|
| 1496 |
|
|
.afirdataenfull ( afi_rdata_en_full ), //HARD NET
|
| 1497 |
|
|
.afirdata ( afi_rdata_int ), //HARD NET
|
| 1498 |
|
|
.afirdatavalid ( afi_rdata_valid ), //HARD NET
|
| 1499 |
|
|
.ctlcalsuccess ( afi_cal_success ), //HARD NET
|
| 1500 |
|
|
.ctlcalfail ( afi_cal_fail ), //HARD NET
|
| 1501 |
|
|
.ctlcalreq ( afi_cal_req ), //SOFT NET
|
| 1502 |
|
|
.ctlcalbytelaneseln ( afi_cal_byte_lane_sel_n ), //SOFT NET
|
| 1503 |
|
|
.ctlmemclkdisable ( afi_mem_clk_disable ), //HARD NET
|
| 1504 |
|
|
.afictlrefreshdone ( afi_ctl_refresh_done ), //SOFT NET
|
| 1505 |
|
|
.afiseqbusy ( afi_seq_busy_int ), //SOFT NET
|
| 1506 |
|
|
.afictllongidle ( afi_ctl_long_idle ), //SOFT NET
|
| 1507 |
|
|
.mmrclk ( csr_clk ), //SOFT NET
|
| 1508 |
|
|
.mmrresetn ( csr_reset_n ), //SOFT NET
|
| 1509 |
|
|
.mmrreadreq ( csr_read_req ), //SOFT NET
|
| 1510 |
|
|
.mmrwritereq ( csr_write_req ), //SOFT NET
|
| 1511 |
|
|
.mmrburstcount ( 2'b01 ), //SOFT NET
|
| 1512 |
|
|
.mmrburstbegin ( 1'b1 ), //SOFT NET
|
| 1513 |
|
|
.mmraddr ( csr_addr ), //SOFT NET
|
| 1514 |
|
|
.mmrwdata ( csr_wdata ), //SOFT NET
|
| 1515 |
|
|
.mmrbe ( csr_be ), //SOFT NET
|
| 1516 |
|
|
.mmrrdata ( csr_rdata ), //SOFT NET
|
| 1517 |
|
|
.mmrrdatavalid ( csr_rdata_valid ), //SOFT NET
|
| 1518 |
|
|
.mmrwaitrequest ( csr_waitrequest ), //SOFT NET
|
| 1519 |
|
|
.scclk ( 1'b0 ), //INTERNAL USE
|
| 1520 |
|
|
.scresetn ( 1'b1 ), //INTERNAL USE
|
| 1521 |
|
|
.screadreq ( 1'b0 ), //INTERNAL USE
|
| 1522 |
|
|
.scwritereq ( 1'b0 ), //INTERNAL USE
|
| 1523 |
|
|
.scburstcount ( 2'b0 ), //INTERNAL USE
|
| 1524 |
|
|
.scburstbegin ( 1'b0 ), //INTERNAL USE
|
| 1525 |
|
|
.scaddr ( 10'b0000000000 ), //INTERNAL USE
|
| 1526 |
|
|
.scwdata ( 8'b0 ), //INTERNAL USE
|
| 1527 |
|
|
.scbe ( 1'b0 ), //INTERNAL USE
|
| 1528 |
|
|
.scrdata ( ), //INTERNAL USE
|
| 1529 |
|
|
.scrdatavalid ( ), //INTERNAL USE
|
| 1530 |
|
|
.scwaitrequest ( ), //INTERNAL USE
|
| 1531 |
|
|
.dramconfig ( cfg_dramconfig_wire ), //SOFT NET
|
| 1532 |
|
|
.cfgcaswrlat ( cfg_caswrlat_wire ), //SOFT NET
|
| 1533 |
|
|
.cfgaddlat ( cfg_addlat_wire ), //SOFT NET
|
| 1534 |
|
|
.cfgtcl ( cfg_tcl_wire ), //SOFT NET
|
| 1535 |
|
|
.cfgtrfc ( cfg_trfc_wire ), //SOFT NET
|
| 1536 |
|
|
.cfgtrefi ( cfg_trefi_wire ), //SOFT NET
|
| 1537 |
|
|
.cfgtwr ( cfg_twr_wire ), //SOFT NET
|
| 1538 |
|
|
.cfgtmrd ( cfg_tmrd_wire ), //SOFT NET
|
| 1539 |
|
|
.cfgcoladdrwidth ( cfg_coladdrwidth_wire ), //SOFT NET
|
| 1540 |
|
|
.cfgrowaddrwidth ( cfg_rowaddrwidth_wire ), //SOFT NET
|
| 1541 |
|
|
.cfgbankaddrwidth ( cfg_bankaddrwidth_wire ), //SOFT NET
|
| 1542 |
|
|
.cfgcsaddrwidth ( cfg_csaddrwidth_wire ), //SOFT NET
|
| 1543 |
|
|
.cfginterfacewidth ( cfg_interfacewidth_wire ), //SOFT NET
|
| 1544 |
|
|
.cfgdevicewidth ( cfg_devicewidth_wire ), //SOFT NET
|
| 1545 |
|
|
.scanenable ( 1'b0 ), //INTERNAL USE
|
| 1546 |
|
|
.ctlclk ( ctl_clk ), //HARD NET
|
| 1547 |
|
|
.ctlresetn ( ctl_reset_n ) //HARD NET
|
| 1548 |
|
|
);
|
| 1549 |
|
|
|
| 1550 |
|
|
// Those that mark with // SYTH & SIM is used to force MMR signals in simulation
|
| 1551 |
|
|
// Those that mark with // SYTH ONLY is only used for Quartus sythesis
|
| 1552 |
|
|
defparam hmc_inst.attr_counter_one_mask = VECT_ATTR_COUNTER_ONE_MASK; //SYTH & SIM
|
| 1553 |
|
|
defparam hmc_inst.attr_counter_one_match = VECT_ATTR_COUNTER_ONE_MATCH; //SYTH & SIM
|
| 1554 |
|
|
defparam hmc_inst.attr_counter_one_reset = ENUM_ATTR_COUNTER_ONE_RESET; //SYTH & SIM
|
| 1555 |
|
|
defparam hmc_inst.attr_counter_zero_mask = VECT_ATTR_COUNTER_ZERO_MASK; //SYTH & SIM
|
| 1556 |
|
|
defparam hmc_inst.attr_counter_zero_match = VECT_ATTR_COUNTER_ZERO_MATCH; //SYTH & SIM
|
| 1557 |
|
|
defparam hmc_inst.attr_counter_zero_reset = ENUM_ATTR_COUNTER_ZERO_RESET; //SYTH & SIM
|
| 1558 |
|
|
defparam hmc_inst.attr_debug_select_byte = VECT_ATTR_DEBUG_SELECT_BYTE; //SYTH & SIM
|
| 1559 |
|
|
defparam hmc_inst.attr_static_config_valid = ENUM_ATTR_STATIC_CONFIG_VALID; //SYTH & SIM
|
| 1560 |
|
|
defparam hmc_inst.auto_pch_enable_0 = ENUM_AUTO_PCH_ENABLE_0; //SYTH & SIM
|
| 1561 |
|
|
defparam hmc_inst.auto_pch_enable_1 = ENUM_AUTO_PCH_ENABLE_1; //SYTH & SIM
|
| 1562 |
|
|
defparam hmc_inst.auto_pch_enable_2 = ENUM_AUTO_PCH_ENABLE_2; //SYTH & SIM
|
| 1563 |
|
|
defparam hmc_inst.auto_pch_enable_3 = ENUM_AUTO_PCH_ENABLE_3; //SYTH & SIM
|
| 1564 |
|
|
defparam hmc_inst.auto_pch_enable_4 = ENUM_AUTO_PCH_ENABLE_4; //SYTH & SIM
|
| 1565 |
|
|
defparam hmc_inst.auto_pch_enable_5 = ENUM_AUTO_PCH_ENABLE_5; //SYTH & SIM
|
| 1566 |
|
|
defparam hmc_inst.cal_req = ENUM_CAL_REQ; //SYTH & SIM
|
| 1567 |
|
|
defparam hmc_inst.cfg_burst_length = ENUM_CFG_BURST_LENGTH; //SYTH & SIM
|
| 1568 |
|
|
defparam hmc_inst.cfg_interface_width = ENUM_CFG_INTERFACE_WIDTH; //SYTH & SIM
|
| 1569 |
|
|
defparam hmc_inst.cfg_self_rfsh_exit_cycles = ENUM_CFG_SELF_RFSH_EXIT_CYCLES; //SYTH & SIM
|
| 1570 |
|
|
defparam hmc_inst.cfg_starve_limit = ENUM_CFG_STARVE_LIMIT; //SYTH & SIM
|
| 1571 |
|
|
defparam hmc_inst.cfg_type = ENUM_CFG_TYPE; //SYTH & SIM
|
| 1572 |
|
|
defparam hmc_inst.clock_off_0 = ENUM_CLOCK_OFF_0; //SIM ONLY
|
| 1573 |
|
|
defparam hmc_inst.clock_off_1 = ENUM_CLOCK_OFF_1; //SIM ONLY
|
| 1574 |
|
|
defparam hmc_inst.clock_off_2 = ENUM_CLOCK_OFF_2; //SIM ONLY
|
| 1575 |
|
|
defparam hmc_inst.clock_off_3 = ENUM_CLOCK_OFF_3; //SIM ONLY
|
| 1576 |
|
|
defparam hmc_inst.clock_off_4 = ENUM_CLOCK_OFF_4; //SIM ONLY
|
| 1577 |
|
|
defparam hmc_inst.clock_off_5 = ENUM_CLOCK_OFF_5; //SIM ONLY
|
| 1578 |
|
|
defparam hmc_inst.clr_intr = ENUM_CLR_INTR; //SIM ONLY
|
| 1579 |
|
|
defparam hmc_inst.cmd_port_in_use_0 = ENUM_CMD_PORT_IN_USE_0; //SYTH ONLY
|
| 1580 |
|
|
defparam hmc_inst.cmd_port_in_use_1 = ENUM_CMD_PORT_IN_USE_1; //SYTH ONLY
|
| 1581 |
|
|
defparam hmc_inst.cmd_port_in_use_2 = ENUM_CMD_PORT_IN_USE_2; //SYTH ONLY
|
| 1582 |
|
|
defparam hmc_inst.cmd_port_in_use_3 = ENUM_CMD_PORT_IN_USE_3; //SYTH ONLY
|
| 1583 |
|
|
defparam hmc_inst.cmd_port_in_use_4 = ENUM_CMD_PORT_IN_USE_4; //SYTH ONLY
|
| 1584 |
|
|
defparam hmc_inst.cmd_port_in_use_5 = ENUM_CMD_PORT_IN_USE_5; //SYTH ONLY
|
| 1585 |
|
|
defparam hmc_inst.cport0_rdy_almost_full = ENUM_CPORT0_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1586 |
|
|
defparam hmc_inst.cport0_rfifo_map = ENUM_CPORT0_RFIFO_MAP; //SYTH & SIM
|
| 1587 |
|
|
defparam hmc_inst.cport0_type = ENUM_CPORT0_TYPE; //SYTH & SIM
|
| 1588 |
|
|
defparam hmc_inst.cport0_wfifo_map = ENUM_CPORT0_WFIFO_MAP; //SYTH & SIM
|
| 1589 |
|
|
defparam hmc_inst.cport1_rdy_almost_full = ENUM_CPORT1_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1590 |
|
|
defparam hmc_inst.cport1_rfifo_map = ENUM_CPORT1_RFIFO_MAP; //SYTH & SIM
|
| 1591 |
|
|
defparam hmc_inst.cport1_type = ENUM_CPORT1_TYPE; //SYTH & SIM
|
| 1592 |
|
|
defparam hmc_inst.cport1_wfifo_map = ENUM_CPORT1_WFIFO_MAP; //SYTH & SIM
|
| 1593 |
|
|
defparam hmc_inst.cport2_rdy_almost_full = ENUM_CPORT2_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1594 |
|
|
defparam hmc_inst.cport2_rfifo_map = ENUM_CPORT2_RFIFO_MAP; //SYTH & SIM
|
| 1595 |
|
|
defparam hmc_inst.cport2_type = ENUM_CPORT2_TYPE; //SYTH & SIM
|
| 1596 |
|
|
defparam hmc_inst.cport2_wfifo_map = ENUM_CPORT2_WFIFO_MAP; //SYTH & SIM
|
| 1597 |
|
|
defparam hmc_inst.cport3_rdy_almost_full = ENUM_CPORT3_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1598 |
|
|
defparam hmc_inst.cport3_rfifo_map = ENUM_CPORT3_RFIFO_MAP; //SYTH & SIM
|
| 1599 |
|
|
defparam hmc_inst.cport3_type = ENUM_CPORT3_TYPE; //SYTH & SIM
|
| 1600 |
|
|
defparam hmc_inst.cport3_wfifo_map = ENUM_CPORT3_WFIFO_MAP; //SYTH & SIM
|
| 1601 |
|
|
defparam hmc_inst.cport4_rdy_almost_full = ENUM_CPORT4_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1602 |
|
|
defparam hmc_inst.cport4_rfifo_map = ENUM_CPORT4_RFIFO_MAP; //SYTH & SIM
|
| 1603 |
|
|
defparam hmc_inst.cport4_type = ENUM_CPORT4_TYPE; //SYTH & SIM
|
| 1604 |
|
|
defparam hmc_inst.cport4_wfifo_map = ENUM_CPORT4_WFIFO_MAP; //SYTH & SIM
|
| 1605 |
|
|
defparam hmc_inst.cport5_rdy_almost_full = ENUM_CPORT5_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1606 |
|
|
defparam hmc_inst.cport5_rfifo_map = ENUM_CPORT5_RFIFO_MAP; //SYTH & SIM
|
| 1607 |
|
|
defparam hmc_inst.cport5_type = ENUM_CPORT5_TYPE; //SYTH & SIM
|
| 1608 |
|
|
defparam hmc_inst.cport5_wfifo_map = ENUM_CPORT5_WFIFO_MAP; //SYTH & SIM
|
| 1609 |
|
|
defparam hmc_inst.ctl_addr_order = ENUM_CTL_ADDR_ORDER; //SYTH & SIM
|
| 1610 |
|
|
defparam hmc_inst.ctl_ecc_enabled = ENUM_CTL_ECC_ENABLED; //SYTH & SIM
|
| 1611 |
|
|
defparam hmc_inst.ctl_ecc_rmw_enabled = ENUM_CTL_ECC_RMW_ENABLED; //SYTH & SIM
|
| 1612 |
|
|
defparam hmc_inst.ctl_regdimm_enabled = ENUM_CTL_REGDIMM_ENABLED; //SIM ONLY
|
| 1613 |
|
|
defparam hmc_inst.ctl_usr_refresh = ENUM_CTL_USR_REFRESH; //SYTH & SIM
|
| 1614 |
|
|
defparam hmc_inst.ctrl_width = ENUM_CTRL_WIDTH; //SYTH & SIM
|
| 1615 |
|
|
defparam hmc_inst.cyc_to_rld_jars_0 = INTG_CYC_TO_RLD_JARS_0; //SYTH & SIM
|
| 1616 |
|
|
defparam hmc_inst.cyc_to_rld_jars_1 = INTG_CYC_TO_RLD_JARS_1; //SYTH & SIM
|
| 1617 |
|
|
defparam hmc_inst.cyc_to_rld_jars_2 = INTG_CYC_TO_RLD_JARS_2; //SYTH & SIM
|
| 1618 |
|
|
defparam hmc_inst.cyc_to_rld_jars_3 = INTG_CYC_TO_RLD_JARS_3; //SYTH & SIM
|
| 1619 |
|
|
defparam hmc_inst.cyc_to_rld_jars_4 = INTG_CYC_TO_RLD_JARS_4; //SYTH & SIM
|
| 1620 |
|
|
defparam hmc_inst.cyc_to_rld_jars_5 = INTG_CYC_TO_RLD_JARS_5; //SYTH & SIM
|
| 1621 |
|
|
defparam hmc_inst.power_saving_exit_cycles = INTG_POWER_SAVING_EXIT_CYCLES; //SYTH & SIM
|
| 1622 |
|
|
defparam hmc_inst.mem_clk_entry_cycles = INTG_MEM_CLK_ENTRY_CYCLES; //SYTH & SIM
|
| 1623 |
|
|
defparam hmc_inst.priority_remap = INTG_PRIORITY_REMAP; //SIM ONLY
|
| 1624 |
|
|
defparam hmc_inst.enable_burst_interrupt = ENUM_ENABLE_BURST_INTERRUPT; //SYTH & SIM
|
| 1625 |
|
|
defparam hmc_inst.enable_burst_terminate = ENUM_ENABLE_BURST_TERMINATE; //SYTH & SIM
|
| 1626 |
|
|
defparam hmc_inst.delay_bonding = ENUM_DELAY_BONDING; //SYTH & SIM
|
| 1627 |
|
|
defparam hmc_inst.dfx_bypass_enable = ENUM_DFX_BYPASS_ENABLE; //SYTH & SIM
|
| 1628 |
|
|
defparam hmc_inst.disable_merging = ENUM_DISABLE_MERGING; //SIM ONLY
|
| 1629 |
|
|
defparam hmc_inst.ecc_dq_width = ENUM_ECC_DQ_WIDTH; //SYTH ONLY
|
| 1630 |
|
|
defparam hmc_inst.enable_atpg = ENUM_ENABLE_ATPG; //SYTH & SIM
|
| 1631 |
|
|
defparam hmc_inst.enable_bonding_0 = ENUM_ENABLE_BONDING_0; //SYTH & SIM
|
| 1632 |
|
|
defparam hmc_inst.enable_bonding_1 = ENUM_ENABLE_BONDING_1; //SYTH & SIM
|
| 1633 |
|
|
defparam hmc_inst.enable_bonding_2 = ENUM_ENABLE_BONDING_2; //SYTH & SIM
|
| 1634 |
|
|
defparam hmc_inst.enable_bonding_3 = ENUM_ENABLE_BONDING_3; //SYTH & SIM
|
| 1635 |
|
|
defparam hmc_inst.enable_bonding_4 = ENUM_ENABLE_BONDING_4; //SYTH & SIM
|
| 1636 |
|
|
defparam hmc_inst.enable_bonding_5 = ENUM_ENABLE_BONDING_5; //SYTH & SIM
|
| 1637 |
|
|
defparam hmc_inst.enable_bonding_wrapback = ENUM_ENABLE_BONDING_WRAPBACK; //SYTH & SIM
|
| 1638 |
|
|
defparam hmc_inst.enable_dqs_tracking = ENUM_ENABLE_DQS_TRACKING; //SYTH & SIM
|
| 1639 |
|
|
defparam hmc_inst.enable_ecc_code_overwrites = ENUM_ENABLE_ECC_CODE_OVERWRITES; //SYTH & SIM
|
| 1640 |
|
|
defparam hmc_inst.enable_fast_exit_ppd = ENUM_ENABLE_FAST_EXIT_PPD; //SYTH ONLY
|
| 1641 |
|
|
defparam hmc_inst.enable_intr = ENUM_ENABLE_INTR; //SYTH & SIM
|
| 1642 |
|
|
defparam hmc_inst.enable_no_dm = ENUM_ENABLE_NO_DM; //SYTH & SIM
|
| 1643 |
|
|
defparam hmc_inst.enable_pipelineglobal = ENUM_ENABLE_PIPELINEGLOBAL; //SYTH & SIM
|
| 1644 |
|
|
defparam hmc_inst.extra_ctl_clk_act_to_act = INTG_EXTRA_CTL_CLK_ACT_TO_ACT; //SYTH & SIM
|
| 1645 |
|
|
defparam hmc_inst.extra_ctl_clk_act_to_act_diff_bank = INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK; //SYTH & SIM
|
| 1646 |
|
|
defparam hmc_inst.extra_ctl_clk_act_to_pch = INTG_EXTRA_CTL_CLK_ACT_TO_PCH; //SYTH & SIM
|
| 1647 |
|
|
defparam hmc_inst.extra_ctl_clk_act_to_rdwr = INTG_EXTRA_CTL_CLK_ACT_TO_RDWR; //SYTH & SIM
|
| 1648 |
|
|
defparam hmc_inst.extra_ctl_clk_arf_period = INTG_EXTRA_CTL_CLK_ARF_PERIOD; //SYTH & SIM
|
| 1649 |
|
|
defparam hmc_inst.extra_ctl_clk_arf_to_valid = INTG_EXTRA_CTL_CLK_ARF_TO_VALID; //SYTH & SIM
|
| 1650 |
|
|
defparam hmc_inst.extra_ctl_clk_four_act_to_act = INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT; //SYTH & SIM
|
| 1651 |
|
|
defparam hmc_inst.extra_ctl_clk_pch_all_to_valid = INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID; //SYTH & SIM
|
| 1652 |
|
|
defparam hmc_inst.extra_ctl_clk_pch_to_valid = INTG_EXTRA_CTL_CLK_PCH_TO_VALID; //SYTH & SIM
|
| 1653 |
|
|
defparam hmc_inst.extra_ctl_clk_pdn_period = INTG_EXTRA_CTL_CLK_PDN_PERIOD; //SYTH & SIM
|
| 1654 |
|
|
defparam hmc_inst.extra_ctl_clk_pdn_to_valid = INTG_EXTRA_CTL_CLK_PDN_TO_VALID; //SYTH & SIM
|
| 1655 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_ap_to_valid = INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID; //SYTH & SIM
|
| 1656 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_pch = INTG_EXTRA_CTL_CLK_RD_TO_PCH; //SYTH & SIM
|
| 1657 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_rd = INTG_EXTRA_CTL_CLK_RD_TO_RD; //SYTH & SIM
|
| 1658 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_rd_diff_chip = INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP; //SYTH & SIM
|
| 1659 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_wr = INTG_EXTRA_CTL_CLK_RD_TO_WR; //SYTH & SIM
|
| 1660 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_wr_bc = INTG_EXTRA_CTL_CLK_RD_TO_WR_BC; //SYTH & SIM
|
| 1661 |
|
|
defparam hmc_inst.extra_ctl_clk_rd_to_wr_diff_chip = INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP; //SYTH & SIM
|
| 1662 |
|
|
defparam hmc_inst.extra_ctl_clk_srf_to_valid = INTG_EXTRA_CTL_CLK_SRF_TO_VALID; //SYTH & SIM
|
| 1663 |
|
|
defparam hmc_inst.extra_ctl_clk_srf_to_zq_cal = INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL; //SYTH & SIM
|
| 1664 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_ap_to_valid = INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID; //SYTH & SIM
|
| 1665 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_pch = INTG_EXTRA_CTL_CLK_WR_TO_PCH; //SYTH & SIM
|
| 1666 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_rd = INTG_EXTRA_CTL_CLK_WR_TO_RD; //SYTH & SIM
|
| 1667 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_rd_bc = INTG_EXTRA_CTL_CLK_WR_TO_RD_BC; //SYTH & SIM
|
| 1668 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_rd_diff_chip = INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP; //SYTH & SIM
|
| 1669 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_wr = INTG_EXTRA_CTL_CLK_WR_TO_WR; //SYTH & SIM
|
| 1670 |
|
|
defparam hmc_inst.extra_ctl_clk_wr_to_wr_diff_chip = INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP; //SYTH & SIM
|
| 1671 |
|
|
defparam hmc_inst.ganged_arf = ENUM_GANGED_ARF; //SIM ONLY
|
| 1672 |
|
|
defparam hmc_inst.gen_dbe = ENUM_GEN_DBE; //SIM ONLY
|
| 1673 |
|
|
defparam hmc_inst.gen_sbe = ENUM_GEN_SBE; //SIM ONLY
|
| 1674 |
|
|
defparam hmc_inst.inc_sync = ENUM_INC_SYNC; //SYTH & SIM
|
| 1675 |
|
|
defparam hmc_inst.local_if_cs_width = ENUM_LOCAL_IF_CS_WIDTH; //SYTH & SIM
|
| 1676 |
|
|
defparam hmc_inst.mask_corr_dropped_intr = ENUM_MASK_CORR_DROPPED_INTR; //SYTH & SIM
|
| 1677 |
|
|
defparam hmc_inst.mask_dbe_intr = ENUM_MASK_DBE_INTR; //SYTH & SIM
|
| 1678 |
|
|
defparam hmc_inst.mask_sbe_intr = ENUM_MASK_SBE_INTR; //SYTH & SIM
|
| 1679 |
|
|
defparam hmc_inst.mem_auto_pd_cycles = INTG_MEM_AUTO_PD_CYCLES; //SYTH & SIM
|
| 1680 |
|
|
defparam hmc_inst.mem_if_al = ENUM_MEM_IF_AL; //SYTH & SIM
|
| 1681 |
|
|
defparam hmc_inst.mem_if_bankaddr_width = ENUM_MEM_IF_BANKADDR_WIDTH; //SYTH & SIM
|
| 1682 |
|
|
defparam hmc_inst.mem_if_burstlength = ENUM_MEM_IF_BURSTLENGTH; //SYTH ONLY
|
| 1683 |
|
|
defparam hmc_inst.mem_if_coladdr_width = ENUM_MEM_IF_COLADDR_WIDTH; //SYTH & SIM
|
| 1684 |
|
|
defparam hmc_inst.mem_if_cs_per_rank = ENUM_MEM_IF_CS_PER_RANK; //SYTH ONLY
|
| 1685 |
|
|
defparam hmc_inst.mem_if_cs_width = ENUM_MEM_IF_CS_WIDTH; //SYTH ONLY
|
| 1686 |
|
|
defparam hmc_inst.mem_if_dq_per_chip = ENUM_MEM_IF_DQ_PER_CHIP; //SYTH ONLY
|
| 1687 |
|
|
defparam hmc_inst.mem_if_dqs_width = ENUM_MEM_IF_DQS_WIDTH; //SYTH & SIM
|
| 1688 |
|
|
defparam hmc_inst.mem_if_dwidth = ENUM_MEM_IF_DWIDTH; //SYTH ONLY
|
| 1689 |
|
|
defparam hmc_inst.mem_if_memtype = ENUM_MEM_IF_MEMTYPE; //SYTH ONLY
|
| 1690 |
|
|
defparam hmc_inst.mem_if_rowaddr_width = ENUM_MEM_IF_ROWADDR_WIDTH; //SYTH & SIM
|
| 1691 |
|
|
defparam hmc_inst.mem_if_speedbin = ENUM_MEM_IF_SPEEDBIN; //SYTH ONLY
|
| 1692 |
|
|
defparam hmc_inst.mem_if_tccd = ENUM_MEM_IF_TCCD; //SYTH & SIM
|
| 1693 |
|
|
defparam hmc_inst.mem_if_tcl = ENUM_MEM_IF_TCL; //SYTH & SIM
|
| 1694 |
|
|
defparam hmc_inst.mem_if_tcwl = ENUM_MEM_IF_TCWL; //SYTH & SIM
|
| 1695 |
|
|
defparam hmc_inst.mem_if_tfaw = ENUM_MEM_IF_TFAW; //SYTH & SIM
|
| 1696 |
|
|
defparam hmc_inst.mem_if_tmrd = ENUM_MEM_IF_TMRD; //SYTH & SIM
|
| 1697 |
|
|
defparam hmc_inst.mem_if_tras = ENUM_MEM_IF_TRAS; //SYTH & SIM
|
| 1698 |
|
|
defparam hmc_inst.mem_if_trc = ENUM_MEM_IF_TRC; //SYTH & SIM
|
| 1699 |
|
|
defparam hmc_inst.mem_if_trcd = ENUM_MEM_IF_TRCD; //SYTH & SIM
|
| 1700 |
|
|
defparam hmc_inst.mem_if_trefi = INTG_MEM_IF_TREFI; //SYTH & SIM
|
| 1701 |
|
|
defparam hmc_inst.mem_if_trfc = INTG_MEM_IF_TRFC; //SYTH & SIM
|
| 1702 |
|
|
defparam hmc_inst.mem_if_trp = ENUM_MEM_IF_TRP; //SYTH & SIM
|
| 1703 |
|
|
defparam hmc_inst.mem_if_trrd = ENUM_MEM_IF_TRRD; //SYTH & SIM
|
| 1704 |
|
|
defparam hmc_inst.mem_if_trtp = ENUM_MEM_IF_TRTP; //SYTH & SIM
|
| 1705 |
|
|
defparam hmc_inst.mem_if_twr = ENUM_MEM_IF_TWR; //SYTH & SIM
|
| 1706 |
|
|
defparam hmc_inst.mem_if_twtr = ENUM_MEM_IF_TWTR; //SYTH & SIM
|
| 1707 |
|
|
defparam hmc_inst.mmr_cfg_mem_bl = ENUM_MMR_CFG_MEM_BL; //SYTH & SIM
|
| 1708 |
|
|
defparam hmc_inst.output_regd = ENUM_OUTPUT_REGD; //SYTH & SIM
|
| 1709 |
|
|
defparam hmc_inst.pdn_exit_cycles = ENUM_PDN_EXIT_CYCLES; //SYTH & SIM
|
| 1710 |
|
|
defparam hmc_inst.port0_width = ENUM_PORT0_WIDTH; //SYTH & SIM
|
| 1711 |
|
|
defparam hmc_inst.port1_width = ENUM_PORT1_WIDTH; //SYTH & SIM
|
| 1712 |
|
|
defparam hmc_inst.port2_width = ENUM_PORT2_WIDTH; //SYTH & SIM
|
| 1713 |
|
|
defparam hmc_inst.port3_width = ENUM_PORT3_WIDTH; //SYTH & SIM
|
| 1714 |
|
|
defparam hmc_inst.port4_width = ENUM_PORT4_WIDTH; //SYTH & SIM
|
| 1715 |
|
|
defparam hmc_inst.port5_width = ENUM_PORT5_WIDTH; //SYTH & SIM
|
| 1716 |
|
|
defparam hmc_inst.priority_0_0 = ENUM_PRIORITY_0_0; //SYTH ONLY
|
| 1717 |
|
|
defparam hmc_inst.priority_0_1 = ENUM_PRIORITY_0_1; //SYTH ONLY
|
| 1718 |
|
|
defparam hmc_inst.priority_0_2 = ENUM_PRIORITY_0_2; //SYTH ONLY
|
| 1719 |
|
|
defparam hmc_inst.priority_0_3 = ENUM_PRIORITY_0_3; //SYTH ONLY
|
| 1720 |
|
|
defparam hmc_inst.priority_0_4 = ENUM_PRIORITY_0_4; //SYTH ONLY
|
| 1721 |
|
|
defparam hmc_inst.priority_0_5 = ENUM_PRIORITY_0_5; //SYTH ONLY
|
| 1722 |
|
|
defparam hmc_inst.priority_1_0 = ENUM_PRIORITY_1_0; //SYTH ONLY
|
| 1723 |
|
|
defparam hmc_inst.priority_1_1 = ENUM_PRIORITY_1_1; //SYTH ONLY
|
| 1724 |
|
|
defparam hmc_inst.priority_1_2 = ENUM_PRIORITY_1_2; //SYTH ONLY
|
| 1725 |
|
|
defparam hmc_inst.priority_1_3 = ENUM_PRIORITY_1_3; //SYTH ONLY
|
| 1726 |
|
|
defparam hmc_inst.priority_1_4 = ENUM_PRIORITY_1_4; //SYTH ONLY
|
| 1727 |
|
|
defparam hmc_inst.priority_1_5 = ENUM_PRIORITY_1_5; //SYTH ONLY
|
| 1728 |
|
|
defparam hmc_inst.priority_2_0 = ENUM_PRIORITY_2_0; //SYTH ONLY
|
| 1729 |
|
|
defparam hmc_inst.priority_2_1 = ENUM_PRIORITY_2_1; //SYTH ONLY
|
| 1730 |
|
|
defparam hmc_inst.priority_2_2 = ENUM_PRIORITY_2_2; //SYTH ONLY
|
| 1731 |
|
|
defparam hmc_inst.priority_2_3 = ENUM_PRIORITY_2_3; //SYTH ONLY
|
| 1732 |
|
|
defparam hmc_inst.priority_2_4 = ENUM_PRIORITY_2_4; //SYTH ONLY
|
| 1733 |
|
|
defparam hmc_inst.priority_2_5 = ENUM_PRIORITY_2_5; //SYTH ONLY
|
| 1734 |
|
|
defparam hmc_inst.priority_3_0 = ENUM_PRIORITY_3_0; //SYTH ONLY
|
| 1735 |
|
|
defparam hmc_inst.priority_3_1 = ENUM_PRIORITY_3_1; //SYTH ONLY
|
| 1736 |
|
|
defparam hmc_inst.priority_3_2 = ENUM_PRIORITY_3_2; //SYTH ONLY
|
| 1737 |
|
|
defparam hmc_inst.priority_3_3 = ENUM_PRIORITY_3_3; //SYTH ONLY
|
| 1738 |
|
|
defparam hmc_inst.priority_3_4 = ENUM_PRIORITY_3_4; //SYTH ONLY
|
| 1739 |
|
|
defparam hmc_inst.priority_3_5 = ENUM_PRIORITY_3_5; //SYTH ONLY
|
| 1740 |
|
|
defparam hmc_inst.priority_4_0 = ENUM_PRIORITY_4_0; //SYTH ONLY
|
| 1741 |
|
|
defparam hmc_inst.priority_4_1 = ENUM_PRIORITY_4_1; //SYTH ONLY
|
| 1742 |
|
|
defparam hmc_inst.priority_4_2 = ENUM_PRIORITY_4_2; //SYTH ONLY
|
| 1743 |
|
|
defparam hmc_inst.priority_4_3 = ENUM_PRIORITY_4_3; //SYTH ONLY
|
| 1744 |
|
|
defparam hmc_inst.priority_4_4 = ENUM_PRIORITY_4_4; //SYTH ONLY
|
| 1745 |
|
|
defparam hmc_inst.priority_4_5 = ENUM_PRIORITY_4_5; //SYTH ONLY
|
| 1746 |
|
|
defparam hmc_inst.priority_5_0 = ENUM_PRIORITY_5_0; //SYTH ONLY
|
| 1747 |
|
|
defparam hmc_inst.priority_5_1 = ENUM_PRIORITY_5_1; //SYTH ONLY
|
| 1748 |
|
|
defparam hmc_inst.priority_5_2 = ENUM_PRIORITY_5_2; //SYTH ONLY
|
| 1749 |
|
|
defparam hmc_inst.priority_5_3 = ENUM_PRIORITY_5_3; //SYTH ONLY
|
| 1750 |
|
|
defparam hmc_inst.priority_5_4 = ENUM_PRIORITY_5_4; //SYTH ONLY
|
| 1751 |
|
|
defparam hmc_inst.priority_5_5 = ENUM_PRIORITY_5_5; //SYTH ONLY
|
| 1752 |
|
|
defparam hmc_inst.priority_6_0 = ENUM_PRIORITY_6_0; //SYTH ONLY
|
| 1753 |
|
|
defparam hmc_inst.priority_6_1 = ENUM_PRIORITY_6_1; //SYTH ONLY
|
| 1754 |
|
|
defparam hmc_inst.priority_6_2 = ENUM_PRIORITY_6_2; //SYTH ONLY
|
| 1755 |
|
|
defparam hmc_inst.priority_6_3 = ENUM_PRIORITY_6_3; //SYTH ONLY
|
| 1756 |
|
|
defparam hmc_inst.priority_6_4 = ENUM_PRIORITY_6_4; //SYTH ONLY
|
| 1757 |
|
|
defparam hmc_inst.priority_6_5 = ENUM_PRIORITY_6_5; //SYTH ONLY
|
| 1758 |
|
|
defparam hmc_inst.priority_7_0 = ENUM_PRIORITY_7_0; //SYTH ONLY
|
| 1759 |
|
|
defparam hmc_inst.priority_7_1 = ENUM_PRIORITY_7_1; //SYTH ONLY
|
| 1760 |
|
|
defparam hmc_inst.priority_7_2 = ENUM_PRIORITY_7_2; //SYTH ONLY
|
| 1761 |
|
|
defparam hmc_inst.priority_7_3 = ENUM_PRIORITY_7_3; //SYTH ONLY
|
| 1762 |
|
|
defparam hmc_inst.priority_7_4 = ENUM_PRIORITY_7_4; //SYTH ONLY
|
| 1763 |
|
|
defparam hmc_inst.priority_7_5 = ENUM_PRIORITY_7_5; //SYTH ONLY
|
| 1764 |
|
|
defparam hmc_inst.rcfg_static_weight_0 = ENUM_RCFG_STATIC_WEIGHT_0; //SYTH & SIM
|
| 1765 |
|
|
defparam hmc_inst.rcfg_static_weight_1 = ENUM_RCFG_STATIC_WEIGHT_1; //SYTH & SIM
|
| 1766 |
|
|
defparam hmc_inst.rcfg_static_weight_2 = ENUM_RCFG_STATIC_WEIGHT_2; //SYTH & SIM
|
| 1767 |
|
|
defparam hmc_inst.rcfg_static_weight_3 = ENUM_RCFG_STATIC_WEIGHT_3; //SYTH & SIM
|
| 1768 |
|
|
defparam hmc_inst.rcfg_static_weight_4 = ENUM_RCFG_STATIC_WEIGHT_4; //SYTH & SIM
|
| 1769 |
|
|
defparam hmc_inst.rcfg_static_weight_5 = ENUM_RCFG_STATIC_WEIGHT_5; //SYTH & SIM
|
| 1770 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_0 = INTG_RCFG_SUM_WT_PRIORITY_0; //SYTH & SIM
|
| 1771 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_1 = INTG_RCFG_SUM_WT_PRIORITY_1; //SYTH & SIM
|
| 1772 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_2 = INTG_RCFG_SUM_WT_PRIORITY_2; //SYTH & SIM
|
| 1773 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_3 = INTG_RCFG_SUM_WT_PRIORITY_3; //SYTH & SIM
|
| 1774 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_4 = INTG_RCFG_SUM_WT_PRIORITY_4; //SYTH & SIM
|
| 1775 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_5 = INTG_RCFG_SUM_WT_PRIORITY_5; //SYTH & SIM
|
| 1776 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_6 = INTG_RCFG_SUM_WT_PRIORITY_6; //SYTH & SIM
|
| 1777 |
|
|
defparam hmc_inst.rcfg_sum_wt_priority_7 = INTG_RCFG_SUM_WT_PRIORITY_7; //SYTH & SIM
|
| 1778 |
|
|
defparam hmc_inst.rcfg_user_priority_0 = ENUM_RCFG_USER_PRIORITY_0; //SYTH & SIM
|
| 1779 |
|
|
defparam hmc_inst.rcfg_user_priority_1 = ENUM_RCFG_USER_PRIORITY_1; //SYTH & SIM
|
| 1780 |
|
|
defparam hmc_inst.rcfg_user_priority_2 = ENUM_RCFG_USER_PRIORITY_2; //SYTH & SIM
|
| 1781 |
|
|
defparam hmc_inst.rcfg_user_priority_3 = ENUM_RCFG_USER_PRIORITY_3; //SYTH & SIM
|
| 1782 |
|
|
defparam hmc_inst.rcfg_user_priority_4 = ENUM_RCFG_USER_PRIORITY_4; //SYTH & SIM
|
| 1783 |
|
|
defparam hmc_inst.rcfg_user_priority_5 = ENUM_RCFG_USER_PRIORITY_5; //SYTH & SIM
|
| 1784 |
|
|
defparam hmc_inst.rd_dwidth_0 = ENUM_RD_DWIDTH_0; //SYTH ONLY
|
| 1785 |
|
|
defparam hmc_inst.rd_dwidth_1 = ENUM_RD_DWIDTH_1; //SYTH ONLY
|
| 1786 |
|
|
defparam hmc_inst.rd_dwidth_2 = ENUM_RD_DWIDTH_2; //SYTH ONLY
|
| 1787 |
|
|
defparam hmc_inst.rd_dwidth_3 = ENUM_RD_DWIDTH_3; //SYTH ONLY
|
| 1788 |
|
|
defparam hmc_inst.rd_dwidth_4 = ENUM_RD_DWIDTH_4; //SYTH ONLY
|
| 1789 |
|
|
defparam hmc_inst.rd_dwidth_5 = ENUM_RD_DWIDTH_5; //SYTH ONLY
|
| 1790 |
|
|
defparam hmc_inst.rd_fifo_in_use_0 = ENUM_RD_FIFO_IN_USE_0; //SYTH ONLY
|
| 1791 |
|
|
defparam hmc_inst.rd_fifo_in_use_1 = ENUM_RD_FIFO_IN_USE_1; //SYTH ONLY
|
| 1792 |
|
|
defparam hmc_inst.rd_fifo_in_use_2 = ENUM_RD_FIFO_IN_USE_2; //SYTH ONLY
|
| 1793 |
|
|
defparam hmc_inst.rd_fifo_in_use_3 = ENUM_RD_FIFO_IN_USE_3; //SYTH ONLY
|
| 1794 |
|
|
defparam hmc_inst.rd_port_info_0 = ENUM_RD_PORT_INFO_0; //SYTH ONLY
|
| 1795 |
|
|
defparam hmc_inst.rd_port_info_1 = ENUM_RD_PORT_INFO_1; //SYTH ONLY
|
| 1796 |
|
|
defparam hmc_inst.rd_port_info_2 = ENUM_RD_PORT_INFO_2; //SYTH ONLY
|
| 1797 |
|
|
defparam hmc_inst.rd_port_info_3 = ENUM_RD_PORT_INFO_3; //SYTH ONLY
|
| 1798 |
|
|
defparam hmc_inst.rd_port_info_4 = ENUM_RD_PORT_INFO_4; //SYTH ONLY
|
| 1799 |
|
|
defparam hmc_inst.rd_port_info_5 = ENUM_RD_PORT_INFO_5; //SYTH ONLY
|
| 1800 |
|
|
defparam hmc_inst.read_odt_chip = ENUM_READ_ODT_CHIP; //SYTH & SIM
|
| 1801 |
|
|
defparam hmc_inst.reorder_data = ENUM_REORDER_DATA; //SYTH & SIM
|
| 1802 |
|
|
defparam hmc_inst.rfifo0_cport_map = ENUM_RFIFO0_CPORT_MAP; //SYTH & SIM
|
| 1803 |
|
|
defparam hmc_inst.rfifo1_cport_map = ENUM_RFIFO1_CPORT_MAP; //SYTH & SIM
|
| 1804 |
|
|
defparam hmc_inst.rfifo2_cport_map = ENUM_RFIFO2_CPORT_MAP; //SYTH & SIM
|
| 1805 |
|
|
defparam hmc_inst.rfifo3_cport_map = ENUM_RFIFO3_CPORT_MAP; //SYTH & SIM
|
| 1806 |
|
|
defparam hmc_inst.single_ready_0 = ENUM_SINGLE_READY_0; //SYTH & SIM
|
| 1807 |
|
|
defparam hmc_inst.single_ready_1 = ENUM_SINGLE_READY_1; //SYTH & SIM
|
| 1808 |
|
|
defparam hmc_inst.single_ready_2 = ENUM_SINGLE_READY_2; //SYTH & SIM
|
| 1809 |
|
|
defparam hmc_inst.single_ready_3 = ENUM_SINGLE_READY_3; //SYTH & SIM
|
| 1810 |
|
|
defparam hmc_inst.static_weight_0 = ENUM_STATIC_WEIGHT_0; //SYTH ONLY
|
| 1811 |
|
|
defparam hmc_inst.static_weight_1 = ENUM_STATIC_WEIGHT_1; //SYTH ONLY
|
| 1812 |
|
|
defparam hmc_inst.static_weight_2 = ENUM_STATIC_WEIGHT_2; //SYTH ONLY
|
| 1813 |
|
|
defparam hmc_inst.static_weight_3 = ENUM_STATIC_WEIGHT_3; //SYTH ONLY
|
| 1814 |
|
|
defparam hmc_inst.static_weight_4 = ENUM_STATIC_WEIGHT_4; //SYTH ONLY
|
| 1815 |
|
|
defparam hmc_inst.static_weight_5 = ENUM_STATIC_WEIGHT_5; //SYTH ONLY
|
| 1816 |
|
|
defparam hmc_inst.sum_wt_priority_0 = INTG_SUM_WT_PRIORITY_0; //SYTH ONLY
|
| 1817 |
|
|
defparam hmc_inst.sum_wt_priority_1 = INTG_SUM_WT_PRIORITY_1; //SYTH ONLY
|
| 1818 |
|
|
defparam hmc_inst.sum_wt_priority_2 = INTG_SUM_WT_PRIORITY_2; //SYTH ONLY
|
| 1819 |
|
|
defparam hmc_inst.sum_wt_priority_3 = INTG_SUM_WT_PRIORITY_3; //SYTH ONLY
|
| 1820 |
|
|
defparam hmc_inst.sum_wt_priority_4 = INTG_SUM_WT_PRIORITY_4; //SYTH ONLY
|
| 1821 |
|
|
defparam hmc_inst.sum_wt_priority_5 = INTG_SUM_WT_PRIORITY_5; //SYTH ONLY
|
| 1822 |
|
|
defparam hmc_inst.sum_wt_priority_6 = INTG_SUM_WT_PRIORITY_6; //SYTH ONLY
|
| 1823 |
|
|
defparam hmc_inst.sum_wt_priority_7 = INTG_SUM_WT_PRIORITY_7; //SYTH ONLY
|
| 1824 |
|
|
defparam hmc_inst.sync_mode_0 = ENUM_SYNC_MODE_0; //SYTH & SIM
|
| 1825 |
|
|
defparam hmc_inst.sync_mode_1 = ENUM_SYNC_MODE_1; //SYTH & SIM
|
| 1826 |
|
|
defparam hmc_inst.sync_mode_2 = ENUM_SYNC_MODE_2; //SYTH & SIM
|
| 1827 |
|
|
defparam hmc_inst.sync_mode_3 = ENUM_SYNC_MODE_3; //SYTH & SIM
|
| 1828 |
|
|
defparam hmc_inst.sync_mode_4 = ENUM_SYNC_MODE_4; //SYTH & SIM
|
| 1829 |
|
|
defparam hmc_inst.sync_mode_5 = ENUM_SYNC_MODE_5; //SYTH & SIM
|
| 1830 |
|
|
defparam hmc_inst.test_mode = ENUM_TEST_MODE; //SYTH & SIM
|
| 1831 |
|
|
defparam hmc_inst.thld_jar1_0 = ENUM_THLD_JAR1_0; //SYTH & SIM
|
| 1832 |
|
|
defparam hmc_inst.thld_jar1_1 = ENUM_THLD_JAR1_1; //SYTH & SIM
|
| 1833 |
|
|
defparam hmc_inst.thld_jar1_2 = ENUM_THLD_JAR1_2; //SYTH & SIM
|
| 1834 |
|
|
defparam hmc_inst.thld_jar1_3 = ENUM_THLD_JAR1_3; //SYTH & SIM
|
| 1835 |
|
|
defparam hmc_inst.thld_jar1_4 = ENUM_THLD_JAR1_4; //SYTH & SIM
|
| 1836 |
|
|
defparam hmc_inst.thld_jar1_5 = ENUM_THLD_JAR1_5; //SYTH & SIM
|
| 1837 |
|
|
defparam hmc_inst.thld_jar2_0 = ENUM_THLD_JAR2_0; //SYTH & SIM
|
| 1838 |
|
|
defparam hmc_inst.thld_jar2_1 = ENUM_THLD_JAR2_1; //SYTH & SIM
|
| 1839 |
|
|
defparam hmc_inst.thld_jar2_2 = ENUM_THLD_JAR2_2; //SYTH & SIM
|
| 1840 |
|
|
defparam hmc_inst.thld_jar2_3 = ENUM_THLD_JAR2_3; //SYTH & SIM
|
| 1841 |
|
|
defparam hmc_inst.thld_jar2_4 = ENUM_THLD_JAR2_4; //SYTH & SIM
|
| 1842 |
|
|
defparam hmc_inst.thld_jar2_5 = ENUM_THLD_JAR2_5; //SYTH & SIM
|
| 1843 |
|
|
defparam hmc_inst.use_almost_empty_0 = ENUM_USE_ALMOST_EMPTY_0; //SYTH & SIM
|
| 1844 |
|
|
defparam hmc_inst.use_almost_empty_1 = ENUM_USE_ALMOST_EMPTY_1; //SYTH & SIM
|
| 1845 |
|
|
defparam hmc_inst.use_almost_empty_2 = ENUM_USE_ALMOST_EMPTY_2; //SYTH & SIM
|
| 1846 |
|
|
defparam hmc_inst.use_almost_empty_3 = ENUM_USE_ALMOST_EMPTY_3; //SYTH & SIM
|
| 1847 |
|
|
defparam hmc_inst.user_ecc_en = ENUM_USER_ECC_EN; //SYTH & SIM
|
| 1848 |
|
|
defparam hmc_inst.user_priority_0 = ENUM_USER_PRIORITY_0; //SYTH ONLY
|
| 1849 |
|
|
defparam hmc_inst.user_priority_1 = ENUM_USER_PRIORITY_1; //SYTH ONLY
|
| 1850 |
|
|
defparam hmc_inst.user_priority_2 = ENUM_USER_PRIORITY_2; //SYTH ONLY
|
| 1851 |
|
|
defparam hmc_inst.user_priority_3 = ENUM_USER_PRIORITY_3; //SYTH ONLY
|
| 1852 |
|
|
defparam hmc_inst.user_priority_4 = ENUM_USER_PRIORITY_4; //SYTH ONLY
|
| 1853 |
|
|
defparam hmc_inst.user_priority_5 = ENUM_USER_PRIORITY_5; //SYTH ONLY
|
| 1854 |
|
|
defparam hmc_inst.wfifo0_cport_map = ENUM_WFIFO0_CPORT_MAP; //SYTH & SIM
|
| 1855 |
|
|
defparam hmc_inst.wfifo0_rdy_almost_full = ENUM_WFIFO0_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1856 |
|
|
defparam hmc_inst.wfifo1_cport_map = ENUM_WFIFO1_CPORT_MAP; //SYTH & SIM
|
| 1857 |
|
|
defparam hmc_inst.wfifo1_rdy_almost_full = ENUM_WFIFO1_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1858 |
|
|
defparam hmc_inst.wfifo2_cport_map = ENUM_WFIFO2_CPORT_MAP; //SYTH & SIM
|
| 1859 |
|
|
defparam hmc_inst.wfifo2_rdy_almost_full = ENUM_WFIFO2_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1860 |
|
|
defparam hmc_inst.wfifo3_cport_map = ENUM_WFIFO3_CPORT_MAP; //SYTH & SIM
|
| 1861 |
|
|
defparam hmc_inst.wfifo3_rdy_almost_full = ENUM_WFIFO3_RDY_ALMOST_FULL; //SYTH & SIM
|
| 1862 |
|
|
defparam hmc_inst.wr_dwidth_0 = ENUM_WR_DWIDTH_0; //SYTH ONLY
|
| 1863 |
|
|
defparam hmc_inst.wr_dwidth_1 = ENUM_WR_DWIDTH_1; //SYTH ONLY
|
| 1864 |
|
|
defparam hmc_inst.wr_dwidth_2 = ENUM_WR_DWIDTH_2; //SYTH ONLY
|
| 1865 |
|
|
defparam hmc_inst.wr_dwidth_3 = ENUM_WR_DWIDTH_3; //SYTH ONLY
|
| 1866 |
|
|
defparam hmc_inst.wr_dwidth_4 = ENUM_WR_DWIDTH_4; //SYTH ONLY
|
| 1867 |
|
|
defparam hmc_inst.wr_dwidth_5 = ENUM_WR_DWIDTH_5; //SYTH ONLY
|
| 1868 |
|
|
defparam hmc_inst.wr_fifo_in_use_0 = ENUM_WR_FIFO_IN_USE_0; //SYTH ONLY
|
| 1869 |
|
|
defparam hmc_inst.wr_fifo_in_use_1 = ENUM_WR_FIFO_IN_USE_1; //SYTH ONLY
|
| 1870 |
|
|
defparam hmc_inst.wr_fifo_in_use_2 = ENUM_WR_FIFO_IN_USE_2; //SYTH ONLY
|
| 1871 |
|
|
defparam hmc_inst.wr_fifo_in_use_3 = ENUM_WR_FIFO_IN_USE_3; //SYTH ONLY
|
| 1872 |
|
|
defparam hmc_inst.wr_port_info_0 = ENUM_WR_PORT_INFO_0; //SYTH ONLY
|
| 1873 |
|
|
defparam hmc_inst.wr_port_info_1 = ENUM_WR_PORT_INFO_1; //SYTH ONLY
|
| 1874 |
|
|
defparam hmc_inst.wr_port_info_2 = ENUM_WR_PORT_INFO_2; //SYTH ONLY
|
| 1875 |
|
|
defparam hmc_inst.wr_port_info_3 = ENUM_WR_PORT_INFO_3; //SYTH ONLY
|
| 1876 |
|
|
defparam hmc_inst.wr_port_info_4 = ENUM_WR_PORT_INFO_4; //SYTH ONLY
|
| 1877 |
|
|
defparam hmc_inst.wr_port_info_5 = ENUM_WR_PORT_INFO_5; //SYTH ONLY
|
| 1878 |
|
|
defparam hmc_inst.write_odt_chip = ENUM_WRITE_ODT_CHIP; //SYTH & SIM
|
| 1879 |
|
|
|
| 1880 |
|
|
// END ATOM INSTANTIATION
|
| 1881 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1882 |
|
|
|
| 1883 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1884 |
|
|
// START LOCAL FUNCTIONS
|
| 1885 |
|
|
|
| 1886 |
|
|
// END LOCAL FUNCTIONS
|
| 1887 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 1888 |
|
|
|
| 1889 |
|
|
endmodule
|
