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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_mem_if_oct_cyclonev.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
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// ********************************************************************************************************************************
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// This file instantiates the OCT block.
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// ********************************************************************************************************************************
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_oct; -name IP_TOOL_VERSION 17.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
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module altera_mem_if_oct_cyclonev (
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        oct_rzqin,
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        parallelterminationcontrol,
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        seriesterminationcontrol
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);
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parameter OCT_TERM_CONTROL_WIDTH = 0;
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// These should be connected to reference resistance pins on the board, via OCT control block if instantiated by user
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input oct_rzqin;
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// for OCT master, termination control signals will be available to top level
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output [OCT_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol;
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output [OCT_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol;
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        `ifndef ALTERA_RESERVED_QIS
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        // synopsys translate_off
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        `endif
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        tri0  oct_rzqin;
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        `ifndef ALTERA_RESERVED_QIS
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        // synopsys translate_on
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        `endif
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        wire  [0:0]   wire_sd1a_serdataout;
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        cyclonev_termination   sd1a_0
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        (
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        .clkusrdftout(),
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        .compoutrdn(),
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        .compoutrup(),
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        .enserout(),
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        .rzqin(oct_rzqin),
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        .scanout(),
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        .serdataout(wire_sd1a_serdataout[0:0]),
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        .serdatatocore()
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .clkenusr(1'b0),
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        .clkusr(1'b0),
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        .enserusr(1'b0),
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        .nclrusr(1'b0),
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        .otherenser({10{1'b0}}),
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        .scanclk(1'b0),
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        .scanen(1'b0),
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        .scanin(1'b0),
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        .serdatafromcore(1'b0),
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        .serdatain(1'b0)
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        );
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        cyclonev_termination_logic   sd2a_0
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        (
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        .parallelterminationcontrol(parallelterminationcontrol),
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        .serdata(wire_sd1a_serdataout),
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        .seriesterminationcontrol(seriesterminationcontrol)
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .enser(1'b0),
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        .s2pload(1'b0),
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        .scanclk(1'b0),
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        .scanenable(1'b0)
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        // synopsys translate_off
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        // synopsys translate_on
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        );
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endmodule
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