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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_merlin_burst_adapter_new.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4 40 redbear
// files from any of the foregoing (including device programming or simulation
5 32 redbear
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable
8 32 redbear
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14 40 redbear
// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_merlin_burst_adapter_new.sv#1 $
15 32 redbear
// $Revision: #1 $
16 40 redbear
// $Date: 2017/07/30 $
17 32 redbear
// $Author: swbranch $
18
 
19
`timescale 1 ns / 1 ns
20
 
21
// -------------------------------------------------------------------
22
// Merlin Burst Adapter: converts incoming burst packets to fit slave burst
23
// capabilities.
24
// -------------------------------------------------------------------
25
module altera_merlin_burst_adapter_new
26
#(
27
    parameter
28
    // Standard merlin packet parameters that indicate
29
    // field position within the packet
30
    PKT_BEGIN_BURST             = 81,
31
    PKT_ADDR_H                  = 79,
32
    PKT_ADDR_L                  = 48,
33
    PKT_BYTE_CNT_H              = 5,
34
    PKT_BYTE_CNT_L              = 0,
35
    PKT_BURSTWRAP_H             = 11,
36
    PKT_BURSTWRAP_L             = 6,
37
    PKT_TRANS_COMPRESSED_READ   = 14,
38
    PKT_TRANS_WRITE             = 13,
39
    PKT_TRANS_READ              = 12,
40
    PKT_BYTEEN_H                = 83,
41
    PKT_BYTEEN_L                = 80,
42
    PKT_BURST_TYPE_H            = 88,
43
    PKT_BURST_TYPE_L            = 87,
44
    PKT_BURST_SIZE_H            = 86,
45
    PKT_BURST_SIZE_L            = 84,
46
    ST_DATA_W                   = 89,
47
    ST_CHANNEL_W                = 8,
48
 
49
    // The values here are used to infer the slave's maximum
50
    // burst count and constant wrapping boundary (if it exists)
51
    OUT_BYTE_CNT_H              = 5,
52
    OUT_BURSTWRAP_H             = 11,
53
 
54
    // Indicates if incoming packets can have sizes less
55
    // than the data width
56
    IN_NARROW_SIZE              = 0,
57
 
58
    // Indicates if the endpoint slave can accept packets
59
    // with sizes less than the data width
60
    OUT_NARROW_SIZE             = 0,
61
 
62
    // Indicates if the endpoint slave can accept fixed bursts
63
    OUT_FIXED                   = 0,
64
 
65
    // Indicates if the endpoint slave can accept wrap bursts
66
    OUT_COMPLETE_WRAP           = 0,
67
 
68
    // Enables byteenable synthesis, used to convert size to
69
    // byteenables
70
    BYTEENABLE_SYNTHESIS        = 0,
71
 
72
    // A mask that indicates which bits of the burstwrap field are
73
    // constant. Used for optimization purposes.
74
    BURSTWRAP_CONST_MASK        = 0,
75
 
76
    // Indicates the value of burstwrap bits that are constant when
77
    // used with BURSTWRAP_CONST_MASK
78
    BURSTWRAP_CONST_VALUE       = -1,
79
 
80
    // Controls wrapping support. For optimization purposes.
81
    NO_WRAP_SUPPORT             = 0,
82
    INCOMPLETE_WRAP_SUPPORT     = 1,
83
 
84
    // Pipelining options
85
    PIPE_INPUTS                 = 0,
86
    PIPE_INTERNAL               = 0
87
)
88
(
89
    input                           clk,
90
    input                           reset,
91
 
92
    // -------------------
93
    // Command Sink (Input)
94
    // -------------------
95
    input                           sink0_valid,
96
    input [ST_DATA_W    - 1 : 0]    sink0_data,
97
    input [ST_CHANNEL_W - 1 : 0]    sink0_channel,
98
    input                           sink0_startofpacket,
99
    input                           sink0_endofpacket,
100
    output reg                      sink0_ready,
101
 
102
    // -------------------
103
    // Command Source (Output)
104
    // -------------------
105
    output reg                        source0_valid,
106
    output reg [ST_DATA_W    - 1 : 0] source0_data,
107
    output reg [ST_CHANNEL_W - 1 : 0] source0_channel,
108
    output reg                        source0_startofpacket,
109
    output reg                        source0_endofpacket,
110
    input                             source0_ready
111
);
112
 
113
    // Widths of various fields in the packet
114
    localparam
115
    PKT_BYTE_CNT_W        = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
116
    PKT_ADDR_W            = PKT_ADDR_H - PKT_ADDR_L + 1,
117
    PKT_BYTEEN_W          = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
118
    OUT_BYTE_CNT_W        = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
119
    OUT_BURSTWRAP_W       = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
120
    PKT_BURSTWRAP_W       = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
121
    PKT_BURST_SIZE_W      = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1,
122
    PKT_BURST_TYPE_W      = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1;
123
 
124
    localparam
125
    NUM_SYMBOLS           = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
126
    LOG2_NUM_SYMBOLS      = log2ceil(NUM_SYMBOLS),
127
    ADDR_MASK_SEL         = (NUM_SYMBOLS == 1) ? 1 : log2ceil(NUM_SYMBOLS);
128
 
129
    // We try to keep everything in terms of words (transfers) instead of
130
    // bytes in this implementation. Cognitive ease!
131
    localparam
132
    IN_LEN_W              = PKT_BYTE_CNT_W - LOG2_NUM_SYMBOLS,
133
    MAX_IN_LEN            = 1 << (IN_LEN_W - 1),
134
    OUT_LEN_W             = OUT_BYTE_CNT_W - LOG2_NUM_SYMBOLS,
135
    MAX_OUT_LEN           = 1 << (OUT_LEN_W - 1),
136
 
137
    BNDRY_WIDTH           = PKT_BURSTWRAP_W,
138
    OUT_BOUNDARY          = MAX_OUT_LEN * NUM_SYMBOLS,
139
    BYTE_TO_WORD_SHIFT    = log2ceil(NUM_SYMBOLS),
140
    BYTE_TO_WORD_SHIFT_W  = log2ceil(BYTE_TO_WORD_SHIFT) + 1;
141
 
142
    // Determines the protocol from the features that are enabled or disabled.
143
    // Should be moved to the code that parameterizes this adapter.
144
    localparam
145
    AXI_SLAVE             = OUT_FIXED & OUT_NARROW_SIZE & OUT_COMPLETE_WRAP,
146
    IS_WRAP_AVALON_SLAVE  = !AXI_SLAVE & (PKT_BURSTWRAP_H != OUT_BURSTWRAP_H),
147
    IS_INCR_SLAVE         = !AXI_SLAVE & !IS_WRAP_AVALON_SLAVE,
148
    NON_BURSTING_SLAVE    = (MAX_OUT_LEN == 1),
149
    // This parameter indicates that the system is purely INCR avalon master/slave
150
    INCR_AVALON_SYS       = IS_INCR_SLAVE && (PKT_BURSTWRAP_W == 1) && (OUT_BURSTWRAP_W == 1) && (IN_NARROW_SIZE == 0);
151
 
152
    // ---------------------------------------------------
153
    // State definitions
154
    // ---------------------------------------------------
155
    typedef enum bit [1:0] {
156
 
157
        // The idle state.
158
        ST_IDLE         = 2'b00,
159
 
160
        // Adapter enters this state when the converters accept a compressed
161
        // transaction (read). Address and burst length is calculated
162
        // for every output transfer.
163
        ST_COMP_TRANS   = 2'b01,
164
 
165
        // Adapter enters this state when the converters accept uncompressed
166
        // transactions (writes, generally). Address is passed through and
167
        // burst length is decremented according to the conventions of the
168
        // packet format.
169
        ST_UNCOMP_TRANS = 2'b10
170
    } t_state;
171
 
172
    t_state state, next_state;
173
 
174
    // ---------------------------------------------------
175
    // Merlin packet burst type encoding
176
    // ---------------------------------------------------
177
    typedef enum bit[1:0]
178
    {
179
        FIXED       = 2'b00,
180
        INCR        = 2'b01,
181
        WRAP        = 2'b10,
182
        REP_WRAP    = 2'b11
183
    } BurstType;
184
 
185
    // ---------------------------------------------------
186
    // Here we go!
187
    //
188
    // An optional input pipeline stage. We typically do not use this
189
    // because the interconnect allows users to add pipelines just
190
    // before the burst adapter inputs.
191
    //
192
    // Signal prefix entering this stage: sink0_*
193
    // Signal prefix exiting this stage: sink0_pipe_*
194
    // ---------------------------------------------------
195
    wire                         sink0_pipe_valid;
196
    wire [ST_DATA_W    - 1 : 0]  sink0_pipe_data;
197
    wire [ST_CHANNEL_W - 1 : 0]  sink0_pipe_channel;
198
    wire                         sink0_pipe_sop;
199
    wire                         sink0_pipe_eop;
200
    wire                         sink0_pipe_ready;
201
 
202
    generate
203
    if (PIPE_INPUTS == 1) begin : input_pipeline
204
        altera_avalon_st_pipeline_stage #(
205
            .SYMBOLS_PER_BEAT (1),
206
            .BITS_PER_SYMBOL  (ST_DATA_W),
207
            .USE_PACKETS      (1),
208
            .USE_EMPTY        (0),
209
            .EMPTY_WIDTH      (0),
210
            .CHANNEL_WIDTH    (ST_CHANNEL_W),
211
            .PACKET_WIDTH     (2),
212
            .ERROR_WIDTH      (0),
213
            .PIPELINE_READY   (1)
214
        ) input_pipe (
215
            .clk               (clk),
216
            .reset             (reset),
217
 
218
            .in_ready          (sink0_ready),
219
            .in_valid          (sink0_valid),
220
            .in_startofpacket  (sink0_startofpacket),
221
            .in_endofpacket    (sink0_endofpacket),
222
            .in_data           (sink0_data),
223
            .in_channel        (sink0_channel),
224
 
225
            .out_ready         (sink0_pipe_ready),
226
            .out_valid         (sink0_pipe_valid),
227
            .out_startofpacket (sink0_pipe_sop),
228
            .out_endofpacket   (sink0_pipe_eop),
229
            .out_data          (sink0_pipe_data),
230
            .out_channel       (sink0_pipe_channel),
231
 
232
            .in_empty          (1'b0),
233
            .in_error          (1'b0),
234
            .out_empty         (),
235
            .out_error         ()
236
        );
237
    end
238
    else begin : no_input_pipeline
239
 
240
        assign sink0_pipe_valid   = sink0_valid;
241
        assign sink0_pipe_data    = sink0_data;
242
        assign sink0_pipe_channel = sink0_channel;
243
        assign sink0_pipe_sop     = sink0_startofpacket;
244
        assign sink0_pipe_eop     = sink0_endofpacket;
245
        assign sink0_ready        = sink0_pipe_ready;
246
 
247
    end
248
    endgenerate
249
 
250
    // --------------------------------------------------
251
    // Signal extraction stage. We extract signals from
252
    // the packet payload and compute some values.
253
    //
254
    // Signal prefix entering this stage: sink0_pipe_*
255
    // Signal prefix exiting this stage: in_*
256
    // --------------------------------------------------
257
    wire [PKT_BURST_TYPE_W - 1 : 0]  in_bursttype         = sink0_pipe_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L];
258
    wire [PKT_BYTE_CNT_W   - 1 : 0]  in_bytecount         = sink0_pipe_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L];
259
    wire [PKT_ADDR_W       - 1 : 0]  in_addr              = sink0_pipe_data[PKT_ADDR_H : PKT_ADDR_L];
260
    wire [63 : 0]                    log2_numsymbols      = log2ceil(NUM_SYMBOLS);
261
    wire [PKT_BYTE_CNT_W   - 1 : 0]  in_burstcount        = in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0];
262
    wire [IN_LEN_W         - 1 : 0]  in_len               = in_burstcount[IN_LEN_W - 1 : 0];
263
    wire [PKT_BURST_SIZE_W - 1 : 0]  in_size              = sink0_pipe_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L];
264
    wire                             in_write             = sink0_pipe_data[PKT_TRANS_WRITE];
265
    wire                             in_compressed_read   = sink0_pipe_data[PKT_TRANS_COMPRESSED_READ];
266
    wire                             in_read              = sink0_pipe_data[PKT_TRANS_READ];
267
    wire                             in_uncompressed_read = in_read & ~sink0_pipe_data[PKT_TRANS_COMPRESSED_READ];
268
    wire                             in_sop               = sink0_pipe_sop;
269
    wire                             in_eop               = sink0_pipe_eop;
270
    wire [PKT_BYTEEN_W     - 1 : 0]  in_byteen            = sink0_pipe_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
271
    wire                             in_passthru          = in_burstcount <= 16;
272
 
273
    wire                             in_valid;
274
    reg                              in_ready_hold;
275
    wire                             in_narrow;
276
    wire [PKT_BURSTWRAP_W  - 1 : 0]  in_burstwrap;
277
    wire [PKT_ADDR_W       - 1 : 0]  in_aligned_addr;
278
    wire [PKT_BURSTWRAP_W  - 1 : 0]  in_boundary;
279
 
280
    // Used to keep ready low during reset
281
    always_ff @(posedge clk or posedge reset) begin
282
        if (reset) begin
283
            in_ready_hold <= '0;
284
        end else begin
285
            in_ready_hold <= '1;
286
        end
287
    end
288
 
289
    assign in_valid = sink0_pipe_valid & in_ready_hold;
290
    assign in_narrow = in_size < log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0];
291
 
292
    // Optimization: extract burstwrap, and drive the constant bits to
293
    // their constant values to help the synthesis tool.
294
    genvar i;
295
    generate
296
        for (i = 0; i < PKT_BURSTWRAP_W; i = i+1) begin: assign_burstwrap_bit
297
            if (BURSTWRAP_CONST_MASK[i]) begin
298
                assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i];
299
            end
300
            else begin
301
                assign in_burstwrap[i] = sink0_pipe_data[PKT_BURSTWRAP_L + i];
302
            end
303
        end
304
    endgenerate
305
 
306
    // Addresses in the packet can be unaligned. Here we align the address
307
    // for ease of internal calculations. The initial output address may
308
    // still be unaligned to preserve the original transaction intention.
309
 
310
    wire [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0] out_mask_and_aligned_addr;
311
    altera_merlin_address_alignment
312
    #(
313
        .ADDR_W             (PKT_ADDR_W),
314
        .BURSTWRAP_W        (1), // unused because we just want to align address
315
        .TYPE_W             (0), // unused because we just want to align address
316
        .SIZE_W             (PKT_BURST_SIZE_W),
317
        .INCREMENT_ADDRESS  (0),
318
        .NUMSYMBOLS         (NUM_SYMBOLS)
319
    ) align_address_to_size
320
    (
321
        // Not used when INCREMENT_ADDRESS = 0
322
        .clk       (1'b0),
323
        .reset     (1'b0),
324
        .in_valid  (1'b0),
325
        .in_sop    (1'b0),
326
        .in_eop    (1'b0),
327
        .out_ready (),
328
 
329
        .in_data   ({ in_addr, in_size }),
330
        .out_data  (out_mask_and_aligned_addr)
331
    );
332
 
333
    assign in_aligned_addr = out_mask_and_aligned_addr[PKT_ADDR_W - 1 : 0];
334
 
335
    // Incrementing the burstwrap provides the wrapping boundary for
336
    // wrapping transactions.
337
    altera_merlin_burst_adapter_burstwrap_increment
338
    #(
339
        .WIDTH (PKT_BURSTWRAP_W)
340
    ) the_burstwrap_increment
341
    (
342
        .mask (in_burstwrap),
343
        .inc  (in_boundary)
344
    );
345
 
346
    localparam OUT_BNDRY_ADDR_SEL_W = log2ceil(OUT_BOUNDARY);
347
    localparam OUT_BOUNDARY_WIDTH   = OUT_BNDRY_ADDR_SEL_W + 1;
348
 
349
    // address to use for distance calculations when the transaction
350
    // boundary is less than the slave's wrapping boundary.
351
    wire [PKT_ADDR_W           - 1 : 0]     in_bndry_addr_sel;
352
 
353
    // the length (in words) to the transaction boundary (if it exists)
354
    wire [IN_LEN_W             - 1 : 0]     len_to_in_bndry;
355
 
356
    // the length (in words) to the slave's boundary (if it exists)
357
    wire [OUT_BOUNDARY_WIDTH   - 1 : 0]     len_to_out_bndry;
358
 
359
    reg  [IN_LEN_W             - 1 : 0]     first_len;
360
    wire [BYTE_TO_WORD_SHIFT_W - 1 : 0]     byte_to_word_shift;
361
    assign byte_to_word_shift = BYTE_TO_WORD_SHIFT[BYTE_TO_WORD_SHIFT_W - 1 : 0];
362
 
363
    // This part calculates the length that is required to align the burst to
364
    // the transaction's wrapping boundary (if it exists), or to the slave's
365
    // wrapping boundary (if it exists). We pre-compute this ahead of the
366
    // converters to minimize the logic loops in determining the output
367
    // burst lengths. Note that incoming addresses for wrapping transactions
368
    // are always aligned to size by definition.
369
 
370
    assign in_bndry_addr_sel = in_addr & in_burstwrap;
371
    assign len_to_in_bndry = (in_boundary - in_bndry_addr_sel) >> byte_to_word_shift;
372
 
373
    generate
374
 
375
        if (OUT_BNDRY_ADDR_SEL_W > 0) begin : len_to_out_bndry_calc
376
            wire [OUT_BNDRY_ADDR_SEL_W - 1 : 0] out_bndry_addr_sel;
377
 
378
            // We have to use the aligned address, because this part may
379
            // handle incoming incrementing bursts which can be unaligned.
380
            assign out_bndry_addr_sel = in_aligned_addr[OUT_BNDRY_ADDR_SEL_W - 1 : 0];
381
            assign len_to_out_bndry   = (OUT_BOUNDARY - out_bndry_addr_sel) >> byte_to_word_shift;
382
        end
383
 
384
        // A nonsensical corner-case of a wrapping slave with
385
        // MAX_OUT_LEN = 1, NUM_SYMBOLS = 1
386
        else begin : len_to_out_bndry_calc_corner
387
            assign len_to_out_bndry = OUT_BOUNDARY >> byte_to_word_shift;
388
        end
389
 
390
    endgenerate
391
 
392
    // --------------------------------------------------
393
    // Optional internal pipeline stage.
394
    //
395
    // Note that we still buffer the transfer if the pipeline stage is
396
    // unused, because the adapter must accept read transactions before
397
    // converting them. Failure to do this will lead to masters receiving
398
    // responses before their commands have been accepted in unpipelined
399
    // systems. The buffering registers are named in_*_reg.
400
    //
401
    // Notes on signal naming convention used:
402
    //
403
    // in_*       --> These signals are coming directly from the previous stage.
404
    //            --> Timing - zero cycle delta
405
    // d0_in_*    --> Signals that are outputs of this stage.
406
    //            --> Timing - zero cycle delta (IF PIPE_INTERNAL == 0) else 1 clock
407
    // d1_in_*    --> Signals that are outputs of this stage.
408
    //            --> Timing - always delayed by 1 clock. (vs the input)
409
    // --------------------------------------------------
410
    reg                             in_sop_reg;
411
    reg                             in_eop_reg;
412
    reg                             in_valid_reg;
413
    reg                             in_compressed_read_reg;
414
    reg                             in_uncompressed_read_reg;
415
    reg                             in_write_reg;
416
    reg                             in_passthru_reg;
417
    reg [PKT_BURST_SIZE_W - 1 : 0]  in_size_reg;
418
    reg [ST_DATA_W        - 1 : 0]  in_data_reg;
419
    reg [ST_CHANNEL_W     - 1 : 0]  in_channel_reg;
420
    reg [PKT_BURST_TYPE_W - 1 : 0]  in_bursttype_reg;
421
    reg [PKT_BURSTWRAP_W  - 1 : 0]  in_burstwrap_reg;
422
    reg [PKT_BYTEEN_W     - 1 : 0]  in_byteen_reg;
423
    reg [PKT_ADDR_W       - 1 : 0]  in_addr_reg;
424
    reg [PKT_ADDR_W       - 1 : 0]  in_aligned_addr_reg;
425
    reg [IN_LEN_W         - 1 : 0]  in_len_reg;
426
    reg                             in_narrow_reg;
427
 
428
    reg [PKT_ADDR_W       - 1 : 0]  d0_in_addr;
429
    reg [PKT_ADDR_W       - 1 : 0]  d0_in_aligned_addr;
430
    reg                             d0_in_sop;
431
    reg                             d0_in_compressed_read;
432
    reg                             d0_in_uncompressed_read;
433
    reg                             d0_in_write;
434
    reg [PKT_BURST_TYPE_W - 1 : 0]  d0_in_bursttype;
435
    reg [PKT_BURSTWRAP_W  - 1 : 0]  d0_in_burstwrap;
436
    reg [PKT_BURSTWRAP_W  - 1 : 0]  d0_in_burstwrap_value;
437
    reg [PKT_BURST_SIZE_W - 1 : 0]  d0_in_size;
438
    reg [PKT_BURST_SIZE_W - 1 : 0]  d0_in_size_value;
439
    reg [IN_LEN_W         - 1 : 0]  d0_in_len;
440
    reg                             d0_in_valid;
441
 
442
    reg                             d1_in_narrow;
443
    reg [PKT_ADDR_W       - 1 : 0]  d1_in_aligned_addr;
444
    reg                             d1_in_eop;
445
    reg                             d1_in_compressed_read;
446
    reg                             d1_in_uncompressed_read;
447
    reg [ST_DATA_W        - 1 : 0]  d1_in_data;
448
    reg [ST_CHANNEL_W     - 1 : 0]  d1_in_channel;
449
    reg                             d1_in_write;
450
    reg [PKT_BURST_TYPE_W - 1 : 0]  d1_in_bursttype;
451
    reg [PKT_BURSTWRAP_W  - 1 : 0]  d1_in_burstwrap;
452
    reg                             d1_in_passthru;
453
    reg [PKT_BURST_SIZE_W - 1 : 0]  d1_in_size;
454
    reg [PKT_BYTEEN_W     - 1 : 0]  d1_in_byteen;
455
 
456
    reg                             nb;
457
 
458
    generate
459
        if (PIPE_INTERNAL == 0) begin : no_internal_pipeline
460
 
461
            always_ff @(posedge clk or posedge reset) begin
462
                if (reset) begin
463
                    in_eop_reg               <= '0;
464
                    in_compressed_read_reg   <= '0;
465
                    in_uncompressed_read_reg <= '0;
466
                    in_data_reg              <= '0;
467
                    in_channel_reg           <= '0;
468
                    in_write_reg             <= '0;
469
                    in_bursttype_reg         <= '0;
470
                    in_burstwrap_reg         <= '0;
471
                    in_passthru_reg          <= '0;
472
                    in_size_reg              <= '0;
473
                    in_byteen_reg            <= '0;
474
                    in_aligned_addr_reg      <= '0;
475
                    in_narrow_reg            <= '0;
476
                end else begin
477
                    if (sink0_pipe_valid & sink0_pipe_ready) begin
478
                        in_eop_reg               <= in_eop;
479
                        in_data_reg              <= sink0_pipe_data;
480
                        in_channel_reg           <= sink0_pipe_channel;
481
                        in_compressed_read_reg   <= in_compressed_read;
482
                        in_uncompressed_read_reg <= in_uncompressed_read;
483
                        in_write_reg             <= in_write;
484
                        in_bursttype_reg         <= in_bursttype;
485
                        in_burstwrap_reg         <= in_burstwrap;
486
                        in_size_reg              <= in_size;
487
                        in_byteen_reg            <= in_byteen;
488
                        in_aligned_addr_reg      <= in_aligned_addr;
489
                        in_narrow_reg            <= in_narrow;
490
                    end
491
                    // length changes during packets, so sample
492
                    // length-dependent signals at the start
493
                    if (sink0_pipe_valid & sink0_pipe_ready & in_sop) begin
494
                        in_passthru_reg <= in_passthru;
495
                    end
496
                end // else: !if(reset)
497
            end // always_ff @
498
 
499
            always_comb begin
500
                d0_in_sop                = in_sop;
501
                d0_in_compressed_read    = in_compressed_read;
502
                d0_in_uncompressed_read  = in_uncompressed_read;
503
                d0_in_write              = in_write;
504
                d0_in_burstwrap          = in_burstwrap;
505
                d0_in_size               = in_size;
506
                d0_in_addr               = in_addr;
507
                d0_in_aligned_addr       = in_aligned_addr;
508
                d0_in_len                = in_len;
509
                d0_in_valid              = in_valid;
510
 
511
                d1_in_eop                = in_eop_reg;
512
                d1_in_compressed_read    = in_compressed_read_reg;
513
                d1_in_uncompressed_read  = in_uncompressed_read_reg;
514
                d1_in_write              = in_write_reg;
515
                d1_in_burstwrap          = in_burstwrap_reg;
516
                d1_in_size               = in_size_reg;
517
                d1_in_aligned_addr       = in_aligned_addr_reg;
518
                d1_in_data               = in_data_reg;
519
                d1_in_channel            = in_channel_reg;
520
                d1_in_bursttype          = in_bursttype_reg;
521
                d1_in_passthru           = in_passthru_reg;
522
                d1_in_byteen             = in_byteen_reg;
523
                d1_in_narrow             = in_narrow_reg;
524
 
525
                // Assign after the related d1_in_* signals have been assigned.
526
                d0_in_size_value         = nb ? d0_in_size : d1_in_size;
527
                d0_in_burstwrap_value    = nb ? d0_in_burstwrap : d1_in_burstwrap;
528
            end
529
 
530
        end // block: no_internal_pipeline
531
        else begin : internal_pipeline
532
 
533
            reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size_dl;
534
            reg [PKT_BURSTWRAP_W - 1 : 0]  d0_in_burstwrap_dl;
535
 
536
            always_ff @(posedge clk or posedge reset) begin
537
                if (reset) begin
538
                    in_eop_reg               <= '0;
539
                    in_sop_reg               <= '0;
540
                    in_compressed_read_reg   <= '0;
541
                    in_uncompressed_read_reg <= '0;
542
                    in_data_reg              <= '0;
543
                    in_channel_reg           <= '0;
544
                    in_write_reg             <= '0;
545
                    in_bursttype_reg         <= '0;
546
                    in_burstwrap_reg         <= '0;
547
                    in_passthru_reg          <= '0;
548
                    in_size_reg              <= '0;
549
                    in_byteen_reg            <= '0;
550
                    in_addr_reg              <= '0;
551
                    in_aligned_addr_reg      <= '0;
552
                    in_len_reg               <= '0;
553
                    in_narrow_reg            <= '0;
554
                    in_valid_reg             <= '0;
555
 
556
                    d1_in_eop                <= '0;
557
                    d1_in_compressed_read    <= '0;
558
                    d1_in_data               <= '0;
559
                    d1_in_channel            <= '0;
560
                    d1_in_write              <= '0;
561
                    d1_in_bursttype          <= '0;
562
                    d1_in_burstwrap          <= '0;
563
                    d1_in_passthru           <= '0;
564
                    d1_in_size               <= '0;
565
                    d0_in_size_dl            <= '0;
566
                    d0_in_burstwrap_dl       <= '0;
567
                    d1_in_byteen             <= '0;
568
                end else begin
569
                    if (sink0_pipe_valid & sink0_pipe_ready) begin
570
                        in_eop_reg               <= in_eop;
571
                        in_sop_reg               <= in_sop;
572
                        in_data_reg              <= sink0_pipe_data;
573
                        in_channel_reg           <= sink0_pipe_channel;
574
                        in_compressed_read_reg   <= in_compressed_read;
575
                        in_uncompressed_read_reg <= in_uncompressed_read;
576
                        in_write_reg             <= in_write;
577
                        in_bursttype_reg         <= in_bursttype;
578
                        in_burstwrap_reg         <= in_burstwrap;
579
                        in_size_reg              <= in_size;
580
                        in_byteen_reg            <= in_byteen;
581
                        in_addr_reg              <= in_addr;
582
                        in_aligned_addr_reg      <= in_aligned_addr;
583
                        in_len_reg               <= in_len;
584
                        in_narrow_reg            <= in_narrow;
585
                    end
586
                    // length changes during packets, so sample
587
                    // length-dependent signals at the start
588
                    if (in_valid & sink0_pipe_ready & in_sop)
589
                        in_passthru_reg <= in_passthru;
590
                    if (sink0_pipe_ready)
591
                        in_valid_reg <= in_valid;
592
                    if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
593
                        ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) )) begin
594
                        d1_in_eop               <= in_eop_reg;
595
                        d1_in_compressed_read   <= in_compressed_read_reg;
596
                        d1_in_data              <= in_data_reg;
597
                        d1_in_channel           <= in_channel_reg;
598
                        d1_in_write             <= in_write_reg;
599
                        d1_in_bursttype         <= in_bursttype_reg;
600
                        d1_in_burstwrap         <= in_burstwrap_reg;
601
                        d0_in_burstwrap_dl      <= in_burstwrap_reg;
602
                        d1_in_passthru          <= in_passthru_reg;
603
                        d1_in_size              <= in_size_reg;
604
                        d0_in_size_dl           <= in_size_reg;
605
                        d1_in_byteen            <= in_byteen_reg;
606
                        d1_in_aligned_addr      <= in_aligned_addr_reg;
607
                        d1_in_narrow            <= in_narrow_reg;
608
                        d1_in_uncompressed_read <= in_uncompressed_read_reg;
609
                    end // if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |...
610
                end // else: !if(reset)
611
            end // always_ff @
612
 
613
            always_comb begin
614
                d0_in_valid             = in_valid_reg;
615
                d0_in_sop               = in_sop_reg;
616
                d0_in_compressed_read   = in_compressed_read_reg;
617
                d0_in_uncompressed_read = in_uncompressed_read_reg;
618
                d0_in_write             = in_write_reg;
619
                d0_in_burstwrap         = in_burstwrap_reg;
620
                d0_in_size              = in_size_reg;
621
                d0_in_size_value        = nb ? in_size_reg : d0_in_size_dl;
622
                d0_in_burstwrap_value   = nb ? in_burstwrap_reg : d0_in_burstwrap_dl;
623
                d0_in_addr              = in_addr_reg;
624
                d0_in_aligned_addr      = in_aligned_addr_reg;
625
                d0_in_len               = in_len_reg;
626
            end // always_comb
627
        end // block: internal_pipeline
628
 
629
    endgenerate
630
 
631
    // --------------------------------------------------
632
    // Control logic stage: state machine
633
    // --------------------------------------------------
634
    always_ff @(posedge clk or posedge reset) begin
635
        if (reset)  begin
636
            state <= ST_IDLE;
637
        end else begin
638
            if (~source0_valid | source0_ready) begin
639
                state <= next_state;
640
            end
641
        end
642
    end
643
 
644
    always_comb begin : state_transition
645
        next_state = ST_IDLE;   // default
646
        case (state)
647
            ST_IDLE : begin
648
                next_state = ST_IDLE;
649
 
650
                if (d0_in_valid) begin
651
                    if (d0_in_write | d0_in_uncompressed_read)  next_state = ST_UNCOMP_TRANS;
652
                    if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
653
                end
654
            end
655
 
656
            ST_UNCOMP_TRANS : begin
657
                next_state = ST_UNCOMP_TRANS;
658
 
659
                if (source0_endofpacket) begin
660
                    if (!d0_in_valid) next_state = ST_IDLE;
661
                    else begin
662
                        if (d0_in_write | d0_in_uncompressed_read)  next_state = ST_UNCOMP_TRANS;
663
                        if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
664
                    end
665
                end
666
            end
667
            ST_COMP_TRANS : begin
668
                next_state = ST_COMP_TRANS;
669
 
670
                if (source0_endofpacket) begin
671
                    if (!d0_in_valid) begin
672
                        next_state = ST_IDLE;
673
                    end
674
                    else begin
675
                        if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS;
676
                        if (d0_in_compressed_read)                 next_state = ST_COMP_TRANS;
677
                    end
678
                end
679
            end
680
        endcase
681
    end
682
 
683
    // --------------------------------------------------
684
    // Control logic stage: signals for the converters. These signals
685
    // enable the correct converter for a burst type, and act as a
686
    // select line when muxing the converter outputs.
687
    //
688
    // Each type of slave receives its own control logic stage, optimized
689
    // for that particular type.
690
    // --------------------------------------------------
691
    wire [PKT_BYTE_CNT_W  - 1 : 0]  out_byte_cnt;
692
    wire [IN_LEN_W        - 1 : 0]  incr_out_len;
693
    wire [IN_LEN_W        - 1 : 0]  wrap_out_len;
694
    wire [IN_LEN_W        - 1 : 0]  incr_uncompr_out_len;
695
    wire [IN_LEN_W        - 1 : 0]  wrap_uncompr_out_len;
696
    wire [PKT_ADDR_W      - 1 : 0]  incr_out_addr;
697
    wire [PKT_ADDR_W      - 1 : 0]  wrap_out_addr;
698
    wire [PKT_ADDR_W      - 1 : 0]  fixed_out_addr;
699
    reg  [PKT_ADDR_W      - 1 : 0]  uncompr_out_addr;
700
    wire [IN_LEN_W        - 1 : 0]  fixed_out_len;
701
    wire [PKT_ADDR_W      - 1 : 0]  out_addr;
702
 
703
    wire                    in_full_size_write_wrap;
704
    wire                    in_full_size_read_wrap;
705
    wire                    in_default_converter;
706
    wire                    in_full_size_incr;
707
    reg                     in_default_converter_reg;
708
    reg                     in_full_size_incr_reg;
709
    reg                     in_full_size_write_wrap_reg;
710
    reg                     in_full_size_read_wrap_reg;
711
 
712
    wire                    new_burst;
713
    wire                    fixed_new_burst;
714
    wire                    wrap_new_burst;
715
    wire                    incr_new_burst;
716
 
717
    wire                    next_out_sop;
718
    wire                    next_out_eop;
719
    wire                    is_passthru;
720
    wire                    enable_incr_converter;
721
    wire                    enable_fixed_converter;
722
    wire                    enable_write_wrap_converter;
723
    wire                    enable_read_wrap_converter;
724
    wire                    enable_incr_write_converter;
725
    wire                    enable_incr_read_converter;
726
    reg [IN_LEN_W - 1 : 0]  d0_first_len;
727
 
728
 
729
    // -----------------------------------------------------------------------
730
    // Enable the converters when:
731
    // - (sink0_pipe_valid  && (source0_ready | ~source0_valid):
732
    //         : when the BA is in idle (!source_valid) and there is a packet coming at input
733
    //           or the outpacket has been accepted and there is a packet coming
734
    // - (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready))
735
    //         : For compressed read, need something consider at end_of_packet, only when seeing
736
    //           end_of_packet then turn off converter.
737
    // Each converter will be turned on with its own enable based on different type of incoming burst
738
    // -----------------------------------------------------------------------
739
    generate
740
        if (NON_BURSTING_SLAVE) begin : non_bursting_converter_control
741
            wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
742
            assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
743
 
744
            if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
745
                always_comb begin
746
                    d0_in_bursttype            = nb ? in_bursttype : in_bursttype_reg;
747
                end
748
            end
749
            else begin : PIPELINE_INPUT
750
                    reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
751
                always_ff @(posedge clk or posedge reset) begin
752
                    if (reset) begin
753
                        d0_in_bursttype_dl         <= '0;
754
                    end else begin
755
                        if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
756
                            ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
757
                            d0_in_bursttype_dl        <= in_bursttype_reg;
758
                        end
759
                    end // else: !if(reset)
760
                end // always_ff @
761
                always_comb begin
762
                    d0_in_bursttype            = nb ? in_bursttype_reg : d0_in_bursttype_dl;
763
                end
764
            end
765
 
766
            //nb: new burst signal
767
            assign nb                        =  fixed_new_burst;
768
 
769
            // -----------------------------------------------------------------------
770
            // I. Conveter enable signals: Turn on/off each conveter accordingly
771
            // -----------------------------------------------------------------------
772
            assign enable_fixed_converter = (d0_in_valid  && (source0_ready | !source0_valid) || (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready)));
773
 
774
            // -----------------------------------------------------------------------
775
            // II. Packet signals
776
            // -----------------------------------------------------------------------
777
            assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(fixed_new_burst)) ? 1'b0 : d0_in_sop;
778
            assign next_out_eop = (state == ST_COMP_TRANS) ?  fixed_new_burst  : d1_in_eop;
779
 
780
            // -----------------------------------------------------------------------
781
            // III. Output select
782
            // -----------------------------------------------------------------------
783
            assign out_byte_cnt  = fixed_out_byte_cnt;
784
            assign out_addr      = fixed_out_addr;
785
        end
786
        else if (INCR_AVALON_SYS) begin : incr_avalon_converter_control
787
            wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
788
            assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
789
 
790
            //nb: new burst signal
791
            assign nb                        =  incr_new_burst;
792
 
793
            // -----------------------------------------------------------------------
794
            // I. Conveter enable signals: Turn on/off each conveter accordingly
795
            // -----------------------------------------------------------------------
796
            assign enable_incr_converter = (d0_in_valid  && (source0_ready | !source0_valid) || (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready)));
797
 
798
            // -----------------------------------------------------------------------
799
            // II. Packet signals
800
            // -----------------------------------------------------------------------
801
            assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(incr_new_burst)) ? 1'b0 : d0_in_sop;
802
            assign next_out_eop = (state == ST_COMP_TRANS) ?  incr_new_burst  : d1_in_eop;
803
 
804
            // -----------------------------------------------------------------------
805
            // III. Output select
806
            // -----------------------------------------------------------------------
807
            assign out_byte_cnt  = incr_out_byte_cnt;
808
            assign out_addr  =  incr_out_addr;
809
        end
810
        else begin : other_converter_control
811
            if (IS_WRAP_AVALON_SLAVE) begin
812
                wire                    in_narrow_or_fixed;
813
                wire                    in_read_but_not_fixed_or_narrow;
814
                wire                    in_write_but_not_fixed_or_narrow;
815
                reg                     in_read_but_not_fixed_or_narrow_reg;
816
                reg                     in_write_but_not_fixed_or_narrow_reg;
817
                reg                     in_narrow_or_fixed_reg;
818
                reg                     d0_in_read_but_not_fixed_or_narrow;
819
                reg                     d0_in_write_but_not_fixed_or_narrow;
820
                reg                     d0_in_default_converter;
821
                reg                     d1_in_narrow_or_fixed;
822
                reg                     d1_in_read_but_not_fixed_or_narrow;
823
                reg                     d1_in_write_but_not_fixed_or_narrow;
824
                reg                     d1_in_default_converter;
825
                reg [IN_LEN_W - 1 : 0]  first_len_reg;
826
 
827
                wire [PKT_BYTE_CNT_W - 1 : 0]  fixed_out_byte_cnt;
828
                wire [PKT_BYTE_CNT_W - 1 : 0]  incr_out_byte_cnt;
829
                wire                    in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
830
 
831
                // nb: new burst
832
                assign nb                               = (d1_in_narrow_or_fixed ? fixed_new_burst : new_burst);
833
                assign in_read_but_not_fixed_or_narrow  = in_compressed_read & !in_narrow_or_fixed;
834
                assign in_write_but_not_fixed_or_narrow = in_write & !in_narrow_or_fixed;
835
                assign in_narrow_or_fixed               = in_narrow || in_fixed;
836
                assign in_default_converter             = in_fixed || in_narrow || in_uncompressed_read;
837
                assign incr_out_byte_cnt                = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
838
                assign fixed_out_byte_cnt               = fixed_out_len << log2_numsymbols;
839
 
840
                //----------------------------------------------------------------
841
                // I. Pipeline input stage
842
                //----------------------------------------------------------------
843
                if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
844
                    always_ff @(posedge clk or posedge reset) begin
845
                        if (reset) begin
846
                            in_narrow_or_fixed_reg               <= '0;
847
                            in_read_but_not_fixed_or_narrow_reg  <= '0;
848
                            in_write_but_not_fixed_or_narrow_reg <= '0;
849
                            in_default_converter_reg             <= '0;
850
                        end else begin
851
                            if (sink0_pipe_ready & sink0_pipe_valid) begin
852
                                in_narrow_or_fixed_reg               <= in_narrow_or_fixed;
853
                                in_read_but_not_fixed_or_narrow_reg  <= in_read_but_not_fixed_or_narrow;
854
                                in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow;
855
                                in_default_converter_reg             <= in_default_converter;
856
                            end // if (sink0_pipe_ready & sink0_pipe_valid)
857
                        end // else: !if(reset)
858
                    end // always_ff @
859
                    always_comb begin
860
                        d0_first_len                         = first_len;
861
                        d0_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow;
862
                        d0_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow;
863
                        d0_in_default_converter              = in_default_converter;
864
                        d1_in_narrow_or_fixed                = in_narrow_or_fixed_reg;
865
                        d1_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow_reg;
866
                        d1_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow_reg;
867
                        d1_in_default_converter              = in_default_converter_reg;
868
                    end // always_comb
869
                end // block: NO_PIPELINE_INPUT
870
                else begin : PIPELINE_INPUT
871
                    always_ff @(posedge clk or posedge reset) begin
872
                        if (reset) begin
873
                            in_narrow_or_fixed_reg               <= '0;
874
                            in_read_but_not_fixed_or_narrow_reg  <= '0;
875
                            in_write_but_not_fixed_or_narrow_reg <= '0;
876
                            in_default_converter_reg             <= '0;
877
                            d1_in_narrow_or_fixed                <= '0;
878
                            d1_in_read_but_not_fixed_or_narrow   <= '0;
879
                            d1_in_write_but_not_fixed_or_narrow  <= '0;
880
                            d1_in_default_converter              <= '0;
881
                            first_len_reg                        <= '0;
882
                        end else begin
883
                            if (sink0_pipe_ready & sink0_pipe_valid) begin
884
                                in_narrow_or_fixed_reg               <= in_narrow_or_fixed;
885
                                in_read_but_not_fixed_or_narrow_reg  <= in_read_but_not_fixed_or_narrow;
886
                                in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow;
887
                                in_default_converter_reg             <= in_default_converter;
888
                            end // if (sink0_pipe_ready & sink0_pipe_valid)
889
                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
890
                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
891
                                first_len_reg                       <= first_len;
892
                                d1_in_narrow_or_fixed               <= in_narrow_or_fixed_reg;
893
                                d1_in_read_but_not_fixed_or_narrow  <= in_read_but_not_fixed_or_narrow_reg;
894
                                d1_in_write_but_not_fixed_or_narrow <= in_write_but_not_fixed_or_narrow_reg;
895
                                d1_in_default_converter             <= in_default_converter_reg;
896
                            end
897
                        end // else: !if(reset)
898
                    end // always_ff @
899
                    always_comb begin
900
                        d0_in_default_converter              = in_default_converter_reg;
901
                        d0_first_len                         = first_len_reg;
902
                        d0_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow_reg;
903
                        d0_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow_reg;
904
                    end
905
                end // block: PIPELINE_INPUT
906
 
907
                // -------------------------------------------------------------------------
908
                // II. First length calculation
909
                // -------------------------------------------------------------------------
910
                wire same_boundary;
911
                // ----------------------------------------------------------
912
                // Slave is a wrapping slave, if in_burst wrap has same boundary
913
                // pass the burst untouched.
914
                // ----------------------------------------------------------
915
                if (OUT_BNDRY_ADDR_SEL_W <= PKT_BURSTWRAP_W - 1) begin
916
                    assign same_boundary = (in_boundary[OUT_BNDRY_ADDR_SEL_W] == 1);
917
                end else begin
918
                    assign same_boundary = 0;
919
                end
920
 
921
                // --------------------------------------------------------------------------
922
                // 1. If in_burst wrapping boundary is lager or INCR burst then always
923
                // send first sub_burst length is aligned to slave boudary,
924
                // 2. Else aligned to master boundary
925
                // Notes:
926
                // For INCR, it is tricky that the length can be any value but as the slave is
927
                // wrapping, still needs to convert the burst at slave boundary
928
                // (in_len <= len_to_out_bndry): can tell the in INCR burst can totally
929
                // fit in slave boundary -> pass thru
930
                // This works same way for INCOMPLETE wrap as well, so cannot make seperate
931
                // optimization when dont support INCOMPLETE wrap
932
                // --------------------------------------------------------------------------
933
                wire in_len_smaller_not_cross_out_bndry;
934
                wire in_len_smaller_not_cross_in_bndry;
935
 
936
                assign in_len_smaller_not_cross_out_bndry  = (in_len <= len_to_out_bndry);
937
                assign in_len_smaller_not_cross_in_bndry   = (in_len <= len_to_in_bndry);
938
                always_comb begin
939
                    if ((in_boundary > OUT_BOUNDARY) || (in_burstwrap[BNDRY_WIDTH - 1] == 1)) begin
940
                        first_len  = len_to_out_bndry;
941
                        if (in_len_smaller_not_cross_out_bndry || same_boundary)
942
                            first_len = in_len;
943
                    end
944
                    else begin
945
                        first_len  = len_to_in_bndry;
946
                        if (in_len_smaller_not_cross_in_bndry || same_boundary)
947
                            first_len = in_len;
948
                    end
949
                end // always_comb
950
 
951
                // -----------------------------------------------------------------------
952
                // III. Conveter enable signals: Turn on/off each conveter accordingly
953
                // -----------------------------------------------------------------------
954
                // WRAPPING AVALON: two conveters:
955
                //  1. wrap_burst_conveter    -> handle full_size INCR, WRAP
956
                //  2. default_burst_conveter -> handle narrow_size burst
957
                //  opt, seperate enable for write and reach
958
                // -----------------------------------------------------------------------
959
                // fixed_new_burst && new_burst : note this for incr_write as it is write_enable, cannot turn on incase a read happen before
960
                assign enable_incr_write_converter = (d0_in_valid && d0_in_write_but_not_fixed_or_narrow && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_but_not_fixed_or_narrow && !nb));
961
                assign enable_incr_read_converter  = (d0_in_valid && d0_in_read_but_not_fixed_or_narrow && fixed_new_burst && (source0_ready || !source0_valid) || (( state == ST_COMP_TRANS) && source0_ready && d1_in_read_but_not_fixed_or_narrow && !nb));
962
                assign enable_fixed_converter      = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
963
 
964
                // -----------------------------------------------------------------------
965
                // IV. Packet signals
966
                // -----------------------------------------------------------------------
967
                assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : new_burst)) ? 1'b0 : d0_in_sop;
968
                assign next_out_eop  = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : new_burst)  : d1_in_eop;
969
 
970
                // -----------------------------------------------------------------------
971
                // V. Output select
972
                // -----------------------------------------------------------------------
973
                assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt;
974
                assign out_addr      = d1_in_default_converter ? fixed_out_addr : incr_out_addr;
975
            end // if (IS_WRAP_AVALON_SLAVE)
976
 
977
            if (AXI_SLAVE) begin
978
                reg [IN_LEN_W - 1 : 0]   first_len_reg;
979
                reg                      d0_in_incr;
980
                reg                      d1_in_incr;
981
                reg                      in_incr_reg;
982
                wire                     in_read_wrap_conveter;
983
                wire                     in_write_wrap_conveter;
984
                reg                      in_read_wrap_conveter_reg;
985
                reg                      in_write_wrap_conveter_reg;
986
 
987
                reg                      d0_in_read_wrap_conveter;
988
                reg                      d0_in_write_wrap_conveter;
989
                reg                      d0_in_default_converter;
990
                reg                      d1_in_read_wrap_conveter;
991
                reg                      d1_in_write_wrap_conveter;
992
                reg                      d1_in_default_converter;
993
 
994
                wire                     in_incr                          = (in_bursttype == 2'b01) && !in_uncompressed_read;
995
                wire                     in_wrap                          = (in_bursttype == 2'b10);
996
                wire                     in_fixed                         = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
997
                wire                     in_narrow_read_wrap_smaller_16   = in_narrow && in_wrap && is_passthru && in_compressed_read;
998
                wire                     in_narrow_write_wrap_smaller_16  = in_narrow && in_wrap && is_passthru && in_write;
999
                wire                     in_narrow_wrap_larger_16         = in_narrow && in_wrap && !is_passthru;
1000
 
1001
                wire [PKT_BYTE_CNT_W  - 1 : 0]  wrap_out_byte_cnt;
1002
                wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
1003
                wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
1004
 
1005
                assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
1006
                assign wrap_out_byte_cnt  = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols;
1007
                assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
1008
 
1009
                assign in_full_size_read_wrap  = in_compressed_read & in_wrap & !in_narrow;
1010
                assign in_full_size_write_wrap = in_write & in_wrap & !in_narrow;
1011
                assign in_read_wrap_conveter   = in_full_size_read_wrap  || in_narrow_read_wrap_smaller_16;
1012
                assign in_write_wrap_conveter  = in_full_size_write_wrap || in_narrow_write_wrap_smaller_16;
1013
                assign in_default_converter    = in_narrow_wrap_larger_16 || in_fixed || in_uncompressed_read;
1014
 
1015
                //nb: new burst signal
1016
                assign nb                       = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst));
1017
                // is_passthru : still read from real input, as we want to shift 1 clock here, all control signal and first len
1018
                assign is_passthru = in_sop ? (in_passthru) : in_passthru_reg;
1019
 
1020
                //----------------------------------------------------------------
1021
                // I. Pipeline input stage
1022
                //----------------------------------------------------------------
1023
                if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
1024
                    always_ff @(posedge clk or posedge reset) begin
1025
                        if (reset) begin
1026
                            in_write_wrap_conveter_reg <= '0;
1027
                            in_read_wrap_conveter_reg  <= '0;
1028
                            in_default_converter_reg   <= '0;
1029
                            in_incr_reg                <= '0;
1030
                        end else begin
1031
                            if (sink0_pipe_ready & sink0_pipe_valid) begin
1032
                                in_write_wrap_conveter_reg <= in_write_wrap_conveter;
1033
                                in_read_wrap_conveter_reg  <= in_read_wrap_conveter;
1034
                                in_default_converter_reg   <= in_default_converter;
1035
                                in_incr_reg                <= in_incr;
1036
                            end
1037
                        end // else: !if(reset)
1038
                    end // always_ff @
1039
                    always_comb begin
1040
                        d0_in_incr                 = in_incr;
1041
                        d0_in_default_converter    = in_default_converter;
1042
                        d0_in_read_wrap_conveter   = in_read_wrap_conveter;
1043
                        d0_in_write_wrap_conveter  = in_write_wrap_conveter;
1044
                        d0_first_len               = first_len;
1045
                        d1_in_default_converter    = in_default_converter_reg;
1046
                        d1_in_read_wrap_conveter   = in_read_wrap_conveter_reg;
1047
                        d1_in_write_wrap_conveter  = in_write_wrap_conveter_reg;
1048
                        d1_in_incr                 = in_incr_reg;
1049
                        d0_in_bursttype            = nb ? in_bursttype : in_bursttype_reg;
1050
                    end
1051
                end
1052
                else begin : PIPELINE_INPUT
1053
                        reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
1054
                    always_ff @(posedge clk or posedge reset) begin
1055
                        if (reset) begin
1056
                            in_write_wrap_conveter_reg <= '0;
1057
                            in_read_wrap_conveter_reg  <= '0;
1058
                            in_default_converter_reg   <= '0;
1059
                            d1_in_default_converter    <= '0;
1060
                            d1_in_read_wrap_conveter   <= '0;
1061
                            d1_in_write_wrap_conveter  <= '0;
1062
                            first_len_reg              <= '0;
1063
                            in_incr_reg                <= '0;
1064
                            d0_in_bursttype_dl         <= '0;
1065
                        end else begin
1066
                            if (sink0_pipe_ready & in_valid) begin
1067
                                in_write_wrap_conveter_reg <= in_write_wrap_conveter;
1068
                                in_read_wrap_conveter_reg  <= in_read_wrap_conveter;
1069
                                in_default_converter_reg   <= in_default_converter;
1070
                                first_len_reg              <= first_len;
1071
                                in_incr_reg                <= in_incr;
1072
                            end
1073
                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
1074
                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
1075
                                d1_in_default_converter   <= in_default_converter_reg;
1076
                                d1_in_read_wrap_conveter  <= in_read_wrap_conveter_reg;
1077
                                d1_in_write_wrap_conveter <= in_write_wrap_conveter_reg;
1078
                                d1_in_incr                <= in_incr_reg;
1079
                                d0_in_bursttype_dl        <= in_bursttype_reg;
1080
                            end
1081
                        end // else: !if(reset)
1082
                    end // always_ff @
1083
                    always_comb begin
1084
                        d0_in_incr                 = in_incr_reg;
1085
                        d0_in_default_converter    = in_default_converter_reg;
1086
                        d0_in_read_wrap_conveter   = in_read_wrap_conveter_reg;
1087
                        d0_in_write_wrap_conveter  = in_write_wrap_conveter_reg;
1088
                        d0_first_len               = first_len_reg;
1089
                        d0_in_bursttype            = nb ? in_bursttype_reg : d0_in_bursttype_dl;
1090
                    end
1091
                end
1092
 
1093
                // -------------------------------------------------------------------------
1094
                // II. First length calculation
1095
                // -------------------------------------------------------------------------
1096
                // For AXI slave, avalon master must set alwaysBurstMaxBurst so
1097
                // INCOMPLETE wrap burst will not happen
1098
                // 1. If any wrapping burst that smaller than 16 -> pass thru
1099
                // 2. Else first sub_burst length is aligned to slave boundary
1100
                // -------------------------------------------------------------------------
1101
                //wire passthru = (in_len < len_to_out_bndry) || is_passthru; // why compare here? Keep this until we figure out why.
1102
                always_comb begin
1103
                    if (in_boundary > OUT_BOUNDARY) begin
1104
                        first_len = is_passthru ? in_len : len_to_out_bndry;
1105
                    end else begin
1106
                        first_len = is_passthru ? in_len : len_to_in_bndry;
1107
                    end
1108
                end // always_comb
1109
 
1110
                // -----------------------------------------------------------------------
1111
                // III. Conveter enable signals: Turn on/off each conveter accordingly
1112
                // -----------------------------------------------------------------------
1113
                // AXI slave: three conveters:
1114
                //  1. wrap_burst_conveter    -> handle WRAP
1115
                //     1.1 : full size wrap   --> convert to fit in slave boundary
1116
                //     1.2 : narrow size wrap
1117
                //                            ---> <= 16 : pass thru
1118
                //                            ---> > 16 : convert to non-bursting
1119
                //  2. incr_burst_convter     -> handle full/narrow size INCR
1120
                //  3. default_burst_conveter -> handle FIXED
1121
                // -----------------------------------------------------------------------
1122
                // Note: narrow wrap with length larger 16 can happen with Avalon narrow wraping
1123
                // master to AXI slave. To support this, it will hurt fmax
1124
                // also the WA adapter currently not pack data in this case, to be better support
1125
                // need to start from WA first
1126
                // -----------------------------------------------------------------------
1127
                assign new_burst                   = incr_new_burst && wrap_new_burst;
1128
                assign enable_incr_converter       = (d0_in_valid && d0_in_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_incr && !nb));
1129
                assign enable_write_wrap_converter = (d0_in_valid && d0_in_write_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_wrap_conveter && !nb));
1130
                assign enable_read_wrap_converter  = (d0_in_valid && d0_in_read_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_read_wrap_conveter && !nb));
1131
                assign enable_fixed_converter      = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
1132
 
1133
                // -----------------------------------------------------------------------
1134
                // IV. Packet signals
1135
                // -----------------------------------------------------------------------
1136
                assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop;
1137
                assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))  : d1_in_eop;
1138
 
1139
                // -----------------------------------------------------------------------
1140
                // V. Output select
1141
                // -----------------------------------------------------------------------
1142
                assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt);
1143
                assign out_addr      = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr);
1144
            end // if (AXI_SLAVE)
1145
 
1146
            if (IS_INCR_SLAVE) begin
1147
                reg [IN_LEN_W - 1 : 0]   first_len_reg;
1148
                reg                      d0_in_default_converter;
1149
                reg                      d0_in_full_size_incr;
1150
                reg                      d0_in_full_size_write_wrap;
1151
                reg                      d0_in_full_size_read_wrap;
1152
                reg                      d1_in_default_converter;
1153
                reg                      d1_in_full_size_incr;
1154
                reg                      d1_in_full_size_write_wrap;
1155
                reg                      d1_in_full_size_read_wrap;
1156
                reg                      d1_in_incr;
1157
                reg                      in_incr_reg;
1158
                wire                     in_incr  = (in_bursttype == 2'b01);
1159
                wire                     in_wrap  = (in_bursttype == 2'b10);
1160
 
1161
                wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
1162
                wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
1163
 
1164
                assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
1165
                assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
1166
 
1167
                if (NO_WRAP_SUPPORT) begin
1168
                    assign in_default_converter      = !in_full_size_incr;
1169
                    assign nb   = d1_in_default_converter ? fixed_new_burst : incr_new_burst;
1170
                end
1171
                else begin
1172
                    wire    in_narrow_incr;
1173
                    wire    in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
1174
 
1175
                    assign in_narrow_incr       = in_incr & in_narrow;
1176
                    assign in_default_converter = in_fixed || in_narrow || in_narrow_incr || in_uncompressed_read;
1177
                    assign nb                   = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst));
1178
                end
1179
 
1180
                assign in_full_size_incr         = in_incr & !in_narrow & !in_uncompressed_read;
1181
                assign in_full_size_write_wrap   = in_write & in_wrap & !in_narrow;
1182
                assign in_full_size_read_wrap    = in_compressed_read & in_wrap & !in_narrow;
1183
 
1184
                //----------------------------------------------------------------
1185
                // I. Pipeline input stage
1186
                //----------------------------------------------------------------
1187
                if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
1188
                    always_ff @(posedge clk or posedge reset) begin
1189
                        if (reset) begin
1190
                            in_full_size_write_wrap_reg <= '0;
1191
                            in_full_size_read_wrap_reg  <= '0;
1192
                            in_full_size_incr_reg       <= '0;
1193
                            in_default_converter_reg    <= '0;
1194
                            in_incr_reg                 <= '0;
1195
                        end else begin
1196
                            if (sink0_pipe_ready & sink0_pipe_valid) begin
1197
                                in_incr_reg                 <= in_incr;
1198
                                in_full_size_incr_reg       <= in_full_size_incr;
1199
                                in_full_size_write_wrap_reg <= in_full_size_write_wrap;
1200
                                in_full_size_read_wrap_reg  <= in_full_size_read_wrap;
1201
                                in_default_converter_reg    <= in_default_converter;
1202
                            end
1203
                        end // else: !if(reset)
1204
                    end // always_ff @
1205
                    always_comb begin
1206
                        d0_in_default_converter     = in_default_converter;
1207
                        d0_in_full_size_incr        = in_full_size_incr;
1208
                        d0_in_full_size_write_wrap  = in_full_size_write_wrap;
1209
                        d0_in_full_size_read_wrap   = in_full_size_read_wrap;
1210
                        d0_first_len                = first_len;
1211
                        d1_in_incr                  = in_incr_reg;
1212
                        d1_in_default_converter     = in_default_converter_reg;
1213
                        d1_in_full_size_incr        = in_full_size_incr_reg;
1214
                        d1_in_full_size_write_wrap  = in_full_size_write_wrap_reg;
1215
                        d1_in_full_size_read_wrap   = in_full_size_read_wrap_reg;
1216
                        d0_in_bursttype             = nb ? in_bursttype : in_bursttype_reg;
1217
                    end
1218
                end
1219
                else begin : PIPELINE_INPUT
1220
                    reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
1221
                    always_ff @(posedge clk or posedge reset) begin
1222
                        if (reset) begin
1223
                            in_full_size_write_wrap_reg <= '0;
1224
                            in_full_size_read_wrap_reg  <= '0;
1225
                            in_full_size_incr_reg       <= '0;
1226
                            in_default_converter_reg    <= '0;
1227
                            d1_in_default_converter     <= '0;
1228
                            d1_in_full_size_incr        <= '0;
1229
                            d1_in_full_size_write_wrap  <= '0;
1230
                            d1_in_full_size_read_wrap   <= '0;
1231
                            d1_in_incr                  <= '0;
1232
                            first_len_reg               <= '0;
1233
                            in_incr_reg                 <= '0;
1234
                            d0_in_bursttype_dl          <= '0;
1235
                        end else begin
1236
                            if (sink0_pipe_ready & in_valid) begin
1237
                                in_full_size_incr_reg       <= in_full_size_incr;
1238
                                in_full_size_write_wrap_reg <= in_full_size_write_wrap;
1239
                                in_full_size_read_wrap_reg  <= in_full_size_read_wrap;
1240
                                in_default_converter_reg    <= in_default_converter;
1241
                                in_incr_reg                 <= in_incr;
1242
                                first_len_reg               <= first_len;
1243
                            end
1244
                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
1245
                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
1246
                                d1_in_default_converter    <= in_default_converter_reg;
1247
                                d1_in_full_size_incr       <= in_full_size_incr_reg;
1248
                                d1_in_full_size_write_wrap <= in_full_size_write_wrap_reg;
1249
                                d1_in_full_size_read_wrap  <= in_full_size_read_wrap_reg;
1250
                                d1_in_incr                 <= in_incr_reg;
1251
                                d0_in_bursttype_dl         <= in_bursttype_reg;
1252
                            end
1253
                        end // else: !if(reset)
1254
                    end // always_ff @
1255
                    always_comb begin
1256
                        d0_in_default_converter     = in_default_converter_reg;
1257
                        d0_in_full_size_incr        = in_full_size_incr_reg;
1258
                        d0_in_full_size_write_wrap  = in_full_size_write_wrap_reg;
1259
                        d0_in_full_size_read_wrap   = in_full_size_read_wrap_reg;
1260
                        d0_first_len                = first_len_reg;
1261
                        d0_in_bursttype             = nb ? in_bursttype_reg : d0_in_bursttype_dl;
1262
                    end
1263
                end
1264
 
1265
                // --------------------------------------------------------------------------------------
1266
                // II. First length calculation
1267
                // --------------------------------------------------------------------------------------
1268
                // Note: the slave is INCR slave, in pratical is has no boundary so if in burst is wrap
1269
                // the sub burst can send out "slave max length" first fs the in burst not yet wraps back
1270
                // To simplify and optimize: the first sub_burst length stills send out aligned length first
1271
                // --------------------------------------------------------------------------------------
1272
                // If no INCOMPLETE wrap burst
1273
                // 1. in_boundary is larger out_boundary; first sub_burst length is: aligned to out boundary
1274
                // 2. in_boundary is smaller out_boundary; first sub_burst length is: aligned to in boundary
1275
                // --------------------------------------------------------------------------------------
1276
                if (!NO_WRAP_SUPPORT) begin : HAVE_WRAP_BURSTING_SUPPORT
1277
                    if (!INCOMPLETE_WRAP_SUPPORT) begin : no_incomplete_wrap_support
1278
                        assign first_len = (in_boundary > OUT_BOUNDARY) ? len_to_out_bndry : len_to_in_bndry;
1279
                    end
1280
                    else begin : incomplete_wrap_support
1281
                        // -------------------------------------------------------------------------
1282
                        // If INCOMPLETE wrap support
1283
                        // 1. The idea is still same, based on boundary and select either aligned to in/out boundary
1284
                        // 2. But need to check if in_len is smaller to "aligned" in/out boundary for incomplete case
1285
                        // -> the burst is pass thru is in_len is smaller
1286
                        // -------------------------------------------------------------------------
1287
                        wire in_len_smaller_aligned_out_bdry = (in_len <= len_to_out_bndry);
1288
                        wire in_len_smaller_aligned_in_bdry  = (in_len <= len_to_in_bndry);
1289
                        always_comb begin
1290
                            if (in_boundary > OUT_BOUNDARY) begin
1291
                                first_len = (in_len_smaller_aligned_out_bdry) ? in_len : len_to_out_bndry;
1292
                            end
1293
                            else begin
1294
                                first_len = (in_len_smaller_aligned_in_bdry) ? in_len : len_to_in_bndry;
1295
                            end
1296
                        end
1297
                    end // block: incomplete_wrap_support
1298
                end
1299
 
1300
                // -----------------------------------------------------------------------
1301
                // III. Conveter enable signals: Turn on/off each conveter accordingly
1302
                // -----------------------------------------------------------------------
1303
                // INCR slave: three conveters:
1304
                //  1. wrap_burst_conveter    -> handle WRAP
1305
                //  2. incr_burst_convter     -> handle INCR
1306
                //  2. default_burst_conveter -> handle narrow burst
1307
                // -----------------------------------------------------------------------
1308
                // -----------------------------------------------------------------------
1309
                // Purposely support AXI to Avalon: with no wrapping suppport
1310
                // all wrapping transaction witll be converted to non-bursting sub-burst
1311
                // 21-January-2014
1312
                // -----------------------------------------------------------------------
1313
                if (NO_WRAP_SUPPORT) begin
1314
                    assign enable_incr_converter        = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb));
1315
                    assign enable_fixed_converter       = (d0_in_valid && d0_in_default_converter && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
1316
 
1317
                    // -----------------------------------------------------------------------
1318
                    // IV. Packet signals
1319
                    // -----------------------------------------------------------------------
1320
                    assign next_out_sop  = (state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : incr_new_burst) ? 1'b0 : d0_in_sop;
1321
                    assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : incr_new_burst)  : d1_in_eop;
1322
 
1323
                    // -----------------------------------------------------------------------
1324
                    // V. Output select
1325
                    // -----------------------------------------------------------------------
1326
                    assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt;
1327
                    assign out_addr  = d1_in_default_converter ? fixed_out_addr : incr_out_addr;
1328
                end
1329
                else begin
1330
                    assign new_burst                    = incr_new_burst && wrap_new_burst;
1331
                    assign enable_incr_converter        = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb));
1332
                    assign enable_fixed_converter       = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
1333
                    assign enable_write_wrap_converter  = (d0_in_valid && d0_in_full_size_write_wrap && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_write_wrap && !nb));
1334
                    assign enable_read_wrap_converter   = (d0_in_valid && d0_in_full_size_read_wrap  && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_read_wrap && !nb));
1335
 
1336
                    // -----------------------------------------------------------------------
1337
                    // IV. Packet signals
1338
                    // -----------------------------------------------------------------------
1339
                    assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop;
1340
                    assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))  : d1_in_eop;
1341
 
1342
                    // -----------------------------------------------------------------------
1343
                    // V. Output select
1344
                    // -----------------------------------------------------------------------
1345
                    wire [PKT_BYTE_CNT_W  - 1 : 0]  wrap_out_byte_cnt;
1346
                    assign wrap_out_byte_cnt    = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols;
1347
 
1348
                    assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt);
1349
                    assign out_addr  = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr);
1350
                end
1351
            end
1352
        end
1353
    endgenerate
1354
 
1355
    // --------------------------------------------------
1356
    // Control signals
1357
    // --------------------------------------------------
1358
    reg   source0_valid_reg;
1359
    wire  next_source0_valid;
1360
    reg   source0_startofpacket_reg;
1361
 
1362
    wire  is_write;
1363
    assign is_write  = nb ? (d0_in_write) : d1_in_write;
1364
 
1365
    //-------------------------------------------------------------------------
1366
    // Handshaking and packet signals
1367
    // -----------------------------------------------------------------------
1368
    // source0_valid: takes from in sink_valid unless read then wait until end_of_packet
1369
    assign next_source0_valid  = ((state == ST_COMP_TRANS) & !source0_endofpacket) ? 1'b1 : d0_in_valid;
1370
 
1371
    // sink0_ready needs always to be asserted first, hold one after reset
1372
    assign sink0_pipe_ready  = (state == ST_UNCOMP_TRANS) ? source0_ready || !source0_valid : (state == ST_COMP_TRANS) ? nb && source0_ready || !source0_valid : in_ready_hold;
1373
 
1374
    always_ff @(posedge clk or posedge reset) begin
1375
        if (reset)  begin
1376
            source0_valid_reg         <= '0;
1377
            source0_startofpacket_reg <= '1;
1378
        end else begin
1379
            if (~source0_valid | source0_ready) begin
1380
                source0_valid_reg         <= next_source0_valid;
1381
                source0_startofpacket_reg <= next_out_sop;
1382
            end
1383
        end // else: !if(reset)
1384
    end // always_ff @
1385
 
1386
    // Assign output signals
1387
    always_comb begin
1388
        source0_endofpacket    = next_out_eop;
1389
        source0_startofpacket  = source0_startofpacket_reg;
1390
        source0_valid          = source0_valid_reg;
1391
    end
1392
 
1393
    // --------------------------------------------------
1394
    // Converters instantiation and signal mappings.
1395
    // --------------------------------------------------
1396
    generate
1397
        if (NON_BURSTING_SLAVE) begin : non_bursting_slave_converters_sel
1398
            altera_default_burst_converter
1399
            #(
1400
             .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
1401
             .PKT_ADDR_W          (PKT_ADDR_W),
1402
             .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
1403
             .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
1404
             .LEN_W               (IN_LEN_W),
1405
             .IS_AXI_SLAVE        (AXI_SLAVE)
1406
            )
1407
            the_default_burst_converter
1408
            (
1409
             .clk                       (clk),
1410
             .reset                     (reset),
1411
             .enable                    (enable_fixed_converter), // turn on if a fixed
1412
             .in_addr                   (d0_in_aligned_addr),
1413
             .in_addr_reg               (d1_in_aligned_addr),
1414
             .in_bursttype              (d0_in_bursttype),
1415
             .in_burstwrap_reg          (d1_in_burstwrap),
1416
             .in_burstwrap_value        (d0_in_burstwrap_value),
1417
             .in_len                    (d0_in_len),
1418
             .in_size_value             (d0_in_size_value),
1419
             .in_is_write               (is_write),
1420
             .out_len                   (fixed_out_len),
1421
             .out_addr                  (fixed_out_addr),
1422
             .new_burst                 (fixed_new_burst)
1423
            );
1424
        end
1425
        else if (INCR_AVALON_SYS) begin : system_purely_avalon_converter_sel
1426
            //-----------------------------------------------------------------
1427
            // When system is purely INCR, only need one converter.
1428
            //-----------------------------------------------------------------
1429
            altera_incr_burst_converter
1430
            #(
1431
             .MAX_IN_LEN          (MAX_IN_LEN),
1432
             .MAX_OUT_LEN         (MAX_OUT_LEN),
1433
             .ADDR_WIDTH          (PKT_ADDR_W),
1434
             .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
1435
             .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
1436
             .IN_NARROW_SIZE      (IN_NARROW_SIZE),
1437
             .NUM_SYMBOLS         (NUM_SYMBOLS),
1438
             .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
1439
            )
1440
            the_converter_for_avalon_incr_slave
1441
            (
1442
             .clk                     (clk),
1443
             .reset                   (reset),
1444
             .enable                  (enable_incr_converter),
1445
             .in_len                  (d0_in_len),
1446
             .in_sop                  (d0_in_sop),
1447
             .in_burstwrap_reg        (d1_in_burstwrap),
1448
             .in_size_t               (d0_in_size),
1449
             .in_size_reg             (d1_in_size),
1450
             .in_addr                 (d0_in_aligned_addr),
1451
             .in_addr_reg             (d1_in_aligned_addr),
1452
             .is_write                (is_write),
1453
             .out_len                 (incr_out_len),
1454
             .uncompr_out_len         (incr_uncompr_out_len),
1455
             .out_addr                (incr_out_addr),
1456
             .new_burst_export        (incr_new_burst)
1457
            );
1458
        end
1459
        else begin : converters_selection
1460
            if (IS_WRAP_AVALON_SLAVE) begin : wrapping_avalon_slave_converter_sel
1461
                altera_wrap_burst_converter
1462
                #(
1463
                 .MAX_IN_LEN            (MAX_IN_LEN),
1464
                 .MAX_OUT_LEN           (MAX_OUT_LEN),
1465
                 .ADDR_WIDTH            (PKT_ADDR_W),
1466
                 .BNDRY_WIDTH           (PKT_BURSTWRAP_W),
1467
                 .AXI_SLAVE             (AXI_SLAVE),
1468
                 .NUM_SYMBOLS           (NUM_SYMBOLS),
1469
                 .OPTIMIZE_WRITE_BURST  (0)
1470
                )
1471
                the_converter_for_avalon_wrap_slave
1472
                (
1473
                 .clk                               (clk),
1474
                 .reset                             (reset),
1475
                 .enable_read                       (enable_incr_read_converter),
1476
                 .enable_write                      (enable_incr_write_converter),
1477
                 .in_len                            (d0_in_len),
1478
                 .first_len                         (d0_first_len),
1479
                 .in_sop                            (d0_in_sop),
1480
                 .in_burstwrap                      (d0_in_burstwrap),
1481
                 .in_burstwrap_reg                  (d1_in_burstwrap),
1482
                 .in_boundary                       (in_boundary),
1483
                 .in_addr                           (d0_in_aligned_addr),
1484
                 .in_addr_reg                       (d1_in_aligned_addr),
1485
                 .out_len                           (incr_out_len),
1486
                 .uncompr_out_len                   (incr_uncompr_out_len),
1487
                 .out_addr                          (incr_out_addr),
1488
                 .new_burst_export                  (new_burst)
1489
                );
1490
 
1491
                altera_default_burst_converter
1492
                #(
1493
                 .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
1494
                 .PKT_ADDR_W          (PKT_ADDR_W),
1495
                 .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
1496
                 .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
1497
                 .LEN_W               (IN_LEN_W),
1498
                 .IS_AXI_SLAVE        (AXI_SLAVE)
1499
                )
1500
                the_default_burst_converter
1501
                (
1502
                 .clk                       (clk),
1503
                 .reset                     (reset),
1504
                 .enable                    (enable_fixed_converter), // turn on if a fixed
1505
                 .in_addr                   (d0_in_aligned_addr),
1506
                 .in_addr_reg               (d1_in_aligned_addr),
1507
                 .in_bursttype              (d0_in_bursttype),
1508
                 .in_burstwrap_reg          (d1_in_burstwrap),
1509
                 .in_burstwrap_value        (d0_in_burstwrap_value),
1510
                 .in_len                    (d0_in_len),
1511
                 .in_size_value             (d0_in_size_value),
1512
                 .in_is_write               (is_write),
1513
                 .out_len                   (fixed_out_len),
1514
                 .out_addr                  (fixed_out_addr),
1515
                 .new_burst                 (fixed_new_burst)
1516
                );
1517
            end
1518
            if (AXI_SLAVE) begin : axi_slave_converter_sel
1519
                altera_wrap_burst_converter
1520
                #(
1521
                 .MAX_IN_LEN              (MAX_IN_LEN),
1522
                 .MAX_OUT_LEN             (MAX_OUT_LEN),
1523
                 .ADDR_WIDTH              (PKT_ADDR_W),
1524
                 .BNDRY_WIDTH             (PKT_BURSTWRAP_W),
1525
                 .NUM_SYMBOLS             (NUM_SYMBOLS),
1526
                 .AXI_SLAVE               (AXI_SLAVE),
1527
                 .OPTIMIZE_WRITE_BURST    (0)
1528
                )
1529
                the_converter_for_avalon_wrap_slave
1530
                (
1531
                 .clk                               (clk),
1532
                 .reset                             (reset),
1533
                 .enable_read                       (enable_read_wrap_converter),
1534
                 .enable_write                      (enable_write_wrap_converter),
1535
                 .in_len                            (d0_in_len),
1536
                 .first_len                         (d0_first_len),
1537
                 .in_sop                            (d0_in_sop),
1538
                 .in_burstwrap                      (d0_in_burstwrap),
1539
                 .in_burstwrap_reg                  (d1_in_burstwrap),
1540
                 .in_boundary                       (in_boundary),
1541
                 .in_addr                           (d0_in_aligned_addr),
1542
                 .in_addr_reg                       (d1_in_aligned_addr),
1543
                 .out_len                           (wrap_out_len),
1544
                 .uncompr_out_len                   (wrap_uncompr_out_len),
1545
                 .out_addr                          (wrap_out_addr),
1546
                 .new_burst_export                  (wrap_new_burst)
1547
                );
1548
 
1549
                altera_incr_burst_converter
1550
                #(
1551
                 .MAX_IN_LEN          (MAX_IN_LEN),
1552
                 .MAX_OUT_LEN         (MAX_OUT_LEN),
1553
                 .ADDR_WIDTH          (PKT_ADDR_W),
1554
                 .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
1555
                 .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
1556
                 .IN_NARROW_SIZE      (IN_NARROW_SIZE),
1557
                 .NUM_SYMBOLS         (NUM_SYMBOLS),
1558
                 .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
1559
                )
1560
                the_converter_for_avalon_incr_slave
1561
                (
1562
                 .clk                (clk),
1563
                 .reset              (reset),
1564
                 .enable             (enable_incr_converter),
1565
                 .in_len             (d0_in_len),
1566
                 .in_sop             (d0_in_sop),
1567
                 .in_burstwrap_reg   (d1_in_burstwrap),
1568
                 .in_size_t          (d0_in_size),
1569
                 .in_size_reg        (d1_in_size),
1570
                 .in_addr            (d0_in_aligned_addr),
1571
                 .in_addr_reg        (d1_in_aligned_addr),
1572
                 .is_write           (is_write),
1573
                 .out_len            (incr_out_len),
1574
                 .uncompr_out_len    (incr_uncompr_out_len),
1575
                 .out_addr           (incr_out_addr),
1576
                 .new_burst_export   (incr_new_burst)
1577
                );
1578
 
1579
                // --------------------------------------------------
1580
                // The fixed burst converter module
1581
                // --------------------------------------------------
1582
                altera_default_burst_converter
1583
                #(
1584
                 .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
1585
                 .PKT_ADDR_W          (PKT_ADDR_W),
1586
                 .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
1587
                 .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
1588
                 .LEN_W               (IN_LEN_W),
1589
                 .IS_AXI_SLAVE        (AXI_SLAVE)
1590
                )
1591
                the_default_burst_converter
1592
                (
1593
                 .clk                       (clk),
1594
                 .reset                     (reset),
1595
                 .enable                    (enable_fixed_converter), // turn on if a fixed
1596
                 .in_addr                   (d0_in_aligned_addr),
1597
                 .in_addr_reg               (d1_in_aligned_addr),
1598
                 .in_bursttype              (d0_in_bursttype),
1599
                 .in_burstwrap_reg          (d1_in_burstwrap),
1600
                 .in_burstwrap_value        (d0_in_burstwrap_value),
1601
                 .in_len                    (d0_in_len),
1602
                 .in_size_value             (d0_in_size_value),
1603
                 .in_is_write               (is_write),
1604
                 .out_len                   (fixed_out_len),
1605
                 .out_addr                  (fixed_out_addr),
1606
                 .new_burst                 (fixed_new_burst)
1607
                );
1608
            end
1609
            if (IS_INCR_SLAVE) begin : incr_slave_converter_sel
1610
                if (NO_WRAP_SUPPORT) begin : no_wrap_incr_slave_converter_sel
1611
                    altera_incr_burst_converter
1612
                    #(
1613
                     .MAX_IN_LEN          (MAX_IN_LEN),
1614
                     .MAX_OUT_LEN         (MAX_OUT_LEN),
1615
                     .ADDR_WIDTH          (PKT_ADDR_W),
1616
                     .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
1617
                     .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
1618
                     .IN_NARROW_SIZE      (0), // not support narrow as this is INCR avalon slave
1619
                     .NUM_SYMBOLS         (NUM_SYMBOLS),
1620
                     .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
1621
                    )
1622
                    the_converter_for_avalon_incr_slave
1623
                    (
1624
                     .clk                (clk),
1625
                     .reset              (reset),
1626
                     .enable             (enable_incr_converter),
1627
                     .in_len             (d0_in_len),
1628
                     .in_sop             (d0_in_sop),
1629
                     .in_burstwrap_reg   (d1_in_burstwrap),
1630
                     .in_size_t          (d0_in_size),
1631
                     .in_size_reg        (d1_in_size),
1632
                     .in_addr            (d0_in_aligned_addr),
1633
                     .in_addr_reg        (d1_in_aligned_addr),
1634
                     .is_write           (is_write),
1635
                     .out_len            (incr_out_len),
1636
                     .uncompr_out_len    (incr_uncompr_out_len),
1637
                     .out_addr           (incr_out_addr),
1638
                     .new_burst_export   (incr_new_burst)
1639
                    );
1640
 
1641
                    // --------------------------------------------------
1642
                    // The default converter
1643
                    // --------------------------------------------------
1644
                    altera_default_burst_converter
1645
                    #(
1646
                     .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
1647
                     .PKT_ADDR_W          (PKT_ADDR_W),
1648
                     .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
1649
                     .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
1650
                     .LEN_W               (IN_LEN_W),
1651
                     .IS_AXI_SLAVE        (AXI_SLAVE)
1652
                    )
1653
                    the_default_burst_converter
1654
                    (
1655
                     .clk                       (clk),
1656
                     .reset                     (reset),
1657
                     .enable                    (enable_fixed_converter), // turn on if a fixed
1658
                     .in_addr                   (d0_in_aligned_addr),
1659
                     .in_addr_reg               (d1_in_aligned_addr),
1660
                     .in_bursttype              (d0_in_bursttype),
1661
                     .in_burstwrap_reg          (d1_in_burstwrap),
1662
                     .in_burstwrap_value        (d0_in_burstwrap_value),
1663
                     .in_len                    (d0_in_len),
1664
                     .in_size_value             (d0_in_size_value),
1665
                     .in_is_write               (is_write),
1666
                     .out_len                   (fixed_out_len),
1667
                     .out_addr                  (fixed_out_addr),
1668
                     .new_burst                 (fixed_new_burst)
1669
                    );
1670
                end
1671
                else begin : wrap_incr_slave_conveter_sel
1672
                    altera_wrap_burst_converter
1673
                    #(
1674
                     .MAX_IN_LEN              (MAX_IN_LEN),
1675
                     .MAX_OUT_LEN             (MAX_OUT_LEN),
1676
                     .ADDR_WIDTH              (PKT_ADDR_W),
1677
                     .BNDRY_WIDTH             (PKT_BURSTWRAP_W),
1678
                     .NUM_SYMBOLS             (NUM_SYMBOLS),
1679
                     .AXI_SLAVE               (AXI_SLAVE),
1680
                     .OPTIMIZE_WRITE_BURST    (0)
1681
                    )
1682
                    the_converter_for_avalon_wrap_slave
1683
                    (
1684
                     .clk                               (clk),
1685
                     .reset                             (reset),
1686
                     .enable_read                       (enable_read_wrap_converter),
1687
                     .enable_write                      (enable_write_wrap_converter),
1688
                     .in_len                            (d0_in_len),
1689
                     .first_len                         (d0_first_len),
1690
                     .in_sop                            (d0_in_sop),
1691
                     .in_burstwrap                      (d0_in_burstwrap),
1692
                     .in_burstwrap_reg                  (d1_in_burstwrap),
1693
                     .in_boundary                       (in_boundary),
1694
                     .in_addr                           (d0_in_aligned_addr),
1695
                     .in_addr_reg                       (d1_in_aligned_addr),
1696
                     .out_len                           (wrap_out_len),
1697
                     .uncompr_out_len                   (wrap_uncompr_out_len),
1698
                     .out_addr                          (wrap_out_addr),
1699
                     .new_burst_export                  (wrap_new_burst)
1700
                    );
1701
 
1702
                    altera_incr_burst_converter
1703
                    #(
1704
                     .MAX_IN_LEN          (MAX_IN_LEN),
1705
                     .MAX_OUT_LEN         (MAX_OUT_LEN),
1706
                     .ADDR_WIDTH          (PKT_ADDR_W),
1707
                     .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
1708
                     .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
1709
                     .IN_NARROW_SIZE      (IN_NARROW_SIZE),
1710
                     .NUM_SYMBOLS         (NUM_SYMBOLS),
1711
                     .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
1712
                    )
1713
                    the_converter_for_avalon_incr_slave
1714
                    (
1715
                     .clk                     (clk),
1716
                     .reset                   (reset),
1717
                     .enable                  (enable_incr_converter),
1718
                     .in_len                  (d0_in_len),
1719
                     .in_sop                  (d0_in_sop),
1720
                     .in_burstwrap_reg        (d1_in_burstwrap),
1721
                     .in_size_t               (d0_in_size),
1722
                     .in_size_reg             (d1_in_size),
1723
                     .in_addr                 (d0_in_aligned_addr),
1724
                     .in_addr_reg             (d1_in_aligned_addr),
1725
                     .is_write                (is_write),
1726
                     .out_len                 (incr_out_len),
1727
                     .uncompr_out_len         (incr_uncompr_out_len),
1728
                     .out_addr                (incr_out_addr),
1729
                     .new_burst_export        (incr_new_burst)
1730
                    );
1731
 
1732
                    // --------------------------------------------------
1733
                    // The fixed burst converter module
1734
                    // --------------------------------------------------
1735
                    altera_default_burst_converter
1736
                    #(
1737
                     .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
1738
                     .PKT_ADDR_W          (PKT_ADDR_W),
1739
                     .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
1740
                     .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
1741
                     .LEN_W               (IN_LEN_W),
1742
                     .IS_AXI_SLAVE        (AXI_SLAVE)
1743
                    )
1744
                    the_default_burst_converter
1745
                    (
1746
                     .clk                       (clk),
1747
                     .reset                     (reset),
1748
                     .enable                    (enable_fixed_converter), // turn on if a fixed
1749
                     .in_addr                   (d0_in_aligned_addr),
1750
                     .in_addr_reg               (d1_in_aligned_addr),
1751
                     .in_bursttype              (d0_in_bursttype),
1752
                     .in_burstwrap_reg          (d1_in_burstwrap),
1753
                     .in_burstwrap_value        (d0_in_burstwrap_value),
1754
                     .in_len                    (d0_in_len),
1755
                     .in_size_value             (d0_in_size_value),
1756
                     .in_is_write               (is_write),
1757
                     .out_len                   (fixed_out_len),
1758
                     .out_addr                  (fixed_out_addr),
1759
                     .new_burst                 (fixed_new_burst)
1760
                    );
1761
                end
1762
            end
1763
        end
1764
    endgenerate
1765
 
1766
    // --------------------------------------------------
1767
    // Ceil(log2()) function
1768
    // --------------------------------------------------
1769
    function unsigned[63:0] log2ceil;
1770
        input reg [63:0] val;
1771
        reg [63:0]       i;
1772
        begin
1773
            i = 1;
1774
            log2ceil = 0;
1775
 
1776
            while (i < val) begin
1777
                log2ceil = log2ceil + 1;
1778
                i = i << 1;
1779
            end
1780
        end
1781
    endfunction
1782
 
1783
    // ---------------------------------------------------
1784
    // Mapping of output signals.
1785
    // ---------------------------------------------------
1786
    wire load_next_output_pck  = source0_ready | !source0_valid;
1787
    always_ff @(posedge clk or posedge reset) begin
1788
        if (reset) begin
1789
            uncompr_out_addr <= '0;
1790
        end
1791
        else if (load_next_output_pck) begin
1792
            uncompr_out_addr <= d0_in_addr;
1793
        end
1794
 
1795
    end
1796
 
1797
    // ---------------------------------------------------
1798
    // Out burstype
1799
    // ---------------------------------------------------
1800
    // If AXI slave, out_bursttype = INCR if either of the following 2 conditions is met:
1801
    //  1) in_passthru (i.e. the input burst count < 16).
1802
    //  2) input packet has bursttype == REP_WRAP (Repeated Wrap).
1803
    // Else, out_bursttype = in_bursttype.
1804
    // For all other slaves, change the bursttype to INCR.
1805
    wire [PKT_BURST_TYPE_W - 1 : 0] out_bursttype;
1806
    generate
1807
        if (AXI_SLAVE) begin : AXI_SLAVE_out_bursttype
1808
            assign out_bursttype = (!d1_in_passthru || d1_in_bursttype == REP_WRAP) ? INCR : d1_in_bursttype;
1809
        end
1810
        else begin : others_slave_out_bursttype
1811
           assign out_bursttype =  INCR;
1812
        end
1813
    endgenerate
1814
 
1815
    // At source0_startofpacket, out_addr_read is the in_addr.
1816
    wire [PKT_ADDR_W - 1 : 0] out_addr_read;
1817
    assign out_addr_read = source0_startofpacket_reg ? uncompr_out_addr : out_addr;
1818
 
1819
    // Choose between uncompressed or compressed trans address.
1820
    wire [PKT_ADDR_W - 1 : 0] out_addr_assigned_to_packet;
1821
    assign out_addr_assigned_to_packet = (d1_in_write || d1_in_uncompressed_read) ?  uncompr_out_addr : out_addr_read;
1822
 
1823
    // ---------------------------------------------------
1824
    // Byteenable Generation.
1825
    // Passthrough unless compressed transaction.
1826
    // ---------------------------------------------------
1827
    reg  [PKT_BYTEEN_W - 1 : 0 ]     out_byteen;
1828
    reg  [ADDR_MASK_SEL - 1 : 0 ]    out_addr_masked;
1829
    wire [511:0] initial_byteen = set_byteenable_based_on_size(d1_in_size); // To fix quartus integration error. Unused bits are expected to be synthesized away
1830
 
1831
    // Unaligned address changes.
1832
    // Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address.
1833
    //              Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle)
1834
    always_comb begin
1835
        // Addresses from the converters (out_addr) are always aligned.
1836
        out_addr_masked = out_addr[ADDR_MASK_SEL-1:0];
1837
    end
1838
 
1839
    always_comb begin
1840
    if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS))
1841
        out_byteen     = initial_byteen[NUM_SYMBOLS-1:0] << out_addr_masked;
1842
    else
1843
        out_byteen  = d1_in_byteen;
1844
    end
1845
    // -- End of Byteenable Generation --
1846
 
1847
    always_comb begin : source0_out_assignments
1848
        source0_data                                       = d1_in_data;
1849
        source0_channel                                    = d1_in_channel;
1850
        // Override fields the component is aware of.
1851
        source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]  = out_bursttype;
1852
        source0_data[PKT_BYTE_CNT_H   : PKT_BYTE_CNT_L  ]  = out_byte_cnt;
1853
        source0_data[PKT_ADDR_H       : PKT_ADDR_L      ]  = out_addr_assigned_to_packet;
1854
        source0_data[PKT_BYTEEN_H     : PKT_BYTEEN_L    ]  = out_byteen;
1855
    end
1856
 
1857
    //----------------------------------------------------
1858
    // "min" operation on burstwrap values is a bitwise AND.
1859
    //----------------------------------------------------
1860
    function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min;
1861
        input [PKT_BURSTWRAP_W - 1 : 0] a, b;
1862
        begin
1863
            altera_merlin_burst_adapter_burstwrap_min  = a & b;
1864
        end
1865
    endfunction
1866
 
1867
    //----------------------------------------------------
1868
    // AXSIZE encoding: run-time  size of the transaction.
1869
    // ---------------------------------------------------
1870
    function reg[511:0] set_byteenable_based_on_size;
1871
        input [3:0] axsize;
1872
        begin
1873
            case (axsize)
1874
                4'b0000: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
1875
                4'b0001: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003;
1876
                4'b0010: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F;
1877
                4'b0011: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF;
1878
                4'b0100: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFF;
1879
                4'b0101: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF;
1880
                4'b0110: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF;
1881
                4'b0111: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
1882
                4'b1000: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
1883
                4'b1001: set_byteenable_based_on_size = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
1884
                default: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
1885
            endcase
1886
        end
1887
    endfunction
1888
 
1889
endmodule
1890
 

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