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// Agreement, Intel FPGA IP License Agreement, or other applicable 

// license agreement, including, without limitation, that your use is for the 

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// $Id: //acds/rel/17.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $

// $Revision: #1 $

// $Date: 2017/07/30 $

// $Author: swbranch $

// -----------------------------------------------

// Reset Synchronizer

// -----------------------------------------------

`timescale 1 ns / 1 ns

module altera_reset_synchronizer

#(

    parameter ASYNC_RESET = 1,

    parameter DEPTH       = 2

)

(

    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,

    input   clk,

    output  reset_out

);

    // -----------------------------------------------

    // Synchronizer register chain. We cannot reuse the

    // standard synchronizer in this implementation 

    // because our timing constraints are different.

    //

    // Instead of cutting the timing path to the d-input 

    // on the first flop we need to cut the aclr input.

    // 

    // We omit the "preserve" attribute on the final

    // output register, so that the synthesis tool can

    // duplicate it where needed.

    // -----------------------------------------------

    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;

    reg altera_reset_synchronizer_int_chain_out;

    generate if (ASYNC_RESET) begin

        // -----------------------------------------------

        // Assert asynchronously, deassert synchronously.

        // -----------------------------------------------

        always @(posedge clk or posedge reset_in) begin

            if (reset_in) begin

                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};

                altera_reset_synchronizer_int_chain_out <= 1'b1;

            end

            else begin

                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];

                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;

                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];

            end

        end

        assign reset_out = altera_reset_synchronizer_int_chain_out;

    end else begin

        // -----------------------------------------------

        // Assert synchronously, deassert synchronously.

        // -----------------------------------------------

        always @(posedge clk) begin

            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];

            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;

            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];

        end

        assign reset_out = altera_reset_synchronizer_int_chain_out;

    end

    endgenerate

endmodule