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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_acv_hard_addr_cmd_pads.v] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other 
3
// software and tools, and its AMPP partner logic functions, and any output 
4 40 redbear
// files from any of the foregoing (including device programming or simulation 
5 32 redbear
// files), and any associated documentation or information are expressly subject 
6
// to the terms and conditions of the Intel Program License Subscription 
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable 
8 32 redbear
// license agreement, including, without limitation, that your use is for the 
9
// sole purpose of programming logic devices manufactured by Intel and sold by 
10
// Intel or its authorized distributors.  Please refer to the applicable 
11
// agreement for further details.
12
 
13
 
14
 
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`timescale 1 ps / 1 ps
16
 
17
module hps_sdram_p0_acv_hard_addr_cmd_pads(
18
        /*
19
    config_data_in,
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    config_clock_in,
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    config_io_ena,
22
    config_update,
23
        */
24
    reset_n,
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    reset_n_afi_clk,
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    pll_hr_clk,
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    pll_avl_phy_clk,
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    pll_afi_clk,
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    pll_mem_clk,
30
    pll_write_clk,
31
    phy_ddio_address,
32
    dll_delayctrl_in,
33
    phy_ddio_bank,
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    phy_ddio_cs_n,
35
    phy_ddio_cke,
36
    phy_ddio_odt,
37
    phy_ddio_we_n,
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    phy_ddio_ras_n,
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    phy_ddio_cas_n,
40
    phy_ddio_ck,
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    phy_ddio_reset_n,
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    phy_mem_address,
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    phy_mem_bank,
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    phy_mem_cs_n,
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    phy_mem_cke,
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    phy_mem_odt,
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    phy_mem_we_n,
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    phy_mem_ras_n,
49
    phy_mem_cas_n,
50
    phy_mem_reset_n,
51
    phy_mem_ck,
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    phy_mem_ck_n
53
);
54
 
55
        parameter DEVICE_FAMILY = "";
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        parameter MEM_ADDRESS_WIDTH     = "";
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        parameter MEM_BANK_WIDTH        = "";
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        parameter MEM_CHIP_SELECT_WIDTH = "";
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        parameter MEM_CLK_EN_WIDTH              = "";
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        parameter MEM_CK_WIDTH                  = "";
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        parameter MEM_ODT_WIDTH                 = "";
62
        parameter MEM_CONTROL_WIDTH     = "";
63
 
64
        parameter AFI_ADDRESS_WIDTH         = "";
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        parameter AFI_BANK_WIDTH            = "";
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        parameter AFI_CHIP_SELECT_WIDTH     = "";
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        parameter AFI_CLK_EN_WIDTH                      = "";
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        parameter AFI_ODT_WIDTH                         = "";
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        parameter AFI_CONTROL_WIDTH         = "";
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        parameter DLL_WIDTH = "";
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        parameter ADC_PHASE_SETTING = "";
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        parameter ADC_INVERT_PHASE = "";
73
        parameter IS_HHP_HPS = "";
74
 
75
        /*
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    input config_data_in;
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    input config_clock_in;
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    input config_io_ena;
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    input config_update;
80
        */
81
        input   reset_n;
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        input   reset_n_afi_clk;
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        input   pll_afi_clk;
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        input   pll_hr_clk;
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        input   pll_avl_phy_clk;
86
        input   pll_mem_clk;
87
        input   pll_write_clk;
88
        input   [DLL_WIDTH-1:0] dll_delayctrl_in;
89
 
90
        input   [AFI_ADDRESS_WIDTH-1:0]  phy_ddio_address;
91
 
92
        input   [AFI_BANK_WIDTH-1:0]    phy_ddio_bank;
93
        input   [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
94
        input   [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
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        input   [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
96
        input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
97
        input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
98
        input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
99
        input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
100
        input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
101
 
102
        output  [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
103
        output  [MEM_BANK_WIDTH-1:0]    phy_mem_bank;
104
        output  [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
105
        output  [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
106
        output  [MEM_ODT_WIDTH-1:0] phy_mem_odt;
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        output  [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
108
        output  [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
109
        output  [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
110
        output  phy_mem_reset_n;
111
        output  [MEM_CK_WIDTH-1:0]       phy_mem_ck;
112
        output  [MEM_CK_WIDTH-1:0]       phy_mem_ck_n;
113
 
114
        /* ********* *
115
         * A/C Logic *
116
         * ********* */
117
 
118
        localparam CMD_WIDTH =
119
                MEM_CHIP_SELECT_WIDTH +
120
                MEM_CLK_EN_WIDTH +
121
                MEM_ODT_WIDTH +
122
                MEM_CONTROL_WIDTH +
123
                MEM_CONTROL_WIDTH +
124
                MEM_CONTROL_WIDTH;
125
 
126
        localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
127
 
128
        localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
129
 
130
        wire [AC_CLK_WIDTH-1:0] ac_clk;
131
        generate
132
        genvar i;
133
        for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
134
        begin: address_gen
135
                wire addr_cmd_clk;
136
                hps_sdram_p0_acv_ldc # (
137
                        .DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
138
                        .ADC_PHASE_SETTING(ADC_PHASE_SETTING),
139
                        .ADC_INVERT_PHASE(ADC_INVERT_PHASE),
140
                        .IS_HHP_HPS(IS_HHP_HPS)
141
                ) acv_ac_ldc (
142
                        .pll_hr_clk(pll_avl_phy_clk),
143
                        .pll_dq_clk(pll_write_clk),
144
                        .pll_dqs_clk (pll_mem_clk),
145
                        .dll_phy_delayctrl(dll_delayctrl_in),
146
                        .adc_clk_cps(ac_clk[i])
147
                );
148
        end
149
        endgenerate
150
 
151
        hps_sdram_p0_generic_ddio uaddress_pad(
152
                .datain(phy_ddio_address),
153
                .halfratebypass(1'b1),
154
                .dataout(phy_mem_address),
155
                .clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
156
                .clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
157
        );
158
        defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
159
 
160
        hps_sdram_p0_generic_ddio ubank_pad(
161
                .datain(phy_ddio_bank),
162
                .halfratebypass(1'b1),
163
                .dataout(phy_mem_bank),
164
                .clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
165
                .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
166
        );
167
        defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
168
 
169
        hps_sdram_p0_generic_ddio ucmd_pad(
170
                .datain({
171
                        phy_ddio_we_n,
172
                        phy_ddio_cas_n,
173
                        phy_ddio_ras_n,
174
                        phy_ddio_odt,
175
                        phy_ddio_cke,
176
                        phy_ddio_cs_n
177
                }),
178
                .halfratebypass(1'b1),
179
                .dataout({
180
                        phy_mem_we_n,
181
                        phy_mem_cas_n,
182
                        phy_mem_ras_n,
183
                        phy_mem_odt,
184
                        phy_mem_cke,
185
                        phy_mem_cs_n
186
                }),
187
                .clk_hr({CMD_WIDTH{pll_hr_clk}}),
188
                .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
189
        );
190
        defparam ucmd_pad.WIDTH = CMD_WIDTH;
191
 
192
        hps_sdram_p0_generic_ddio ureset_n_pad(
193
                .datain(phy_ddio_reset_n),
194
                .halfratebypass(1'b1),
195
                .dataout(phy_mem_reset_n),
196
                .clk_hr(pll_hr_clk),
197
                .clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
198
        );
199
        defparam ureset_n_pad.WIDTH = 1;
200
 
201
        /* ************ *
202
         * Config Logic *
203
         * ************ */
204
 
205
        wire [4:0] outputdelaysetting;
206
        wire [4:0] outputenabledelaysetting;
207
        wire outputhalfratebypass;
208
        wire [4:0] inputdelaysetting;
209
 
210
        wire [1:0] rfifo_clock_select;
211
        wire [2:0] rfifo_mode;
212
 
213
        /*
214
        cyclonev_io_config ioconfig (
215
            .datain(config_data_in),
216
            .clk(config_clock_in),
217
            .ena(config_io_ena),
218
            .update(config_update),
219
 
220
            .outputregdelaysetting(outputdelaysetting),
221
            .outputenabledelaysetting(outputenabledelaysetting),
222
            .outputhalfratebypass(outputhalfratebypass),
223
            .readfiforeadclockselect(rfifo_clock_select),
224
            .readfifomode(rfifo_mode),
225
 
226
            .padtoinputregisterdelaysetting(inputdelaysetting),
227
            .dataout()
228
        );
229
        */
230
 
231
        /* *************** *
232
         * Mem Clock Logic *
233
         * *************** */
234
 
235
        wire    [MEM_CK_WIDTH-1:0] mem_ck_source;
236
        wire    [MEM_CK_WIDTH-1:0] mem_ck;
237
 
238
        generate
239
        genvar clock_width;
240
        for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
241
        begin: clock_gen
242
 
243
        if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
244
        begin
245
                hps_sdram_p0_acv_ldc # (
246
                        .DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
247
                        .ADC_PHASE_SETTING(ADC_PHASE_SETTING),
248
                        .ADC_INVERT_PHASE(ADC_INVERT_PHASE),
249
                        .IS_HHP_HPS(IS_HHP_HPS)
250
                ) acv_ck_ldc (
251
                        .pll_hr_clk(pll_avl_phy_clk),
252
                        .pll_dq_clk(pll_write_clk),
253
                        .pll_dqs_clk (pll_mem_clk),
254
                        .dll_phy_delayctrl(dll_delayctrl_in),
255
                        .adc_clk_cps(mem_ck_source[clock_width])
256
                );
257
        end
258
        else
259
        begin
260
                wire [3:0] phy_clk_in;
261
                wire [3:0] phy_clk_out;
262
                assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
263
 
264
                if (IS_HHP_HPS == "true") begin
265
                        assign phy_clk_out = phy_clk_in;
266
                end else begin
267
                        cyclonev_phy_clkbuf phy_clkbuf (
268
                                .inclk (phy_clk_in),
269
                                .outclk (phy_clk_out)
270
                        );
271
                end
272
 
273
                wire [3:0] leveled_dqs_clocks;
274
                cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
275
                        .clkin (phy_clk_out[1]),
276
                        .delayctrlin (dll_delayctrl_in),
277
                        .clkout(leveled_dqs_clocks)
278
                );
279
                defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
280
 
281
                cyclonev_clk_phase_select clk_phase_select_dqs (
282
                        `ifndef SIMGEN
283
                        .clkin (leveled_dqs_clocks[0]),
284
                        `else
285
                        .clkin (leveled_dqs_clocks),
286
                        `endif
287
                        .clkout (mem_ck_source[clock_width])
288
                );
289
                defparam clk_phase_select_dqs.physical_clock_source = "DQS";
290
                defparam clk_phase_select_dqs.use_phasectrlin = "false";
291
                defparam clk_phase_select_dqs.phase_setting = 0;
292
        end
293
 
294
        wire mem_ck_hi;
295
        wire mem_ck_lo;
296
 
297
        if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
298
        begin
299
                assign mem_ck_hi = 1'b0;
300
                assign mem_ck_lo = 1'b1;
301
        end
302
        else
303
        begin
304
                assign mem_ck_hi = phy_ddio_ck[0];
305
                assign mem_ck_lo = phy_ddio_ck[1];
306
        end
307
 
308
        altddio_out umem_ck_pad(
309
                .aclr       (1'b0),
310
                .aset       (1'b0),
311
                .datain_h   (mem_ck_hi),
312
                .datain_l   (mem_ck_lo),
313
                .dataout    (mem_ck[clock_width]),
314
                .oe         (1'b1),
315
                .outclock   (mem_ck_source[clock_width]),
316
                .outclocken (1'b1)
317
        );
318
 
319
        defparam
320
                umem_ck_pad.extend_oe_disable = "UNUSED",
321
                umem_ck_pad.intended_device_family = DEVICE_FAMILY,
322
                umem_ck_pad.invert_output = "OFF",
323
                umem_ck_pad.lpm_hint = "UNUSED",
324
                umem_ck_pad.lpm_type = "altddio_out",
325
                umem_ck_pad.oe_reg = "UNUSED",
326
                umem_ck_pad.power_up_high = "OFF",
327
                umem_ck_pad.width = 1;
328
 
329
                wire mem_ck_temp;
330
 
331
                assign mem_ck_temp = mem_ck[clock_width];
332
 
333
        hps_sdram_p0_clock_pair_generator    uclk_generator(
334
                .datain     (mem_ck_temp),
335
                .dataout    (phy_mem_ck[clock_width]),
336
                .dataout_b  (phy_mem_ck_n[clock_width])
337
        );
338
        end
339
endgenerate
340
 
341
 
342
endmodule

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