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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_acv_hard_io_pads.v] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other 
3
// software and tools, and its AMPP partner logic functions, and any output 
4 40 redbear
// files from any of the foregoing (including device programming or simulation 
5 32 redbear
// files), and any associated documentation or information are expressly subject 
6
// to the terms and conditions of the Intel Program License Subscription 
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable 
8 32 redbear
// license agreement, including, without limitation, that your use is for the 
9
// sole purpose of programming logic devices manufactured by Intel and sold by 
10
// Intel or its authorized distributors.  Please refer to the applicable 
11
// agreement for further details.
12
 
13
 
14
 
15
`timescale 1 ps / 1 ps
16
 
17
module hps_sdram_p0_acv_hard_io_pads(
18
        reset_n_addr_cmd_clk,
19
        reset_n_afi_clk,
20
        oct_ctl_rs_value,
21
        oct_ctl_rt_value,
22
        phy_ddio_address,
23
        phy_ddio_bank,
24
        phy_ddio_cs_n,
25
        phy_ddio_cke,
26
        phy_ddio_odt,
27
        phy_ddio_we_n,
28
        phy_ddio_ras_n,
29
        phy_ddio_cas_n,
30
        phy_ddio_ck,
31
        phy_ddio_reset_n,
32
        phy_mem_address,
33
        phy_mem_bank,
34
        phy_mem_cs_n,
35
        phy_mem_cke,
36
        phy_mem_odt,
37
        phy_mem_we_n,
38
        phy_mem_ras_n,
39
        phy_mem_cas_n,
40
        phy_mem_reset_n,
41
        pll_afi_clk,
42
        pll_afi_phy_clk,
43
        pll_avl_phy_clk,
44
        pll_avl_clk,
45
        avl_clk,
46
        pll_mem_clk,
47
        pll_mem_phy_clk,
48
        pll_write_clk,
49
        pll_dqs_ena_clk,
50
        pll_addr_cmd_clk,
51
        phy_mem_dq,
52
        phy_mem_dm,
53
        phy_mem_ck,
54
        phy_mem_ck_n,
55
        mem_dqs,
56
        mem_dqs_n,
57
        dll_phy_delayctrl,
58
        scc_clk,
59
        scc_data,
60
        scc_dqs_ena,
61
        scc_dqs_io_ena,
62
        scc_dq_ena,
63
        scc_dm_ena,
64
        scc_upd,
65
        seq_read_latency_counter,
66
        seq_read_increment_vfifo_fr,
67
        seq_read_increment_vfifo_hr,
68
        phy_ddio_dmdout,
69
        phy_ddio_dqdout,
70
        phy_ddio_dqs_oe,
71
        phy_ddio_dqsdout,
72
        phy_ddio_dqsb_oe,
73
        phy_ddio_dqslogic_oct,
74
        phy_ddio_dqslogic_fiforeset,
75
        phy_ddio_dqslogic_aclr_pstamble,
76
        phy_ddio_dqslogic_aclr_fifoctrl,
77
        phy_ddio_dqslogic_incwrptr,
78
        phy_ddio_dqslogic_readlatency,
79
        ddio_phy_dqslogic_rdatavalid,
80
        ddio_phy_dqdin,
81
        phy_ddio_dqslogic_incrdataen,
82
        phy_ddio_dqslogic_dqsena,
83
        phy_ddio_dqoe,
84
        capture_strobe_tracking
85
);
86
 
87
 
88
parameter DEVICE_FAMILY = "";
89
parameter FAST_SIM_MODEL            = 0;
90
parameter OCT_SERIES_TERM_CONTROL_WIDTH   = "";
91
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
92
parameter MEM_ADDRESS_WIDTH     = "";
93
parameter MEM_BANK_WIDTH        = "";
94
parameter MEM_CHIP_SELECT_WIDTH = "";
95
parameter MEM_CLK_EN_WIDTH      = "";
96
parameter MEM_CK_WIDTH          = "";
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parameter MEM_ODT_WIDTH         = "";
98
parameter MEM_DQS_WIDTH         = "";
99
parameter MEM_DM_WIDTH          = "";
100
parameter MEM_CONTROL_WIDTH     = "";
101
parameter MEM_DQ_WIDTH          = "";
102
parameter MEM_READ_DQS_WIDTH    = "";
103
parameter MEM_WRITE_DQS_WIDTH   = "";
104
parameter DLL_DELAY_CTRL_WIDTH  = "";
105
parameter ADC_PHASE_SETTING     = "";
106
parameter ADC_INVERT_PHASE      = "";
107
parameter IS_HHP_HPS            = "";
108
 
109
localparam AFI_ADDRESS_WIDTH         = 64;
110
localparam AFI_BANK_WIDTH            = 12;
111
localparam AFI_CHIP_SELECT_WIDTH     = 8;
112
localparam AFI_CLK_EN_WIDTH                     = 8;
113
localparam AFI_ODT_WIDTH                        = 8;
114
localparam AFI_DATA_MASK_WIDTH       = 20;
115
localparam AFI_CONTROL_WIDTH         = 4;
116
 
117
input   reset_n_afi_clk;
118
input   reset_n_addr_cmd_clk;
119
 
120
input   [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
121
input   [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
122
 
123
input   [AFI_ADDRESS_WIDTH-1:0]  phy_ddio_address;
124
input   [AFI_BANK_WIDTH-1:0]    phy_ddio_bank;
125
input   [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
126
input   [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
127
input   [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
128
input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
129
input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
130
input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
131
input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
132
input   [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
133
 
134
output  [MEM_ADDRESS_WIDTH-1:0]  phy_mem_address;
135
output  [MEM_BANK_WIDTH-1:0]     phy_mem_bank;
136
output  [MEM_CHIP_SELECT_WIDTH-1:0]      phy_mem_cs_n;
137
output  [MEM_CLK_EN_WIDTH-1:0]   phy_mem_cke;
138
output  [MEM_ODT_WIDTH-1:0]      phy_mem_odt;
139
output  [MEM_CONTROL_WIDTH-1:0]  phy_mem_we_n;
140
output  [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
141
output  [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
142
output  phy_mem_reset_n;
143
 
144
input   pll_afi_clk;
145
input pll_afi_phy_clk;
146
input pll_avl_phy_clk;
147
input pll_avl_clk;
148
input avl_clk;
149
input   pll_mem_clk;
150
input pll_mem_phy_clk;
151
input   pll_write_clk;
152
input   pll_dqs_ena_clk;
153
input pll_addr_cmd_clk;
154
 
155
 
156
inout   [MEM_DQ_WIDTH-1:0]       phy_mem_dq;
157
output  [MEM_DM_WIDTH-1:0]       phy_mem_dm;
158
output  [MEM_CK_WIDTH-1:0]       phy_mem_ck;
159
output  [MEM_CK_WIDTH-1:0]       phy_mem_ck_n;
160
inout   [MEM_DQS_WIDTH-1:0]      mem_dqs;
161
inout   [MEM_DQS_WIDTH-1:0]      mem_dqs_n;
162
 
163
input   [DLL_DELAY_CTRL_WIDTH-1:0]  dll_phy_delayctrl;
164
 
165
input   scc_clk;
166
input   scc_data;
167
input   [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
168
input   [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
169
input   [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
170
input   [MEM_DM_WIDTH - 1:0] scc_dm_ena;
171
 
172
input [4:0] seq_read_latency_counter;
173
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
174
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
175
input   scc_upd;
176
output  [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
177
 
178
 
179
input [24 : 0] phy_ddio_dmdout;
180
input [179 : 0] phy_ddio_dqdout;
181
input [9 : 0] phy_ddio_dqs_oe;
182
input [19 : 0] phy_ddio_dqsdout;
183
input [9 : 0] phy_ddio_dqsb_oe;
184
input [9 : 0] phy_ddio_dqslogic_oct;
185
input [4 : 0] phy_ddio_dqslogic_fiforeset;
186
input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
187
input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
188
input [9 : 0] phy_ddio_dqslogic_incwrptr;
189
input [24 : 0] phy_ddio_dqslogic_readlatency;
190
output [4 : 0] ddio_phy_dqslogic_rdatavalid;
191
output [179 : 0] ddio_phy_dqdin;
192
input [9 : 0] phy_ddio_dqslogic_incrdataen;
193
input [9 : 0] phy_ddio_dqslogic_dqsena;
194
input [89 : 0] phy_ddio_dqoe;
195
 
196
wire    [MEM_DQ_WIDTH-1:0] mem_phy_dq;
197
wire    [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
198
wire    [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
199
wire    [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
200
wire    [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
201
wire    dqs_busout;
202
 
203
wire    hr_clk = pll_avl_clk;
204
wire    core_clk = pll_afi_clk;
205
wire    reset_n_core_clk = reset_n_afi_clk;
206
 
207
        hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
208
        /*
209
        .config_data_in(config_data_in),
210
        .config_clock_in(config_clock_in),
211
        .config_io_ena(config_io_ena),
212
        .config_update(config_update),
213
                */
214
                .reset_n                                (reset_n_addr_cmd_clk),
215
                .reset_n_afi_clk                (reset_n_afi_clk),
216
                .pll_afi_clk            (pll_afi_phy_clk),
217
                .pll_mem_clk            (pll_mem_phy_clk),
218
                .pll_hr_clk                             (hr_clk),
219
                .pll_avl_phy_clk                (pll_avl_phy_clk),
220
                .pll_write_clk                  (pll_write_clk),
221
                .dll_delayctrl_in               (dll_phy_delayctrl),
222
                .phy_ddio_address               (phy_ddio_address),
223
                .phy_ddio_bank              (phy_ddio_bank),
224
                .phy_ddio_cs_n              (phy_ddio_cs_n),
225
                .phy_ddio_cke                   (phy_ddio_cke),
226
                .phy_ddio_odt                   (phy_ddio_odt),
227
                .phy_ddio_we_n              (phy_ddio_we_n),
228
                .phy_ddio_ras_n             (phy_ddio_ras_n),
229
                .phy_ddio_cas_n             (phy_ddio_cas_n),
230
                .phy_ddio_ck                (phy_ddio_ck),
231
                .phy_ddio_reset_n               (phy_ddio_reset_n),
232
 
233
                .phy_mem_address                (phy_mem_address),
234
                .phy_mem_bank                   (phy_mem_bank),
235
                .phy_mem_cs_n                   (phy_mem_cs_n),
236
                .phy_mem_cke                    (phy_mem_cke),
237
                .phy_mem_odt                    (phy_mem_odt),
238
                .phy_mem_we_n                   (phy_mem_we_n),
239
                .phy_mem_ras_n                  (phy_mem_ras_n),
240
                .phy_mem_cas_n                  (phy_mem_cas_n),
241
                .phy_mem_reset_n                (phy_mem_reset_n),
242
                .phy_mem_ck                             (phy_mem_ck),
243
                .phy_mem_ck_n                   (phy_mem_ck_n)
244
        );
245
        defparam uaddr_cmd_pads.DEVICE_FAMILY                   = DEVICE_FAMILY;
246
        defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH               = MEM_ADDRESS_WIDTH;
247
        defparam uaddr_cmd_pads.MEM_BANK_WIDTH                  = MEM_BANK_WIDTH;
248
        defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH   = MEM_CHIP_SELECT_WIDTH;
249
        defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH                = MEM_CLK_EN_WIDTH;
250
        defparam uaddr_cmd_pads.MEM_CK_WIDTH                    = MEM_CK_WIDTH;
251
        defparam uaddr_cmd_pads.MEM_ODT_WIDTH                   = MEM_ODT_WIDTH;
252
        defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH               = MEM_CONTROL_WIDTH;
253
        defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH       = MEM_ADDRESS_WIDTH * 4;
254
        defparam uaddr_cmd_pads.AFI_BANK_WIDTH          = MEM_BANK_WIDTH * 4;
255
        defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH   = MEM_CHIP_SELECT_WIDTH * 4;
256
        defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH        = MEM_CLK_EN_WIDTH * 4;
257
        defparam uaddr_cmd_pads.AFI_ODT_WIDTH           = MEM_ODT_WIDTH * 4;
258
        defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH       = MEM_CONTROL_WIDTH * 4;
259
        defparam uaddr_cmd_pads.DLL_WIDTH               = DLL_DELAY_CTRL_WIDTH;
260
        defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
261
        defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
262
        defparam uaddr_cmd_pads.IS_HHP_HPS       = IS_HHP_HPS;
263
 
264
        localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
265
        localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
266
 
267
        localparam NATIVE_GROUP_SIZE =
268
                (DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
269
 
270
        localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
271
 
272
        localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
273
 
274
        generate
275
        genvar i;
276
        for (i=0; i<NUM_OF_DQDQS; i=i+1)
277
        begin: dq_ddio
278
                        hps_sdram_p0_altdqdqs ubidir_dq_dqs (
279
                                .write_strobe_clock_in (pll_mem_phy_clk),
280
                                .reset_n_core_clock_in (reset_n_core_clk),
281
                                .core_clock_in (core_clk),
282
                                .fr_clock_in (pll_write_clk),
283
                                .hr_clock_in (pll_avl_phy_clk),
284
                                .parallelterminationcontrol_in(oct_ctl_rt_value),
285
                                .seriesterminationcontrol_in(oct_ctl_rs_value),
286
                                .strobe_ena_hr_clock_in (hr_clk),
287
                                .capture_strobe_tracking (capture_strobe_tracking[i]),
288
                                .read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
289
                                .read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
290
                                .capture_strobe_out(dqs_busout),
291
                                .extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
292
                                .write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
293
                                .write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
294
                                .strobe_io (mem_dqs[i]),
295
                                .strobe_n_io (mem_dqs_n[i]),
296
                                .output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
297
                                .write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
298
                                .oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
299
                                .extra_write_data_out (phy_mem_dm[i]),
300
                                .config_data_in (scc_data),
301
                                .config_dqs_ena (scc_dqs_ena[i]),
302
                                .config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
303
                                .config_dqs_io_ena (scc_dqs_io_ena[i]),
304
                                .config_update (scc_upd),
305
                                .config_clock_in (scc_clk),
306
                                .config_extra_io_ena (scc_dm_ena[i]),
307
                                .lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
308
                                .lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
309
                                .lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
310
                                .lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
311
                                .lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
312
                                .vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
313
                                .vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
314
                                .vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
315
                                .dll_delayctrl_in (dll_phy_delayctrl),
316
                                .rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
317
                                );
318
        end
319
        endgenerate
320
 
321
        generate
322
        genvar j;
323
        for (j = NUM_OF_DQDQS; j < 5; j=j+1)
324
        begin: to_vcc
325
                assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
326
        end
327
        endgenerate
328
 
329
endmodule

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