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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_phy_csr.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
4 40 redbear
// files from any of the foregoing (including device programming or simulation
5 32 redbear
// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable
8 32 redbear
// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
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// ********************************************************************************************************************************
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// File name: phy_csr.v
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// This file instantiates the PHY configuration and status register port
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// ********************************************************************************************************************************
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// PHY CSR ports. The CSR port operates where all reads respond in
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// the next clock cycle and only ever take 1 clock cycle. The writes are cached
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// and are processed in the following clock cycle to when they are initially
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// captured.
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// altera message_off 10036
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module hps_sdram_p0_phy_csr(
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        clk,
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        reset_n,
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        csr_addr,
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        csr_be,
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        csr_write_req,
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        csr_wdata,
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        csr_read_req,
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        csr_rdata,
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        csr_rdata_valid,
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        csr_waitrequest,
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        pll_locked,
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        afi_cal_success,
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        afi_cal_fail,
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        seq_fom_in,
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        seq_fom_out,
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        cal_init_failing_stage,
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        cal_init_failing_substage,
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        cal_init_failing_group
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);
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localparam RESET_REQUEST_DELAY = 4;
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localparam CSR_IP_VERSION_NUMBER = 171;
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parameter CSR_ADDR_WIDTH       = 8;
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parameter CSR_DATA_WIDTH       = 32;
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parameter CSR_BE_WIDTH         = 4;
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parameter MEM_READ_DQS_WIDTH = 64;
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parameter MR1_RTT = 0;
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parameter MR1_ODS = 0;
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parameter MR2_RTT_WR = 0;
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input clk;
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input reset_n;
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input [CSR_ADDR_WIDTH - 1       : 0] csr_addr;
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input [CSR_BE_WIDTH - 1 : 0] csr_be;
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input csr_write_req;
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input [CSR_DATA_WIDTH - 1       : 0] csr_wdata;
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input csr_read_req;
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output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
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output csr_rdata_valid;
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output csr_waitrequest;
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input pll_locked;
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input afi_cal_success;
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input afi_cal_fail;
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input [7:0] seq_fom_in;
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input [7:0] seq_fom_out;
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input [7:0] cal_init_failing_stage;
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input [7:0] cal_init_failing_substage;
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input [7:0] cal_init_failing_group;
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reg int_write_req;
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reg int_read_req;
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reg [CSR_ADDR_WIDTH-1:0] int_addr;
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reg [CSR_BE_WIDTH - 1 : 0] int_be;
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reg [CSR_DATA_WIDTH - 1 : 0] int_rdata;
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reg int_rdata_valid;
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reg int_waitrequest;
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reg [CSR_DATA_WIDTH - 1       : 0] int_wdata;
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reg [31:0] csr_register_0001;
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reg [31:0] csr_register_0002;
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reg [31:0] csr_register_0004;
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reg [31:0] csr_register_0005;
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reg [31:0] csr_register_0006;
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reg [31:0] csr_register_0007;
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reg [31:0] csr_register_0008;
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always @ (posedge clk) begin
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        csr_register_0001 <= 0;
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        csr_register_0001 <= 32'hdeadbeef;
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        csr_register_0002 <= 0;
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        csr_register_0002 <= {CSR_IP_VERSION_NUMBER[15:0],16'h4};
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        csr_register_0004 <= 0;
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        csr_register_0004[24] <= afi_cal_success;
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        csr_register_0004[25] <= afi_cal_fail;
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        csr_register_0004[26] <= pll_locked;
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        csr_register_0005 <= 0;
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        csr_register_0005[7:0] <= seq_fom_in;
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        csr_register_0005[23:16] <= seq_fom_out;
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        csr_register_0006 <= 0;
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        csr_register_0006[7:0] <= cal_init_failing_stage;
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        csr_register_0006[15:8] <= cal_init_failing_substage;
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        csr_register_0006[23:16] <= cal_init_failing_group;
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        csr_register_0007 <= 0;
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        csr_register_0008 <= 0;
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        csr_register_0008[2:0] <= MR1_RTT[2:0] & 3'b111;
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        csr_register_0008[6:5] <= MR1_ODS[1:0] & 2'b11;
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        csr_register_0008[10:9] <= MR2_RTT_WR[1:0] & 2'b11;
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end
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always @ (posedge clk or negedge reset_n) begin
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        if (!reset_n) begin
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                int_write_req <= 0;
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                int_read_req <= 0;
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                int_addr <= 0;
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                int_wdata <= 0;
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                int_be <= 0;
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        end
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        else begin
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                int_addr  <= csr_addr;
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                int_wdata <= csr_wdata;
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                int_be    <= csr_be;
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                if (csr_write_req)
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                        int_write_req <= 1'b1;
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                else
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                        int_write_req <= 1'b0;
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                if (csr_read_req)
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                        int_read_req <= 1'b1;
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                else
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                        int_read_req <= 1'b0;
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        end
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end
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always @ (posedge clk or negedge reset_n) begin
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        if (!reset_n) begin
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                int_rdata       <= 0;
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                int_rdata_valid <= 0;
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                int_waitrequest <= 1;
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        end
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        else begin
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                int_waitrequest <= 1'b0;
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                if (int_read_req)
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                        case (int_addr)
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                                'h1 :
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                                        int_rdata <= csr_register_0001;
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                                'h2 :
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                                        int_rdata <= csr_register_0002;
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                                'h4 :
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                                        int_rdata <= csr_register_0004;
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                                'h5 :
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                                        int_rdata <= csr_register_0005;
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                                'h6 :
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                                        int_rdata <= csr_register_0006;
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                                'h7 :
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                                        int_rdata <= csr_register_0007;
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                                'h8 :
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                                        int_rdata <= csr_register_0008;
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                                default :
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                                        int_rdata <= 0;
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                        endcase
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                if (int_read_req)
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                        int_rdata_valid <= 1'b1;
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                else
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                        int_rdata_valid <= 1'b0;
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        end
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end
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always @ (posedge clk or negedge reset_n) begin
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        if (!reset_n) begin
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211
 
212
        end
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        else begin
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                if (int_write_req) begin
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                end
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        end
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end
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`ifndef SYNTH_FOR_SIM
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hps_sdram_p0_iss_probe pll_probe (
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        .probe_input(pll_locked)
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);
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`endif
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assign csr_waitrequest = int_waitrequest;
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assign csr_rdata = int_rdata;
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assign csr_rdata_valid = int_rdata_valid;
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endmodule

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