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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_pin_assignments.tcl] - Blame information for rev 40

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# (C) 2001-2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and other 
# software and tools, and its AMPP partner logic functions, and any output 
# files from any of the foregoing (including device programming or simulation 
# files), and any associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License Subscription 
# Agreement, Intel FPGA IP License Agreement, or other applicable 
# license agreement, including, without limitation, that your use is for the 
# sole purpose of programming logic devices manufactured by Intel and sold by 
# Intel or its authorized distributors.  Please refer to the applicable 
# agreement for further details.
 
 
#####################################################################
#
# THIS IS AN AUTO-GENERATED FILE!
# -------------------------------
# If you modify this files, all your changes will be lost if you
# regenerate the core!
#
# FILE DESCRIPTION
# ----------------
# This file contains a simple script to automatically apply
# IO standards and other IO assignments for the UniPHY memory
# interface pins that connect to the memory device. The pins
# are automatically detected using the routines defined in
# the hps_sdram_p0_pin_map.tcl script.
# All the memory interface parameters are defined in the
# hps_sdram_p0_parameters.tcl script
 
 
set available_options {
        { c.arg "#_ignore_#" "Option to specify the revision name" }
}
package require cmdline
 
set script_dir [file dirname [info script]]
 
global ::GLOBAL_hps_sdram_p0_corename
global ::GLOBAL_hps_sdram_p0_io_standard
global ::GLOBAL_hps_sdram_p0_io_standard_differential
global ::GLOBAL_hps_sdram_p0_dqs_group_size
global ::GLOBAL_hps_sdram_p0_number_of_dqs_groups
global ::GLOBAL_hps_sdram_p0_uniphy_temp_ver_code
 
#################
#               #
# SETUP SECTION #
#               #
#################
 
global options
set argument_list $quartus(args)
set argv0 "quartus_sta -t [info script]"
set usage "\[<options>\] <project_name>:"
 
if [catch {array set options [cmdline::getoptions argument_list $::available_options]} result] {
        if {[llength $argument_list] > 0 } {
                post_message -type error "Illegal Options"
                post_message -type error  [::cmdline::usage $::available_options $usage]
                qexit -error
        } else {
                post_message -type info  "Usage:"
                post_message -type info  [::cmdline::usage $::available_options $usage]
                qexit -success
        }
}
if {$options(c) != "#_ignore_#"} {
        if [string compare [file extension $options(c)] ""] {
                set options(c) [file rootname $options(c)]
        }
}
 
if {[llength $argument_list] == 1 } {
        set options(project_name) [lindex $argument_list 0]
 
        if [string compare [file extension $options(project_name)] ""] {
                set project_name [file rootname $options(project_name)]
        }
 
        set project_name [file normalize $options(project_name)]
 
} elseif { [llength $argument_list] == 2 } {
        set options(project_name) [lindex $argument_list 0]
        set options(rev)          [lindex $argument_list 1]
 
        if [string compare [file extension $options(project_name)] ""] {
                set project_name [file rootname $options(project_name)]
        }
        if [string compare [file extension $options(c)] ""] {
                set revision_name [file rootname $options(c)]
        }
 
        set project_name [file normalize $options(project_name)]
        set revision_name [file normalize $options(rev)]
 
} elseif { [ is_project_open ] } {
        set project_name $::quartus(project)
        set options(rev) $::quartus(settings)
 
} else {
        post_message -type error "Project name is missing"
        post_message -type info [::cmdline::usage $::available_options $usage]
        post_message -type info "For more details, use \"quartus_sta --help\""
        qexit -error
}
 
 
 # If this script is called from outside quartus_sta/map, it will re-launch itself in quartus_sta
if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } {
        post_message -type info "Restarting in quartus_sta..."
 
        set cmd quartus_sta
        if { [info exists quartus(binpath)] } {
                set cmd [file join $quartus(binpath) $cmd]
        }
 
        if { [ is_project_open ] } {
                set project_name [ get_current_revision ]
        } elseif { ! [ string compare $project_name "" ] } {
                post_message -type error "Missing project_name argument"
 
                return 1
        }
 
        set output [ exec $cmd -t [ info script ] $project_name ]
 
        foreach line [split $output \n] {
                set type info
                set matched_line [ regexp {^\W*(Info|Extra Info|Warning|Critical Warning|Error): (.*)$} $line x type msg ]
                regsub " " $type _ type
 
                if { $matched_line } {
                        post_message -type $type $msg
                } else {
                        puts "$line"
                }
        }
 
        return 0
}
 
if { ! [ is_project_open ] } {
        if { ! [ string compare $project_name "" ] } {
                post_message -type error "Missing project_name argument"
 
                return 1
        }
 
        if {$options(c) == "#_ignore_#"} {
                project_open $project_name
        } else {
                project_open $project_name -revision $options(c)
        }
 
}
 
source "$script_dir/hps_sdram_p0_parameters.tcl"
source "$script_dir/hps_sdram_p0_pin_map.tcl"
 
set family_name [string tolower [regsub -all " +" [get_global_assignment -name FAMILY] ""]]
 
 
##############################
# Clean up stale assignments #
##############################
post_message -type info "Cleaning up stale assignments..."
 
set asgn_types [ list IO_STANDARD INPUT_TERMINATION OUTPUT_TERMINATION CURRENT_STRENGTH_NEW DQ_GROUP TERMINATION_CONTROL_BLOCK ]
foreach asgn_type $asgn_types {
        remove_all_instance_assignments -tag __$::GLOBAL_hps_sdram_p0_corename -name $asgn_type
}
 
if { ! [ timing_netlist_exist ] } {
        create_timing_netlist -post_map
}
 
#######################
#                     #
# ASSIGNMENTS SECTION #
#                     #
#######################
 
# This is the main call to the netlist traversal routines
# that will automatically find all pins and registers required
# to apply pin settings.
hps_sdram_p0_initialize_ddr_db ddr_db
 
# If multiple instances of this core are present in the
# design they will all be constrained through the
# following loop
 
set instances [ array names ddr_db ]
foreach inst $instances {
        if { [ info exists pins ] } {
                # Clean-up stale content
                unset pins
        }
        array set pins $ddr_db($inst)
 
 
        hps_sdram_p0_get_rzq_pins $inst all_rzq_pins
        # Set rzq pin I/O standard
        foreach rzq_pin $all_rzq_pins {
                                if { ! [ string compare $::GLOBAL_hps_sdram_p0_io_standard "SSTL-135" ] } {
                                        set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $rzq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
                                } else {
                                        set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $rzq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
                                }
        }
 
  # 1.35V DDR3L pin assignments
  if { ! [ string compare $::GLOBAL_hps_sdram_p0_io_standard "SSTL-135" ] } {
    foreach dq_pin $pins(all_dq_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
      set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
      set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
 
      set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach ac_pin $pins(ac_wo_reset_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach reset_pin $pins(reset_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach dm_pin $pins(dm_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
  } else {
    # 1.5V DDR3 pin assignments
 
    foreach dq_pin $pins(all_dq_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
      set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential CLASS I" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
      set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential CLASS I" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
 
      set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach ac_pin $pins(ac_wo_reset_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
    foreach reset_pin $pins(reset_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
 
 
    foreach dm_pin $pins(dm_pins) {
      set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename
      set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename
    }
  }
 
 
        set ::GLOBAL_hps_sdram_p0_dqs_group_size_constraint $::GLOBAL_hps_sdram_p0_dqs_group_size
        if { $::GLOBAL_hps_sdram_p0_dqs_group_size == 8 } {
                set ::GLOBAL_hps_sdram_p0_dqs_group_size_constraint 9
        }
 
        set delay_chain_config FLEXIBLE_TIMING
 
        # Disable package skew compensation for data pins in timing analysis
        foreach dq_pin $pins(all_dq_pins) {
                set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename
        }
        foreach dm_pin $pins(dm_pins) {
                set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename
        }
        foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
                set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename
        }
 
        # Disable package skew compensation for address/command pins in timing analysis
        foreach ac_pin $pins(ac_pins) {
                set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename
        }
        foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
                set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename
        }
 
 
        set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __$::GLOBAL_hps_sdram_p0_corename
        set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_n" -tag __$::GLOBAL_hps_sdram_p0_corename
 
        for {set i 0} {$i < $::GLOBAL_hps_sdram_p0_number_of_dqs_groups} {incr i 1} {
                set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uio_pads|dq_ddio[$i].read_capture_clk_buffer" -tag __$::GLOBAL_hps_sdram_p0_corename
                set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_write_side[$i]" -tag __$::GLOBAL_hps_sdram_p0_corename
                set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[$i]" -tag __$::GLOBAL_hps_sdram_p0_corename
        }
 
        set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to $inst -tag __$::GLOBAL_hps_sdram_p0_corename
 
        # Use direct compensation mode to minimize jitter
        set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "${inst}|pll0|fbout" -tag __$::GLOBAL_hps_sdram_p0_corename
}
 
hps_sdram_p0_dump_all_pins ddr_db
 
if { [ llength $quartus(args) ] > 1 } {
        set param [lindex $quartus(args) 1]
 
        if { [ string match -dump_static_pin_map $param ] } {
                set filename "${::GLOBAL_hps_sdram_p0_corename}_static_pin_map.tcl"
 
                hps_sdram_p0_dump_static_pin_map ddr_db $filename
        }
}
 
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 
set_global_assignment -name ECO_REGENERATE_REPORT ON

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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_pin_assignments.tcl] - Blame information for rev 40

Line No.	Rev	Author	Line
1	32	redbear	`# (C) 2001-2017 Intel Corporation. All rights reserved.`
2			`# Your use of Intel Corporation's design tools, logic functions and other`
3			`# software and tools, and its AMPP partner logic functions, and any output`
4	40	redbear	`# files from any of the foregoing (including device programming or simulation`
5	32	redbear	`# files), and any associated documentation or information are expressly subject`
6			`# to the terms and conditions of the Intel Program License Subscription`
7	40	redbear	`# Agreement, Intel FPGA IP License Agreement, or other applicable`
8	32	redbear	`# license agreement, including, without limitation, that your use is for the`
9			`# sole purpose of programming logic devices manufactured by Intel and sold by`
10			`# Intel or its authorized distributors. Please refer to the applicable`
11			`# agreement for further details.`
12
13
14			`#####################################################################`
15			`#`
16			`# THIS IS AN AUTO-GENERATED FILE!`
17			`# -------------------------------`
18			`# If you modify this files, all your changes will be lost if you`
19			`# regenerate the core!`
20			`#`
21			`# FILE DESCRIPTION`
22			`# ----------------`
23			`# This file contains a simple script to automatically apply`
24			`# IO standards and other IO assignments for the UniPHY memory`
25			`# interface pins that connect to the memory device. The pins`
26			`# are automatically detected using the routines defined in`
27			`# the hps_sdram_p0_pin_map.tcl script.`
28			`# All the memory interface parameters are defined in the`
29			`# hps_sdram_p0_parameters.tcl script`
30
31
32			`set available_options {`
33			`{ c.arg "#_ignore_#" "Option to specify the revision name" }`
34			`}`
35			`package require cmdline`
36
37			`set script_dir [file dirname [info script]]`
38
39			`global ::GLOBAL_hps_sdram_p0_corename`
40			`global ::GLOBAL_hps_sdram_p0_io_standard`
41			`global ::GLOBAL_hps_sdram_p0_io_standard_differential`
42			`global ::GLOBAL_hps_sdram_p0_dqs_group_size`
43			`global ::GLOBAL_hps_sdram_p0_number_of_dqs_groups`
44			`global ::GLOBAL_hps_sdram_p0_uniphy_temp_ver_code`
45
46			`#################`
47			`# #`
48			`# SETUP SECTION #`
49			`# #`
50			`#################`
51
52			`global options`
53			`set argument_list $quartus(args)`
54			`set argv0 "quartus_sta -t [info script]"`
55			`set usage "\[<options>\] <project_name>:"`
56
57			`if [catch {array set options [cmdline::getoptions argument_list $::available_options]} result] {`
58			`if {[llength $argument_list] > 0 } {`
59			`post_message -type error "Illegal Options"`
60			`post_message -type error [::cmdline::usage $::available_options $usage]`
61			`qexit -error`
62			`} else {`
63			`post_message -type info "Usage:"`
64			`post_message -type info [::cmdline::usage $::available_options $usage]`
65			`qexit -success`
66			`}`
67			`}`
68			`if {$options(c) != "#_ignore_#"} {`
69			`if [string compare [file extension $options(c)] ""] {`
70			`set options(c) [file rootname $options(c)]`
71			`}`
72			`}`
73
74			`if {[llength $argument_list] == 1 } {`
75			`set options(project_name) [lindex $argument_list 0]`
76
77			`if [string compare [file extension $options(project_name)] ""] {`
78			`set project_name [file rootname $options(project_name)]`
79			`}`
80
81			`set project_name [file normalize $options(project_name)]`
82
83			`} elseif { [llength $argument_list] == 2 } {`
84			`set options(project_name) [lindex $argument_list 0]`
85			`set options(rev) [lindex $argument_list 1]`
86
87			`if [string compare [file extension $options(project_name)] ""] {`
88			`set project_name [file rootname $options(project_name)]`
89			`}`
90			`if [string compare [file extension $options(c)] ""] {`
91			`set revision_name [file rootname $options(c)]`
92			`}`
93
94			`set project_name [file normalize $options(project_name)]`
95			`set revision_name [file normalize $options(rev)]`
96
97			`} elseif { [ is_project_open ] } {`
98			`set project_name $::quartus(project)`
99			`set options(rev) $::quartus(settings)`
100
101			`} else {`
102			`post_message -type error "Project name is missing"`
103			`post_message -type info [::cmdline::usage $::available_options $usage]`
104			`post_message -type info "For more details, use \"quartus_sta --help\""`
105			`qexit -error`
106			`}`
107
108
109			`# If this script is called from outside quartus_sta/map, it will re-launch itself in quartus_sta`
110			`if { ![info exists quartus(nameofexecutable)] \|\| ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } {`
111			`post_message -type info "Restarting in quartus_sta..."`
112
113			`set cmd quartus_sta`
114			`if { [info exists quartus(binpath)] } {`
115			`set cmd [file join $quartus(binpath) $cmd]`
116			`}`
117
118			`if { [ is_project_open ] } {`
119			`set project_name [ get_current_revision ]`
120			`} elseif { ! [ string compare $project_name "" ] } {`
121			`post_message -type error "Missing project_name argument"`
122
123			`return 1`
124			`}`
125
126			`set output [ exec $cmd -t [ info script ] $project_name ]`
127
128			`foreach line [split $output \n] {`
129			`set type info`
130			`set matched_line [ regexp {^\W(Info\|Extra Info\|Warning\|Critical Warning\|Error): (.)$} $line x type msg ]`
131			`regsub " " $type _ type`
132
133			`if { $matched_line } {`
134			`post_message -type $type $msg`
135			`} else {`
136			`puts "$line"`
137			`}`
138			`}`
139
140			`return 0`
141			`}`
142
143			`if { ! [ is_project_open ] } {`
144			`if { ! [ string compare $project_name "" ] } {`
145			`post_message -type error "Missing project_name argument"`
146
147			`return 1`
148			`}`
149
150			`if {$options(c) == "#_ignore_#"} {`
151			`project_open $project_name`
152			`} else {`
153			`project_open $project_name -revision $options(c)`
154			`}`
155
156			`}`
157
158			`source "$script_dir/hps_sdram_p0_parameters.tcl"`
159			`source "$script_dir/hps_sdram_p0_pin_map.tcl"`
160
161			`set family_name [string tolower [regsub -all " +" [get_global_assignment -name FAMILY] ""]]`
162
163
164			`##############################`
165			`# Clean up stale assignments #`
166			`##############################`
167			`post_message -type info "Cleaning up stale assignments..."`
168
169			`set asgn_types [ list IO_STANDARD INPUT_TERMINATION OUTPUT_TERMINATION CURRENT_STRENGTH_NEW DQ_GROUP TERMINATION_CONTROL_BLOCK ]`
170			`foreach asgn_type $asgn_types {`
171			`remove_all_instance_assignments -tag __$::GLOBAL_hps_sdram_p0_corename -name $asgn_type`
172			`}`
173
174			`if { ! [ timing_netlist_exist ] } {`
175			`create_timing_netlist -post_map`
176			`}`
177
178			`#######################`
179			`# #`
180			`# ASSIGNMENTS SECTION #`
181			`# #`
182			`#######################`
183
184			`# This is the main call to the netlist traversal routines`
185			`# that will automatically find all pins and registers required`
186			`# to apply pin settings.`
187			`hps_sdram_p0_initialize_ddr_db ddr_db`
188
189			`# If multiple instances of this core are present in the`
190			`# design they will all be constrained through the`
191			`# following loop`
192
193			`set instances [ array names ddr_db ]`
194			`foreach inst $instances {`
195			`if { [ info exists pins ] } {`
196			`# Clean-up stale content`
197			`unset pins`
198			`}`
199			`array set pins $ddr_db($inst)`
200
201
202			`hps_sdram_p0_get_rzq_pins $inst all_rzq_pins`
203			`# Set rzq pin I/O standard`
204			`foreach rzq_pin $all_rzq_pins {`
205			`if { ! [ string compare $::GLOBAL_hps_sdram_p0_io_standard "SSTL-135" ] } {`
206			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $rzq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
207			`} else {`
208			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $rzq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
209			`}`
210			`}`
211
212			`# 1.35V DDR3L pin assignments`
213			`if { ! [ string compare $::GLOBAL_hps_sdram_p0_io_standard "SSTL-135" ] } {`
214			`foreach dq_pin $pins(all_dq_pins) {`
215			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
216			`set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
217			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
218			`}`
219
220			`foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {`
221			`set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
222			`set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
223			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
224			`}`
225
226			`foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {`
227			`set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
228			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
229
230			`set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
231			`}`
232
233			`foreach ac_pin $pins(ac_wo_reset_pins) {`
234			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
235			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
236			`}`
237
238			`foreach reset_pin $pins(reset_pins) {`
239			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
240			`set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
241			`set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
242			`set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
243			`set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
244			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
245			`}`
246
247			`foreach dm_pin $pins(dm_pins) {`
248			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
249			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
250			`}`
251			`} else {`
252			`# 1.5V DDR3 pin assignments`
253
254			`foreach dq_pin $pins(all_dq_pins) {`
255			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
256			`set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
257			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
258			`}`
259
260			`foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {`
261			`set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential CLASS I" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
262			`set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
263			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
264			`}`
265
266			`foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {`
267			`set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_hps_sdram_p0_io_standard_differential CLASS I" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
268			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
269
270			`set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
271			`}`
272
273			`foreach ac_pin $pins(ac_wo_reset_pins) {`
274			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
275			`set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
276			`}`
277
278			`foreach reset_pin $pins(reset_pins) {`
279			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
280			`set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $reset_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
281			`}`
282
283
284			`foreach dm_pin $pins(dm_pins) {`
285			`set_instance_assignment -name IO_STANDARD "$::GLOBAL_hps_sdram_p0_io_standard CLASS I" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
286			`set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
287			`}`
288			`}`
289
290
291			`set ::GLOBAL_hps_sdram_p0_dqs_group_size_constraint $::GLOBAL_hps_sdram_p0_dqs_group_size`
292			`if { $::GLOBAL_hps_sdram_p0_dqs_group_size == 8 } {`
293			`set ::GLOBAL_hps_sdram_p0_dqs_group_size_constraint 9`
294			`}`
295
296			`set delay_chain_config FLEXIBLE_TIMING`
297
298			`# Disable package skew compensation for data pins in timing analysis`
299			`foreach dq_pin $pins(all_dq_pins) {`
300			`set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dq_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
301			`}`
302			`foreach dm_pin $pins(dm_pins) {`
303			`set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dm_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
304			`}`
305			`foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {`
306			`set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dqs_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
307			`}`
308
309			`# Disable package skew compensation for address/command pins in timing analysis`
310			`foreach ac_pin $pins(ac_pins) {`
311			`set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ac_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
312			`}`
313			`foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {`
314			`set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ck_pin -tag __$::GLOBAL_hps_sdram_p0_corename`
315			`}`
316
317
318			`set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}\|p0\|umemphy\|ureset\|phy_reset_mem_stable_n" -tag __$::GLOBAL_hps_sdram_p0_corename`
319			`set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}\|p0\|umemphy\|ureset\|phy_reset_n" -tag __$::GLOBAL_hps_sdram_p0_corename`
320
321			`for {set i 0} {$i < $::GLOBAL_hps_sdram_p0_number_of_dqs_groups} {incr i 1} {`
322			`set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}\|p0\|umemphy\|uio_pads\|dq_ddio[$i].read_capture_clk_buffer" -tag __$::GLOBAL_hps_sdram_p0_corename`
323			`set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}\|p0\|umemphy\|uread_datapath\|reset_n_fifo_write_side[$i]" -tag __$::GLOBAL_hps_sdram_p0_corename`
324			`set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}\|p0\|umemphy\|uread_datapath\|reset_n_fifo_wraddress[$i]" -tag __$::GLOBAL_hps_sdram_p0_corename`
325			`}`
326
327			`set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to $inst -tag __$::GLOBAL_hps_sdram_p0_corename`
328
329			`# Use direct compensation mode to minimize jitter`
330			`set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "${inst}\|pll0\|fbout" -tag __$::GLOBAL_hps_sdram_p0_corename`
331			`}`
332
333			`hps_sdram_p0_dump_all_pins ddr_db`
334
335			`if { [ llength $quartus(args) ] > 1 } {`
336			`set param [lindex $quartus(args) 1]`
337
338			`if { [ string match -dump_static_pin_map $param ] } {`
339			`set filename "${::GLOBAL_hps_sdram_p0_corename}_static_pin_map.tcl"`
340
341			`hps_sdram_p0_dump_static_pin_map ddr_db $filename`
342			`}`
343			`}`
344
345			`set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON`
346			`set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON`
347			`set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON`
348
349			`set_global_assignment -name ECO_REGENERATE_REPORT ON`