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# (C) 2001-2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files from any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License Subscription
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# Agreement, Intel FPGA IP License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# Intel or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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#############################################################
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# Write Timing Analysis
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#############################################################
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proc hps_sdram_p0_perform_flexible_write_launch_timing_analysis {opcs opcname inst family scale_factors_name interface_type max_package_skew dll_length period pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name} {
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###############################################################################
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# This timing analysis covers the write timing constraints. It includes support
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# for uncalibrated and calibrated write paths. The analysis starts by running a
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# conventional timing analysis for the write paths and then adds support for
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# topologies and IP options which are unique to source-synchronous data transfers.
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# The support for further topologies includes common clock paths in DDR3 as well as
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# correlation between D and K. The support for further IP includes support for
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# write-deskew calibration.
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#
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# During write deskew calibration, the IP will adjust delay chain settings along
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# each signal path to reduce the skew between D pins and to centre align the K
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# clock within the DVW. This operation has the benefit of increasing margin on the
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# setup and hold, as well as removing some of the unknown process variation on each
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# signal path. This timing analysis emulates the IP process by deskewing each pin as
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# well as accounting for the elimination of the unknown process variation. Once the
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# deskew emulation is complete, the analysis further considers the effect of changing
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# the delay chain settings to the operation of the device after calibration: these
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# effects include changes in voltage and temperature which may affect the optimality
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# of the deskew process.
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#
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# The timing analysis creates a write summary report indicating how the timing analysis
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# was performed starting with a typical timing analysis before calibration.
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###############################################################################
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#######################################
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# Need access to global variables
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upvar 1 $summary_name summary
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upvar 1 $timing_parameters_array_name t
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upvar 1 $pin_array_name pins
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upvar 1 $MP_name MP
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upvar 1 $IP_name IP
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upvar 1 $board_name board
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upvar 1 $scale_factors_name scale_factors
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set eol_reduction_factor $IP(eol_reduction_factor_write)
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set num_failing_path $IP(num_report_paths)
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set debug 0
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set result 1
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#################################
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# Find the clock output of the PLL
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set msg_list [ list ]
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set dqs_pll_clock_id [hps_sdram_p0_get_output_clock_id $pins(dqs_pins) "DQS output" msg_list]
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if {$dqs_pll_clock_id == -1} {
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foreach {msg_type msg} $msg_list {
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post_message -type $msg_type "$msg"
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}
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post_message -type warning "Failed to find PLL clock for pins [join $pins(dqs_pins)]"
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set result 0
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} else {
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set dqsclksource [get_node_info -name $dqs_pll_clock_id]
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}
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set msg_list [ list ]
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set dq_pll_clock_id [hps_sdram_p0_get_output_clock_id [ join [ join $pins(q_groups) ]] "DQ output" msg_list]
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if {$dq_pll_clock_id == -1} {
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foreach {msg_type msg} $msg_list {
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post_message -type $msg_type "$msg"
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}
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post_message -type warning "Failed to find PLL clock for pins [ join [ join $pins(q_groups) ]]"
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set result 0
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} else {
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set dqclksource [get_node_info -name $dq_pll_clock_id]
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}
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foreach q_group $pins(q_groups) {
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set q_group $q_group
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lappend q_groups $q_group
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}
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set all_dq_pins [ join [ join $q_groups ] ]
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set dm_pins $pins(dm_pins)
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set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ]
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if {$IP(write_deskew_mode) == "dynamic"} {
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set panel_name_setup "Before Calibration \u0028Negative slacks are OK\u0029||$inst Write \u0028Before Calibration\u0029 (setup)"
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set panel_name_hold "Before Calibration \u0028Negative slacks are OK\u0029||$inst Write \u0028Before Calibration\u0029 (hold)"
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} else {
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set panel_name_setup "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Write (setup)"
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set panel_name_hold "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Write (hold)"
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}
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#####################################################################
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# Default Write Analysis
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set before_calibration_reporting [get_ini_var -name "qsta_enable_before_calibration_ddr_reporting"]
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if {![string equal -nocase $before_calibration_reporting off]} {
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set res_0 [report_timing -detail full_path -to [get_ports $all_dq_dm_pins] \
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-npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet]
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set res_1 [report_timing -detail full_path -to [get_ports $all_dq_dm_pins] \
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-npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet]
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}
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# Perform the default timing analysis to get required and arrival times
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set paths_setup [get_timing_paths -to [get_ports $all_dq_dm_pins] -npaths 400 -setup -nworst 1]
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set paths_hold [get_timing_paths -to [get_ports $all_dq_dm_pins] -npaths 400 -hold -nworst 1]
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#####################################
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# Find Memory Calibration Improvement
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#####################################
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set mp_setup_slack 0
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set mp_hold_slack 0
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if {($IP(write_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
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# Reduce the effect of tDS on the setup slack
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set mp_setup_slack [expr $MP(DS)*$t(DS)]
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# Reduce the effect of tDH on the hold slack
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set mp_hold_slack [expr $MP(DH)*$t(DH)]
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}
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set pll_ccpp 0
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########################################
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# Go over each pin and compute its slack
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# Then include any effects that are unique
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# to source synchronous designs including
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# common clocks, signal correlation, and
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# IP calibration options to compute the
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# total slack of the instance
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set setup_slack 1000000000
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set hold_slack 1000000000
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set default_setup_slack 1000000000
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set default_hold_slack 1000000000
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set max_write_deskew_setup [expr $IP(write_deskew_range_setup)*$IP(quantization_T9)]
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set max_write_deskew_hold [expr $IP(write_deskew_range_hold)*$IP(quantization_T9)]
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if {($result == 1)} {
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# Go over each DQS pin
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set group_number -1
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foreach dqpins $pins(q_groups) {
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set group_number [expr $group_number + 1]
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set dqspin [lindex $pins(dqs_pins) $group_number]
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set dqsnpin [lindex $pins(dqsn_pins) $group_number]
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set dmpins [lindex $pins(dm_pins) $group_number]
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set dqdmpins $dqpins
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if {[llength $dmpins] > 0} {
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lappend dqdmpins $dmpins
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}
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# Find DQS clock node before the periphery
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set msg_list [list]
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set leveling_delay_chain_name [hps_sdram_p0_traverse_to_leveling_delay_chain $dqspin msg_list]
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set dqs_periphery_node ${leveling_delay_chain_name}|clkin
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set cps_name [hps_sdram_p0_traverse_to_clock_phase_select $dqspin msg_list]
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set dqs_clk_phase_select_node ${cps_name}|clkout
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# Find paths from PLL to DQS clock periphery node
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set DQSpaths_max [get_path -rise_from $dqsclksource -rise_to $dqs_clk_phase_select_node -nworst 1]
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set DQSpaths_min [get_path -rise_from $dqsclksource -rise_to $dqs_clk_phase_select_node -nworst 1 -min_path]
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set DQSmin_of_max [hps_sdram_p0_min_in_collection $DQSpaths_max "arrival_time"]
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set DQSmax_of_min [hps_sdram_p0_max_in_collection $DQSpaths_min "arrival_time"]
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set DQSmax_of_max [hps_sdram_p0_max_in_collection $DQSpaths_max "arrival_time"]
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set DQSmin_of_min [hps_sdram_p0_min_in_collection $DQSpaths_min "arrival_time"]
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#############################################
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# Find extra DQS pessimism due to correlation (both spatial correlation and aging correlation)
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#############################################
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# Find paths from DQS clock periphery node to beginning of output buffer
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set output_buffer_node ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*obuf*_0|i
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set DQSperiphery_min [get_path -rise_from $dqs_clk_phase_select_node -rise_to $dqspin -min_path -nworst 1]
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set DQSperiphery_max [get_path -rise_from $dqs_clk_phase_select_node -rise_to $dqspin -nworst 1]
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set DQSperiphery_min_delay [hps_sdram_p0_min_in_collection $DQSperiphery_min "arrival_time"]
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set DQSperiphery_max_delay [hps_sdram_p0_max_in_collection $DQSperiphery_max "arrival_time"]
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set aiot_delay [hps_sdram_p0_round_3dp [expr [hps_sdram_p0_get_rise_aiot_delay $dqspin] * 1e9]]
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set DQSperiphery_min_delay [expr $DQSperiphery_min_delay - $aiot_delay]
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set DQSperiphery_max_delay [expr $DQSperiphery_max_delay - $aiot_delay]
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set DQSpath_pessimism [expr $DQSperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)]
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# Go over each DQ pin in group
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set dq_index 0
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set dm_index 0
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foreach dqpin $dqdmpins {
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if {[lsearch -exact $dmpins $dqpin] >= 0} {
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set isdmpin 1
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regexp {\d+} $dqpin dm_pin_index
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} else {
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set isdmpin 0
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regexp {\d+} $dqpin dq_pin_index
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}
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# Perform the default timing analysis to get required and arrival times
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set pin_setup_slack [hps_sdram_p0_min_in_collection_to_name $paths_setup "slack" $dqpin]
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set pin_hold_slack [hps_sdram_p0_min_in_collection_to_name $paths_hold "slack" $dqpin]
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set default_setup_slack [min $default_setup_slack $pin_setup_slack]
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set default_hold_slack [min $default_hold_slack $pin_hold_slack]
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if { $debug } {
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puts "$group_number $dqspin $dqpin $pin_setup_slack $pin_hold_slack"
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}
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###############################
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# Extra common clock pessimism removal (from PLL) that is not caught by STA
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###############################
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# Find the DQ clock node before the periphery
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set msg_list [list]
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set leveling_delay_chain_name [hps_sdram_p0_traverse_to_leveling_delay_chain $dqpin msg_list]
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set dq_periphery_node ${leveling_delay_chain_name}|clkin
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set cps_name [hps_sdram_p0_traverse_to_clock_phase_select $dqpin msg_list]
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set dq_clk_phase_select_node ${cps_name}|clkout
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# Find paths from PLL to DQ clock periphery node
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set DQpaths_max [get_path -rise_from $dqclksource -rise_to $dq_clk_phase_select_node -nworst 1]
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set DQpaths_min [get_path -rise_from $dqclksource -rise_to $dq_clk_phase_select_node -nworst 1 -min_path]
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set DQmin_of_max [hps_sdram_p0_min_in_collection $DQpaths_max "arrival_time"]
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set DQmax_of_min [hps_sdram_p0_max_in_collection $DQpaths_min "arrival_time"]
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set DQmax_of_max [hps_sdram_p0_max_in_collection $DQpaths_max "arrival_time"]
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set DQmin_of_min [hps_sdram_p0_min_in_collection $DQpaths_min "arrival_time"]
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if {[expr abs(($DQSmax_of_min - $DQSmin_of_max) - ($DQmax_of_min - $DQmin_of_max))] < 0.05} {
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set extra_ccpp_DQS [expr $DQSmin_of_max - $DQSmax_of_min]
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set extra_ccpp_DQ [expr $DQmin_of_max - $DQmax_of_min]
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set extra_ccpp [expr [min $extra_ccpp_DQS $extra_ccpp_DQ] + $pll_ccpp]
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} else {
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set extra_ccpp $pll_ccpp
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}
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# Add the extra ccpp to both setup and hold slacks
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set pin_setup_slack [expr $pin_setup_slack + $extra_ccpp]
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set pin_hold_slack [expr $pin_hold_slack + $extra_ccpp]
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########################################
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# Add the memory calibration improvement
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########################################
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set pin_setup_slack [expr $pin_setup_slack + $mp_setup_slack]
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set pin_hold_slack [expr $pin_hold_slack + $mp_hold_slack]
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############################################
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# Find extra DQ pessimism due to correlation
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# (both spatial correlation and aging correlation)
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############################################
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# Find the DQ clock node before the periphery
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if {$isdmpin == 1} {
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set output_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*extra_output_pad_gen[0].obuf_1|i
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} else {
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set output_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|pad_gen[${dq_index}].data_out|i
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}
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set DQperiphery_min [get_path -rise_from $dq_clk_phase_select_node -rise_to $dqpin -min_path -nworst 1]
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set DQperiphery_max [get_path -rise_from $dq_clk_phase_select_node -rise_to $dqpin -nworst 1]
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set DQperiphery_min_delay [hps_sdram_p0_min_in_collection $DQperiphery_min "arrival_time"]
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|
|
set DQperiphery_max_delay [hps_sdram_p0_max_in_collection $DQperiphery_max "arrival_time"]
|
| 275 |
|
|
set aiot_delay [hps_sdram_p0_round_3dp [expr [hps_sdram_p0_get_rise_aiot_delay $dqpin] * 1e9]]
|
| 276 |
|
|
set DQperiphery_min_delay [expr $DQperiphery_min_delay - $aiot_delay]
|
| 277 |
|
|
set DQperiphery_max_delay [expr $DQperiphery_max_delay - $aiot_delay]
|
| 278 |
|
|
set DQpath_pessimism [expr $DQperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)]
|
| 279 |
|
|
|
| 280 |
|
|
########################################
|
| 281 |
|
|
# Merge current slacks with other slacks
|
| 282 |
|
|
########################################
|
| 283 |
|
|
|
| 284 |
|
|
# If write deskew is available, the setup and hold slacks for this pin will be equal
|
| 285 |
|
|
# and can also remove the extra DQS and DQ pessimism removal
|
| 286 |
|
|
if {$IP(write_deskew_mode) == "dynamic"} {
|
| 287 |
|
|
|
| 288 |
|
|
set extra_pessimism $IP(epw)*$DQperiphery_min_delay
|
| 289 |
|
|
|
| 290 |
|
|
# Consider the maximum range of the deskew when deskewing
|
| 291 |
|
|
set shift_setup_slack [expr ($pin_setup_slack + $pin_hold_slack)/2 - $pin_setup_slack]
|
| 292 |
|
|
if {$shift_setup_slack >= $max_write_deskew_setup} {
|
| 293 |
|
|
if { $debug } {
|
| 294 |
|
|
puts "limited setup"
|
| 295 |
|
|
}
|
| 296 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $max_write_deskew_setup + $extra_pessimism/2]
|
| 297 |
|
|
set pin_hold_slack [expr $pin_hold_slack - $max_write_deskew_setup + $extra_pessimism/2]
|
| 298 |
|
|
|
| 299 |
|
|
# Remember the largest shifts in either direction
|
| 300 |
|
|
if {[info exist max_shift]} {
|
| 301 |
|
|
if {$max_write_deskew_setup > $max_shift} {
|
| 302 |
|
|
set max_shift $max_write_deskew_setup
|
| 303 |
|
|
}
|
| 304 |
|
|
if {$max_write_deskew_setup < $min_shift} {
|
| 305 |
|
|
set min_shift $max_write_deskew_setup
|
| 306 |
|
|
}
|
| 307 |
|
|
} else {
|
| 308 |
|
|
set max_shift $max_write_deskew_setup
|
| 309 |
|
|
set min_shift $max_shift
|
| 310 |
|
|
}
|
| 311 |
|
|
|
| 312 |
|
|
} elseif {$shift_setup_slack <= -$max_write_deskew_hold} {
|
| 313 |
|
|
if { $debug } {
|
| 314 |
|
|
puts "limited hold"
|
| 315 |
|
|
}
|
| 316 |
|
|
set pin_setup_slack [expr $pin_setup_slack - $max_write_deskew_hold + $extra_pessimism/2]
|
| 317 |
|
|
set pin_hold_slack [expr $pin_hold_slack + $max_write_deskew_hold + $extra_pessimism/2]
|
| 318 |
|
|
|
| 319 |
|
|
# Remember the largest shifts in either direction
|
| 320 |
|
|
if {[info exist max_shift]} {
|
| 321 |
|
|
if {[expr 0 -$max_write_deskew_hold] > $max_shift} {
|
| 322 |
|
|
set max_shift [expr 0 - $max_write_deskew_hold]
|
| 323 |
|
|
}
|
| 324 |
|
|
if {[expr 0 -$max_write_deskew_hold] < $min_shift} {
|
| 325 |
|
|
set min_shift [expr 0 - $max_write_deskew_hold]
|
| 326 |
|
|
}
|
| 327 |
|
|
} else {
|
| 328 |
|
|
set max_shift [expr 0 - $max_write_deskew_hold]
|
| 329 |
|
|
set min_shift $max_shift
|
| 330 |
|
|
}
|
| 331 |
|
|
} else {
|
| 332 |
|
|
# In this case we can also consider the DQS/DQpath pessimism since we can guarantee we have enough delay chain settings to align it
|
| 333 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2]
|
| 334 |
|
|
set pin_hold_slack [expr $pin_hold_slack - $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2]
|
| 335 |
|
|
|
| 336 |
|
|
# Remember the largest shifts in either direction
|
| 337 |
|
|
if {[info exist max_shift]} {
|
| 338 |
|
|
if {[expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] > $max_shift} {
|
| 339 |
|
|
set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2]
|
| 340 |
|
|
}
|
| 341 |
|
|
if {[expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] < $min_shift} {
|
| 342 |
|
|
set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2]
|
| 343 |
|
|
}
|
| 344 |
|
|
} else {
|
| 345 |
|
|
set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2]
|
| 346 |
|
|
set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2]
|
| 347 |
|
|
}
|
| 348 |
|
|
}
|
| 349 |
|
|
} else {
|
| 350 |
|
|
# For uncalibrated calls, there is some spatial correlation between DQ and DQS signals, so remove
|
| 351 |
|
|
# some of the pessimism
|
| 352 |
|
|
set total_DQ_DQS_pessimism [expr $DQSpath_pessimism + $DQpath_pessimism]
|
| 353 |
|
|
set dqs_width [llength $dqpins]
|
| 354 |
|
|
if {$dqs_width <= 9} {
|
| 355 |
|
|
set pin_setup_slack [expr $pin_setup_slack + 0.35*$total_DQ_DQS_pessimism]
|
| 356 |
|
|
set pin_hold_slack [expr $pin_hold_slack + 0.35*$total_DQ_DQS_pessimism]
|
| 357 |
|
|
}
|
| 358 |
|
|
}
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
set setup_slack [min $setup_slack $pin_setup_slack]
|
| 362 |
|
|
set hold_slack [min $hold_slack $pin_hold_slack]
|
| 363 |
|
|
|
| 364 |
|
|
if { $debug } {
|
| 365 |
|
|
puts " $extra_ccpp $DQSpath_pessimism $DQpath_pessimism ($pin_setup_slack $pin_hold_slack $setup_slack $hold_slack)"
|
| 366 |
|
|
}
|
| 367 |
|
|
|
| 368 |
|
|
if {$isdmpin == 0} {
|
| 369 |
|
|
set dq_index [expr $dq_index + 1]
|
| 370 |
|
|
} else {
|
| 371 |
|
|
set dm_index [expr $dm_index + 1]
|
| 372 |
|
|
}
|
| 373 |
|
|
}
|
| 374 |
|
|
}
|
| 375 |
|
|
}
|
| 376 |
|
|
|
| 377 |
|
|
###############################
|
| 378 |
|
|
# Consider some post calibration effects on calibration
|
| 379 |
|
|
# and output the write summary report
|
| 380 |
|
|
###############################
|
| 381 |
|
|
set positive_fcolour [list "black" "blue" "blue"]
|
| 382 |
|
|
set negative_fcolour [list "black" "red" "red"]
|
| 383 |
|
|
|
| 384 |
|
|
set wr_summary [list]
|
| 385 |
|
|
|
| 386 |
|
|
if {$IP(write_deskew_mode) == "dynamic"} {
|
| 387 |
|
|
lappend wr_summary [list " Before Calibration Write" [hps_sdram_p0_format_3dp $default_setup_slack] [hps_sdram_p0_format_3dp $default_hold_slack]]
|
| 388 |
|
|
} else {
|
| 389 |
|
|
lappend wr_summary [list " Standard Write" [hps_sdram_p0_format_3dp $default_setup_slack] [hps_sdram_p0_format_3dp $default_hold_slack]]
|
| 390 |
|
|
}
|
| 391 |
|
|
|
| 392 |
|
|
if {($IP(write_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
|
| 393 |
|
|
lappend wr_summary [list " Memory Calibration" [hps_sdram_p0_format_3dp $mp_setup_slack] [hps_sdram_p0_format_3dp $mp_hold_slack]]
|
| 394 |
|
|
}
|
| 395 |
|
|
|
| 396 |
|
|
if {$IP(write_deskew_mode) == "dynamic"} {
|
| 397 |
|
|
if { $debug } {
|
| 398 |
|
|
puts " $setup_slack $hold_slack"
|
| 399 |
|
|
}
|
| 400 |
|
|
|
| 401 |
|
|
#######################################
|
| 402 |
|
|
# Find values for uncertainty table
|
| 403 |
|
|
set t(wru_fpga_deskew_s) [expr $setup_slack - $default_setup_slack - $extra_ccpp - $mp_setup_slack]
|
| 404 |
|
|
set t(wru_fpga_deskew_h) [expr $hold_slack - $default_hold_slack - $extra_ccpp - $mp_setup_slack]
|
| 405 |
|
|
#######################################
|
| 406 |
|
|
|
| 407 |
|
|
# Remove external delays (add slack) that are fixed by the dynamic deskew
|
| 408 |
|
|
if { $IP(discrete_device) == 1 } {
|
| 409 |
|
|
set t(WL_PSE) 0
|
| 410 |
|
|
}
|
| 411 |
|
|
[catch {get_float_table_node_delay -src {DELAYCHAIN_T9} -dst {VTVARIATION} -parameters [list IO $interface_type]} t9_vt_variation_percent]
|
| 412 |
|
|
set extra_shift [expr $board(intra_DQS_group_skew) + [hps_sdram_p0_round_3dp [expr (1.0-$t9_vt_variation_percent)*$t(WL_PSE)]]]
|
| 413 |
|
|
|
| 414 |
|
|
if {$extra_shift > [expr $max_write_deskew_setup - $max_shift]} {
|
| 415 |
|
|
set setup_slack [expr $setup_slack + $max_write_deskew_setup - $max_shift]
|
| 416 |
|
|
} else {
|
| 417 |
|
|
set setup_slack [expr $setup_slack + $extra_shift]
|
| 418 |
|
|
}
|
| 419 |
|
|
if {$extra_shift > [expr $max_write_deskew_hold + $min_shift]} {
|
| 420 |
|
|
set hold_slack [expr $hold_slack + $max_write_deskew_hold + $min_shift]
|
| 421 |
|
|
} else {
|
| 422 |
|
|
set hold_slack [expr $hold_slack + $extra_shift]
|
| 423 |
|
|
}
|
| 424 |
|
|
|
| 425 |
|
|
if { $debug } {
|
| 426 |
|
|
puts " $setup_slack $hold_slack"
|
| 427 |
|
|
}
|
| 428 |
|
|
set deskew_setup [expr $setup_slack - $default_setup_slack -$mp_setup_slack]
|
| 429 |
|
|
set deskew_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack]
|
| 430 |
|
|
lappend wr_summary [list " Deskew Write and/or more clock pessimism removal" [hps_sdram_p0_format_3dp $deskew_setup] [hps_sdram_p0_format_3dp $deskew_hold]]
|
| 431 |
|
|
|
| 432 |
|
|
#######################################
|
| 433 |
|
|
# Find values for uncertainty table
|
| 434 |
|
|
set t(wru_external_deskew_s) [expr $deskew_setup - $t(wru_fpga_deskew_s) + $mp_setup_slack - $extra_ccpp]
|
| 435 |
|
|
set t(wru_external_deskew_h) [expr $deskew_hold - $t(wru_fpga_deskew_h) + $mp_hold_slack - $extra_ccpp]
|
| 436 |
|
|
#######################################
|
| 437 |
|
|
|
| 438 |
|
|
# Consider errors in the dynamic deskew
|
| 439 |
|
|
set t9_quantization $IP(quantization_T9)
|
| 440 |
|
|
set setup_slack [expr $setup_slack - $t9_quantization]
|
| 441 |
|
|
set hold_slack [expr $hold_slack - $t9_quantization]
|
| 442 |
|
|
if { $debug } {
|
| 443 |
|
|
puts " $setup_slack $hold_slack"
|
| 444 |
|
|
}
|
| 445 |
|
|
lappend wr_summary [list " Quantization error" [hps_sdram_p0_format_3dp [expr 0-$t9_quantization]] [hps_sdram_p0_format_3dp [expr 0-$t9_quantization]]]
|
| 446 |
|
|
|
| 447 |
|
|
# Consider variation in the delay chains used during dynamic deksew
|
| 448 |
|
|
#This works out to 0 since the DLL length is 8 for AV/CV
|
| 449 |
|
|
set offset_from_90 0
|
| 450 |
|
|
if {$IP(num_ranks) == 1} {
|
| 451 |
|
|
set t9_variation [expr [min [expr $offset_from_90 + [max [expr $MP(DS)*$t(DS)] [expr $MP(DH)*$t(DH)]] + (2*$board(intra_DQS_group_skew) + $max_package_skew + $t(WL_PSE))] [max $max_write_deskew_setup $max_write_deskew_hold]]*2*$t9_vt_variation_percent]
|
| 452 |
|
|
} else {
|
| 453 |
|
|
set t9_variation [expr [min [expr $offset_from_90 + (2*$board(intra_DQS_group_skew) + $max_package_skew + $t(WL_PSE))] [max $max_write_deskew_setup $max_write_deskew_hold]]*2*$t9_vt_variation_percent]
|
| 454 |
|
|
}
|
| 455 |
|
|
set setup_slack [expr $setup_slack - $t9_variation]
|
| 456 |
|
|
set hold_slack [expr $hold_slack - $t9_variation]
|
| 457 |
|
|
if { $debug } {
|
| 458 |
|
|
puts " $setup_slack $hold_slack"
|
| 459 |
|
|
}
|
| 460 |
|
|
lappend wr_summary [list " Calibration uncertainty" [hps_sdram_p0_format_3dp [expr 0-$t9_variation]] [hps_sdram_p0_format_3dp [expr 0-$t9_variation]]]
|
| 461 |
|
|
|
| 462 |
|
|
#######################################
|
| 463 |
|
|
# Find values for uncertainty table
|
| 464 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 465 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 466 |
|
|
set t(wru_calibration_uncertaintyerror_s) [expr 0 - $t9_variation - $t9_quantization]
|
| 467 |
|
|
set t(wru_calibration_uncertaintyerror_h) [expr 0 - $t9_variation - $t9_quantization]
|
| 468 |
|
|
set t(wru_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(wru_output_max_delay_external) - $extra_ccpp]
|
| 469 |
|
|
set t(wru_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(wru_output_min_delay_external) - $extra_ccpp]
|
| 470 |
|
|
set t(wru_extl_uncertainty_s) [expr $t(wru_output_max_delay_external)]
|
| 471 |
|
|
set t(wru_extl_uncertainty_h) [expr $t(wru_output_min_delay_external)]
|
| 472 |
|
|
}
|
| 473 |
|
|
#######################################
|
| 474 |
|
|
|
| 475 |
|
|
} else {
|
| 476 |
|
|
set pessimism_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack]
|
| 477 |
|
|
set pessimism_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack]
|
| 478 |
|
|
lappend wr_summary [list " Spatial correlation pessimism removal" [hps_sdram_p0_format_3dp $pessimism_setup] [hps_sdram_p0_format_3dp $pessimism_hold]]
|
| 479 |
|
|
|
| 480 |
|
|
#######################################
|
| 481 |
|
|
# Find values for uncertainty table
|
| 482 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 483 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 484 |
|
|
set t(wru_fpga_deskew_s) 0
|
| 485 |
|
|
set t(wru_fpga_deskew_h) 0
|
| 486 |
|
|
set t(wru_external_deskew_s) 0
|
| 487 |
|
|
set t(wru_external_deskew_h) 0
|
| 488 |
|
|
set t(wru_calibration_uncertaintyerror_s) 0
|
| 489 |
|
|
set t(wru_calibration_uncertaintyerror_h) 0
|
| 490 |
|
|
set t(wru_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(wru_output_max_delay_external) - $pessimism_setup]
|
| 491 |
|
|
set t(wru_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(wru_output_min_delay_external) - $pessimism_hold]
|
| 492 |
|
|
set t(wru_extl_uncertainty_s) [expr $t(wru_output_max_delay_external)]
|
| 493 |
|
|
set t(wru_extl_uncertainty_h) [expr $t(wru_output_min_delay_external)]
|
| 494 |
|
|
}
|
| 495 |
|
|
#######################################
|
| 496 |
|
|
}
|
| 497 |
|
|
|
| 498 |
|
|
###############################
|
| 499 |
|
|
# Consider Duty Cycle Calibration if enabled
|
| 500 |
|
|
###############################
|
| 501 |
|
|
|
| 502 |
|
|
if {($IP(write_dcc) == "dynamic")} {
|
| 503 |
|
|
#First remove the Systematic DCD
|
| 504 |
|
|
set setup_slack [expr $setup_slack + $t(WL_DCD)]
|
| 505 |
|
|
set hold_slack [expr $hold_slack + $t(WL_DCD)]
|
| 506 |
|
|
if { $debug } {
|
| 507 |
|
|
puts " $setup_slack $hold_slack"
|
| 508 |
|
|
}
|
| 509 |
|
|
lappend wr_summary [list " Duty cycle correction" $t(WL_DCD) $t(WL_DCD)]
|
| 510 |
|
|
|
| 511 |
|
|
#Add errors in the DCC
|
| 512 |
|
|
set DCC_quantization $IP(quantization_DCC)
|
| 513 |
|
|
set setup_slack [expr $setup_slack - $DCC_quantization]
|
| 514 |
|
|
set hold_slack [expr $hold_slack - $DCC_quantization]
|
| 515 |
|
|
if { $debug } {
|
| 516 |
|
|
puts " $setup_slack $hold_slack"
|
| 517 |
|
|
}
|
| 518 |
|
|
lappend wr_summary [list " Duty cycle correction quantization error" [hps_sdram_p0_format_3dp [expr 0-$DCC_quantization]] [hps_sdram_p0_format_3dp [expr 0-$DCC_quantization]]]
|
| 519 |
|
|
|
| 520 |
|
|
# Consider variation in the DCC
|
| 521 |
|
|
[catch {get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]} dcc_vt_variation_percent]
|
| 522 |
|
|
set dcc_variation [expr $t(WL_DCD)*2*$dcc_vt_variation_percent]
|
| 523 |
|
|
set setup_slack [expr $setup_slack - $dcc_variation]
|
| 524 |
|
|
set hold_slack [expr $hold_slack - $dcc_variation]
|
| 525 |
|
|
if { $debug } {
|
| 526 |
|
|
puts " $setup_slack $hold_slack"
|
| 527 |
|
|
}
|
| 528 |
|
|
lappend wr_summary [list " Duty cycle correction calibration uncertainity" [hps_sdram_p0_format_3dp [expr 0-$dcc_variation]] [hps_sdram_p0_format_3dp [expr 0-$dcc_variation]]]
|
| 529 |
|
|
}
|
| 530 |
|
|
|
| 531 |
|
|
#######################################
|
| 532 |
|
|
#######################################
|
| 533 |
|
|
# Create the write analysis panel
|
| 534 |
|
|
set panel_name "$inst Write"
|
| 535 |
|
|
set root_folder_name [get_current_timequest_report_folder]
|
| 536 |
|
|
|
| 537 |
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
| 538 |
|
|
set panel_name "${root_folder_name}||$panel_name"
|
| 539 |
|
|
}
|
| 540 |
|
|
# Create the root if it doesn't yet exist
|
| 541 |
|
|
if {[get_report_panel_id $root_folder_name] == -1} {
|
| 542 |
|
|
set panel_id [create_report_panel -folder $root_folder_name]
|
| 543 |
|
|
}
|
| 544 |
|
|
|
| 545 |
|
|
# Delete any pre-existing summary panel
|
| 546 |
|
|
set panel_id [get_report_panel_id $panel_name]
|
| 547 |
|
|
if {$panel_id != -1} {
|
| 548 |
|
|
delete_report_panel -id $panel_id
|
| 549 |
|
|
}
|
| 550 |
|
|
|
| 551 |
|
|
if {($setup_slack < 0) || ($hold_slack <0)} {
|
| 552 |
|
|
set panel_id [create_report_panel -table $panel_name -color red]
|
| 553 |
|
|
} else {
|
| 554 |
|
|
set panel_id [create_report_panel -table $panel_name]
|
| 555 |
|
|
}
|
| 556 |
|
|
add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"]
|
| 557 |
|
|
|
| 558 |
|
|
if {($IP(write_deskew_mode) == "dynamic")} {
|
| 559 |
|
|
set fcolour [hps_sdram_p0_get_colours $setup_slack $hold_slack]
|
| 560 |
|
|
add_row_to_table -id $panel_id [list "After Calibration Write" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]] -fcolor $fcolour
|
| 561 |
|
|
lappend summary [list $opcname 0 "Write ($opcname)" $setup_slack $hold_slack]
|
| 562 |
|
|
} else {
|
| 563 |
|
|
set fcolour [hps_sdram_p0_get_colours $setup_slack $hold_slack]
|
| 564 |
|
|
add_row_to_table -id $panel_id [list "Write" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]] -fcolor $fcolour
|
| 565 |
|
|
lappend summary [list $opcname 0 "Write ($opcname)" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]]
|
| 566 |
|
|
}
|
| 567 |
|
|
|
| 568 |
|
|
foreach summary_line $wr_summary {
|
| 569 |
|
|
add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour
|
| 570 |
|
|
}
|
| 571 |
|
|
|
| 572 |
|
|
#######################################
|
| 573 |
|
|
# Create the Write uncertainty panel
|
| 574 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 575 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 576 |
|
|
set panel_name "$inst Write Uncertainty"
|
| 577 |
|
|
set root_folder_name [get_current_timequest_report_folder]
|
| 578 |
|
|
|
| 579 |
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
| 580 |
|
|
set panel_name "${root_folder_name}||$panel_name"
|
| 581 |
|
|
}
|
| 582 |
|
|
|
| 583 |
|
|
# Delete any pre-existing summary panel
|
| 584 |
|
|
set panel_id [get_report_panel_id $panel_name]
|
| 585 |
|
|
if {$panel_id != -1} {
|
| 586 |
|
|
delete_report_panel -id $panel_id
|
| 587 |
|
|
}
|
| 588 |
|
|
|
| 589 |
|
|
set panel_id [create_report_panel -table $panel_name]
|
| 590 |
|
|
add_row_to_table -id $panel_id [list "Value" "Setup Side" "Hold Side"]
|
| 591 |
|
|
add_row_to_table -id $panel_id [list "Uncertainty" "" ""]
|
| 592 |
|
|
add_row_to_table -id $panel_id [list " FPGA uncertainty" [hps_sdram_p0_format_3dp $t(wru_fpga_uncertainty_s)] [hps_sdram_p0_format_3dp $t(wru_fpga_uncertainty_h)]]
|
| 593 |
|
|
add_row_to_table -id $panel_id [list " External uncertainty" [hps_sdram_p0_format_3dp $t(wru_extl_uncertainty_s)] [hps_sdram_p0_format_3dp $t(wru_extl_uncertainty_h)]]
|
| 594 |
|
|
add_row_to_table -id $panel_id [list "Deskew" "" ""]
|
| 595 |
|
|
add_row_to_table -id $panel_id [list " FPGA deskew" [hps_sdram_p0_format_3dp $t(wru_fpga_deskew_s)] [hps_sdram_p0_format_3dp $t(wru_fpga_deskew_h)]]
|
| 596 |
|
|
add_row_to_table -id $panel_id [list " External deskew" [hps_sdram_p0_format_3dp $t(wru_external_deskew_s)] [hps_sdram_p0_format_3dp $t(wru_external_deskew_h)]]
|
| 597 |
|
|
add_row_to_table -id $panel_id [list " Calibration uncertainty/error" [hps_sdram_p0_format_3dp $t(wru_calibration_uncertaintyerror_s)] [hps_sdram_p0_format_3dp $t(wru_calibration_uncertaintyerror_h)]]
|
| 598 |
|
|
}
|
| 599 |
|
|
}
|
| 600 |
|
|
|
| 601 |
|
|
|
| 602 |
|
|
#############################################################
|
| 603 |
|
|
# Read Timing Analysis
|
| 604 |
|
|
#############################################################
|
| 605 |
|
|
proc hps_sdram_p0_perform_flexible_read_capture_timing_analysis {opcs opcname inst family scale_factors_name io_std interface_type max_package_skew dqs_phase period all_dq_pins pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name fpga_name} {
|
| 606 |
|
|
|
| 607 |
|
|
################################################################################
|
| 608 |
|
|
# This timing analysis covers the read timing constraints. It includes support
|
| 609 |
|
|
# for uncalibrated and calibrated read paths. The analysis starts by running a
|
| 610 |
|
|
# conventional timing analysis for the read paths and then adds support for
|
| 611 |
|
|
# topologies and IP options which are unique to source-synchronous data transfers.
|
| 612 |
|
|
# The support for further topologies includes correlation between DQ and DQS signals
|
| 613 |
|
|
# The support for further IP includes support for read-deskew calibration.
|
| 614 |
|
|
#
|
| 615 |
|
|
# During read deskew calibration, the IP will adjust delay chain settings along
|
| 616 |
|
|
# each signal path to reduce the skew between DQ pins and to centre align the DQ
|
| 617 |
|
|
# strobe within the DVW. This operation has the benefit of increasing margin on the
|
| 618 |
|
|
# setup and hold, as well as removing some of the unknown process variation on each
|
| 619 |
|
|
# signal path. This timing analysis emulates the IP process by deskewing each pin as
|
| 620 |
|
|
# well as accounting for the elimination of the unknown process variation. Once the
|
| 621 |
|
|
# deskew emulation is complete, the analysis further considers the effect of changing
|
| 622 |
|
|
# the delay chain settings to the operation of the device after calibration: these
|
| 623 |
|
|
# effects include changes in voltage and temperature which may affect the optimality
|
| 624 |
|
|
# of the deskew process.
|
| 625 |
|
|
#
|
| 626 |
|
|
# The timing analysis creates a read summary report indicating how the timing analysis
|
| 627 |
|
|
# was performed starting with a typical timing analysis before calibration.
|
| 628 |
|
|
###############################################################################
|
| 629 |
|
|
|
| 630 |
|
|
#######################################
|
| 631 |
|
|
# Need access to global variables
|
| 632 |
|
|
upvar 1 $summary_name summary
|
| 633 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 634 |
|
|
upvar 1 $pin_array_name pins
|
| 635 |
|
|
upvar 1 $MP_name MP
|
| 636 |
|
|
upvar 1 $IP_name IP
|
| 637 |
|
|
upvar 1 $board_name board
|
| 638 |
|
|
upvar 1 $fpga_name fpga
|
| 639 |
|
|
upvar 1 $scale_factors_name scale_factors
|
| 640 |
|
|
|
| 641 |
|
|
set eol_reduction_factor $IP(eol_reduction_factor_read)
|
| 642 |
|
|
set num_failing_path $IP(num_report_paths)
|
| 643 |
|
|
|
| 644 |
|
|
# Debug switch. Change to 1 to get more run-time debug information
|
| 645 |
|
|
set debug 0
|
| 646 |
|
|
set result 1
|
| 647 |
|
|
|
| 648 |
|
|
foreach dqsclock $pins(dqs_pins) {
|
| 649 |
|
|
lappend dqs_pins_in ${dqsclock}_IN
|
| 650 |
|
|
}
|
| 651 |
|
|
|
| 652 |
|
|
if {$IP(read_deskew_mode) == "dynamic"} {
|
| 653 |
|
|
set panel_name_setup "Before Calibration \u0028Negative slacks are OK\u0029||$inst Read Capture \u0028Before Calibration\u0029 (setup)"
|
| 654 |
|
|
set panel_name_hold "Before Calibration \u0028Negative slacks are OK\u0029||$inst Read Capture \u0028Before Calibration\u0029 (hold)"
|
| 655 |
|
|
} else {
|
| 656 |
|
|
set panel_name_setup "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Read Capture (setup)"
|
| 657 |
|
|
set panel_name_hold "Before Spatial Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Read Capture (hold)"
|
| 658 |
|
|
}
|
| 659 |
|
|
|
| 660 |
|
|
#####################################################################
|
| 661 |
|
|
# Default Read Analysis
|
| 662 |
|
|
set before_calibration_reporting [get_ini_var -name "qsta_enable_before_calibration_ddr_reporting"]
|
| 663 |
|
|
if {![string equal -nocase $before_calibration_reporting off]} {
|
| 664 |
|
|
set res_0 [report_timing -detail full_path -from [get_ports $all_dq_pins] \
|
| 665 |
|
|
-to_clock [get_clocks $dqs_pins_in] -npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet]
|
| 666 |
|
|
set res_1 [report_timing -detail full_path -from [get_ports $all_dq_pins] \
|
| 667 |
|
|
-to_clock [get_clocks $dqs_pins_in] -npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet]
|
| 668 |
|
|
}
|
| 669 |
|
|
|
| 670 |
|
|
set paths_setup [get_timing_paths -from [get_ports $all_dq_pins] -to_clock [get_clocks $dqs_pins_in] -npaths 400 -setup -nworst 1]
|
| 671 |
|
|
set paths_hold [get_timing_paths -from [get_ports $all_dq_pins] -to_clock [get_clocks $dqs_pins_in] -npaths 400 -hold -nworst 1]
|
| 672 |
|
|
|
| 673 |
|
|
#####################################
|
| 674 |
|
|
# Find Memory Calibration Improvement
|
| 675 |
|
|
#####################################
|
| 676 |
|
|
|
| 677 |
|
|
set mp_setup_slack 0
|
| 678 |
|
|
set mp_hold_slack 0
|
| 679 |
|
|
if {($IP(read_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
|
| 680 |
|
|
# Reduce the effect of tDQSQ on the setup slack
|
| 681 |
|
|
set mp_setup_slack [expr $MP(DQSQ)*$t(DQSQ)]
|
| 682 |
|
|
|
| 683 |
|
|
# Reduce the effect of tQH_time on the hold slack
|
| 684 |
|
|
set mp_hold_slack [expr $MP(QH_time)*(0.5*$period-$t(QH_time))]
|
| 685 |
|
|
}
|
| 686 |
|
|
|
| 687 |
|
|
########################################
|
| 688 |
|
|
# Go over each pin and compute its slack
|
| 689 |
|
|
# Then include any effects that are unique
|
| 690 |
|
|
# to source synchronous designs including
|
| 691 |
|
|
# common clocks, signal correlation, and
|
| 692 |
|
|
# IP calibration options to compute the
|
| 693 |
|
|
# total slack of the instance
|
| 694 |
|
|
|
| 695 |
|
|
set prefix [ string map "| |*:" $inst ]
|
| 696 |
|
|
set prefix "*:$prefix"
|
| 697 |
|
|
# Get some of the FPGA jitter and DCD specs
|
| 698 |
|
|
# When not specified all jitter values are peak-to-peak jitters in ns
|
| 699 |
|
|
set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -period $period]/1000.0]
|
| 700 |
|
|
set tJITdty [expr [get_micro_node_delay -micro MEM_CK_DC_JITTER -parameters [list IO PHY_SHORT]]/1000.0]
|
| 701 |
|
|
# DCD value that is looked up is in %, and thus needs to be divided by 100
|
| 702 |
|
|
set tDCD [expr [get_micro_node_delay -micro MEM_CK_DCD -parameters [list IO PHY_SHORT]]/100.0]
|
| 703 |
|
|
|
| 704 |
|
|
# This is the peak-to-peak jitter on the whole DQ-DQS read capture path
|
| 705 |
|
|
set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0]
|
| 706 |
|
|
# This is the proportion of the DQ-DQS read capture path jitter that applies to setup (looed up value is in %, and thus needs to be divided by 100)
|
| 707 |
|
|
set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0]
|
| 708 |
|
|
# Phase Error on DQS paths. This parameter is queried at run time
|
| 709 |
|
|
set fpga(tDQS_PSERR) [ expr [ get_integer_node_delay -integer $::GLOBAL_hps_sdram_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PSERR -in_fitter ] / 1000.0 ]
|
| 710 |
|
|
|
| 711 |
|
|
set setup_slack 1000000000
|
| 712 |
|
|
set hold_slack 1000000000
|
| 713 |
|
|
set default_setup_slack 1000000000
|
| 714 |
|
|
set default_hold_slack 1000000000
|
| 715 |
|
|
|
| 716 |
|
|
# Find quiet jitter values during calibration
|
| 717 |
|
|
if {$family == "arria v"} {
|
| 718 |
|
|
set quiet_clk_jitter_proportion 0.25
|
| 719 |
|
|
} else {
|
| 720 |
|
|
set quiet_clk_jitter_proportion 0.5
|
| 721 |
|
|
}
|
| 722 |
|
|
set quiet_setup_jitter [expr 0.8*$DQSpathjitter*$DQSpathjitter_setup_prop]
|
| 723 |
|
|
set quiet_hold_jitter [expr 0.8*$DQSpathjitter*(1-$DQSpathjitter_setup_prop) + $quiet_clk_jitter_proportion*$tJITper/2]
|
| 724 |
|
|
set max_read_deskew_setup [expr $IP(read_deskew_range_setup)*$IP(quantization_T1)]
|
| 725 |
|
|
set max_read_deskew_hold [expr $IP(read_deskew_range_hold)*$IP(quantization_T1)]
|
| 726 |
|
|
|
| 727 |
|
|
if {($result == 1)} {
|
| 728 |
|
|
|
| 729 |
|
|
# Go over each DQS pin
|
| 730 |
|
|
set group_number -1
|
| 731 |
|
|
foreach qpins $pins(q_groups) {
|
| 732 |
|
|
|
| 733 |
|
|
set group_number [expr $group_number + 1]
|
| 734 |
|
|
|
| 735 |
|
|
set dqspin [lindex $pins(dqs_pins) $group_number]
|
| 736 |
|
|
set dqsnpin [lindex $pins(dqsn_pins) $group_number]
|
| 737 |
|
|
|
| 738 |
|
|
#############################################
|
| 739 |
|
|
# Find extra DQS pessimism due to correlation
|
| 740 |
|
|
# (both spatial correlation and aging correlation)
|
| 741 |
|
|
#############################################
|
| 742 |
|
|
|
| 743 |
|
|
# Find paths from output of the input buffer to the end of the DQS periphery
|
| 744 |
|
|
set input_buffer_node "${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*strobe_in|o"
|
| 745 |
|
|
set DQScapture_node [list "${prefix}*dq_ddio[${group_number}].ubidir_dq_dqs|*altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO" ]
|
| 746 |
|
|
|
| 747 |
|
|
set DQSperiphery_min [get_path -rise_from $input_buffer_node -rise_to $DQScapture_node -min_path -nworst 1]
|
| 748 |
|
|
set DQSperiphery_max [get_path -rise_from $input_buffer_node -rise_to $DQScapture_node -nworst 1]
|
| 749 |
|
|
set DQSperiphery_min_delay [hps_sdram_p0_min_in_collection $DQSperiphery_min "arrival_time"]
|
| 750 |
|
|
set DQSperiphery_max_delay [hps_sdram_p0_max_in_collection $DQSperiphery_max "arrival_time"]
|
| 751 |
|
|
set DQSpath_pessimism [expr ($DQSperiphery_min_delay - 90.0/360*$t(CK))*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)]
|
| 752 |
|
|
|
| 753 |
|
|
# Go over each DQ pin in group
|
| 754 |
|
|
set q_index 0
|
| 755 |
|
|
foreach qpin $qpins {
|
| 756 |
|
|
regexp {\d+} $qpin q_pin_index
|
| 757 |
|
|
|
| 758 |
|
|
# Perform the default timing analysis to get required and arrival times
|
| 759 |
|
|
set pin_setup_slack [hps_sdram_p0_min_in_collection_from_name $paths_setup "slack" $qpin]
|
| 760 |
|
|
set pin_hold_slack [hps_sdram_p0_min_in_collection_from_name $paths_hold "slack" $qpin]
|
| 761 |
|
|
|
| 762 |
|
|
set default_setup_slack [min $default_setup_slack $pin_setup_slack]
|
| 763 |
|
|
set default_hold_slack [min $default_hold_slack $pin_hold_slack]
|
| 764 |
|
|
|
| 765 |
|
|
if { $debug } {
|
| 766 |
|
|
puts "READ: $group_number $dqspin $qpin $pin_setup_slack $pin_hold_slack (MP: $mp_setup_slack $mp_hold_slack)"
|
| 767 |
|
|
}
|
| 768 |
|
|
|
| 769 |
|
|
###############################
|
| 770 |
|
|
# Add the memory calibration improvement
|
| 771 |
|
|
###############################
|
| 772 |
|
|
|
| 773 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $mp_setup_slack]
|
| 774 |
|
|
set pin_hold_slack [expr $pin_hold_slack + $mp_hold_slack]
|
| 775 |
|
|
|
| 776 |
|
|
############################################
|
| 777 |
|
|
# Find extra DQ pessimism due to correlation
|
| 778 |
|
|
############################################
|
| 779 |
|
|
|
| 780 |
|
|
# Find paths from output of the input buffer to the end of the DQ periphery
|
| 781 |
|
|
set input_buffer_node_dq ${inst}|p0|umemphy|uio_pads|dq_ddio[${group_number}].ubidir_dq_dqs|altdq_dqs2_inst|*pad_gen[${q_index}].data_in|o
|
| 782 |
|
|
set DQcapture_node [list "${prefix}*dq_ddio[${group_number}].ubidir_dq_dqs|*altdq_dqs2_inst|*input_path_gen[${q_index}].capture_reg~DFFLO" ]
|
| 783 |
|
|
|
| 784 |
|
|
set DQperiphery_min [get_path -rise_from $input_buffer_node_dq -rise_to $DQScapture_node -min_path -nworst 1]
|
| 785 |
|
|
set DQperiphery_max [get_path -rise_from $input_buffer_node_dq -rise_to $DQScapture_node -nworst 1]
|
| 786 |
|
|
set DQperiphery_min_delay [hps_sdram_p0_min_in_collection $DQperiphery_min "arrival_time"]
|
| 787 |
|
|
set DQperiphery_max_delay [hps_sdram_p0_max_in_collection $DQperiphery_max "arrival_time"]
|
| 788 |
|
|
set DQpath_pessimism [expr $DQperiphery_min_delay*($scale_factors(emif) + $scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor)]
|
| 789 |
|
|
|
| 790 |
|
|
########################################
|
| 791 |
|
|
# Merge current slacks with other slacks
|
| 792 |
|
|
########################################
|
| 793 |
|
|
|
| 794 |
|
|
# If read deskew is available, the setup and hold slacks for this pin will be equal
|
| 795 |
|
|
# and can also remove the extra DQS pessimism removal
|
| 796 |
|
|
if {$IP(read_deskew_mode) == "dynamic"} {
|
| 797 |
|
|
|
| 798 |
|
|
set extra_pessimism $IP(epr)*$DQperiphery_min_delay
|
| 799 |
|
|
|
| 800 |
|
|
# Consider the maximum range of the deskew when deskewing
|
| 801 |
|
|
set shift_setup_slack [expr (($pin_setup_slack + $quiet_setup_jitter) + ($pin_hold_slack + $quiet_hold_jitter))/2 - $pin_setup_slack - $quiet_setup_jitter]
|
| 802 |
|
|
if {$shift_setup_slack >= $max_read_deskew_setup} {
|
| 803 |
|
|
if { $debug } {
|
| 804 |
|
|
puts "limited setup"
|
| 805 |
|
|
}
|
| 806 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $max_read_deskew_setup + $extra_pessimism/2]
|
| 807 |
|
|
set pin_hold_slack [expr $pin_hold_slack - $max_read_deskew_setup + $extra_pessimism/2]
|
| 808 |
|
|
|
| 809 |
|
|
# Remember the largest shifts in either direction
|
| 810 |
|
|
if {[info exist max_shift]} {
|
| 811 |
|
|
if {$max_read_deskew_setup > $max_shift} {
|
| 812 |
|
|
set max_shift $max_read_deskew_setup
|
| 813 |
|
|
}
|
| 814 |
|
|
if {$max_read_deskew_setup < $min_shift} {
|
| 815 |
|
|
set min_shift $max_read_deskew_setup
|
| 816 |
|
|
}
|
| 817 |
|
|
} else {
|
| 818 |
|
|
set max_shift $max_read_deskew_setup
|
| 819 |
|
|
set min_shift $max_shift
|
| 820 |
|
|
}
|
| 821 |
|
|
|
| 822 |
|
|
} elseif {$shift_setup_slack <= -$max_read_deskew_hold} {
|
| 823 |
|
|
if { $debug } {
|
| 824 |
|
|
puts "limited hold"
|
| 825 |
|
|
}
|
| 826 |
|
|
set pin_setup_slack [expr $pin_setup_slack - $max_read_deskew_hold + $extra_pessimism/2]
|
| 827 |
|
|
set pin_hold_slack [expr $pin_hold_slack + $max_read_deskew_hold + $extra_pessimism/2]
|
| 828 |
|
|
|
| 829 |
|
|
# Remember the largest shifts in either direction
|
| 830 |
|
|
if {[info exist max_shift]} {
|
| 831 |
|
|
if {[expr 0 -$max_read_deskew_hold] > $max_shift} {
|
| 832 |
|
|
set max_shift [expr 0 - $max_read_deskew_hold]
|
| 833 |
|
|
}
|
| 834 |
|
|
if {[expr 0 -$max_read_deskew_hold] < $min_shift} {
|
| 835 |
|
|
set min_shift [expr 0 - $max_read_deskew_hold]
|
| 836 |
|
|
}
|
| 837 |
|
|
} else {
|
| 838 |
|
|
set max_shift [expr 0 - $max_read_deskew_hold]
|
| 839 |
|
|
set min_shift $max_shift
|
| 840 |
|
|
}
|
| 841 |
|
|
} else {
|
| 842 |
|
|
# In this case we can also consider the DQS path pessimism since we can guarantee we have enough delay chain settings to align it
|
| 843 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2]
|
| 844 |
|
|
set pin_hold_slack [expr $pin_hold_slack - $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2 + $extra_pessimism/2]
|
| 845 |
|
|
|
| 846 |
|
|
# Remember the largest shifts in either direction
|
| 847 |
|
|
if {[info exist max_shift]} {
|
| 848 |
|
|
if {[expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2] > $max_shift} {
|
| 849 |
|
|
set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2]
|
| 850 |
|
|
}
|
| 851 |
|
|
if {[expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2] < $min_shift} {
|
| 852 |
|
|
set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2]
|
| 853 |
|
|
}
|
| 854 |
|
|
} else {
|
| 855 |
|
|
set max_shift [expr $shift_setup_slack + $DQSpath_pessimism/2 + $DQpath_pessimism/2]
|
| 856 |
|
|
set min_shift [expr $shift_setup_slack - $DQSpath_pessimism/2 - $DQpath_pessimism/2]
|
| 857 |
|
|
}
|
| 858 |
|
|
}
|
| 859 |
|
|
} else {
|
| 860 |
|
|
# For uncalibrated calls, there is some spatial correlation between DQ and DQS signals, so remove
|
| 861 |
|
|
# some of the pessimism
|
| 862 |
|
|
set total_DQ_DQS_pessimism [expr $DQSpath_pessimism + $DQpath_pessimism]
|
| 863 |
|
|
set dqs_width [llength $qpins]
|
| 864 |
|
|
if {$dqs_width <= 9} {
|
| 865 |
|
|
set pin_setup_slack [expr $pin_setup_slack + 0.35*$total_DQ_DQS_pessimism]
|
| 866 |
|
|
set pin_hold_slack [expr $pin_hold_slack + 0.35*$total_DQ_DQS_pessimism]
|
| 867 |
|
|
}
|
| 868 |
|
|
}
|
| 869 |
|
|
|
| 870 |
|
|
set setup_slack [min $setup_slack $pin_setup_slack]
|
| 871 |
|
|
set hold_slack [min $hold_slack $pin_hold_slack]
|
| 872 |
|
|
|
| 873 |
|
|
if { $debug } {
|
| 874 |
|
|
puts "READ: $DQSpath_pessimism $DQpath_pessimism ($pin_setup_slack $pin_hold_slack $setup_slack $hold_slack)"
|
| 875 |
|
|
}
|
| 876 |
|
|
set q_index [expr $q_index + 1]
|
| 877 |
|
|
}
|
| 878 |
|
|
}
|
| 879 |
|
|
}
|
| 880 |
|
|
|
| 881 |
|
|
########################################################
|
| 882 |
|
|
# Consider some post calibration effects on calibration
|
| 883 |
|
|
# and output the read summary report
|
| 884 |
|
|
########################################################
|
| 885 |
|
|
|
| 886 |
|
|
set positive_fcolour [list "black" "blue" "blue"]
|
| 887 |
|
|
set negative_fcolour [list "black" "red" "red"]
|
| 888 |
|
|
|
| 889 |
|
|
set rc_summary [list]
|
| 890 |
|
|
|
| 891 |
|
|
set fcolour [hps_sdram_p0_get_colours $default_setup_slack $default_hold_slack]
|
| 892 |
|
|
if {$IP(read_deskew_mode) == "dynamic"} {
|
| 893 |
|
|
lappend rc_summary [list " Before Calibration Read Capture" [hps_sdram_p0_format_3dp $default_setup_slack] [hps_sdram_p0_format_3dp $default_hold_slack]]
|
| 894 |
|
|
} else {
|
| 895 |
|
|
lappend rc_summary [list " Standard Read Capture" [hps_sdram_p0_format_3dp $default_setup_slack] [hps_sdram_p0_format_3dp $default_hold_slack]]
|
| 896 |
|
|
}
|
| 897 |
|
|
|
| 898 |
|
|
if {($IP(read_deskew_mode) == "dynamic") && ($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
|
| 899 |
|
|
lappend rc_summary [list " Memory Calibration" [hps_sdram_p0_format_3dp $mp_setup_slack] [hps_sdram_p0_format_3dp $mp_hold_slack]]
|
| 900 |
|
|
}
|
| 901 |
|
|
|
| 902 |
|
|
if {$IP(read_deskew_mode) == "dynamic"} {
|
| 903 |
|
|
if { $debug } {
|
| 904 |
|
|
puts " $setup_slack $hold_slack"
|
| 905 |
|
|
}
|
| 906 |
|
|
|
| 907 |
|
|
#######################################
|
| 908 |
|
|
# Find values for uncertainty table
|
| 909 |
|
|
set t(rdu_fpga_deskew_s) [expr $setup_slack - $default_setup_slack - $mp_setup_slack]
|
| 910 |
|
|
set t(rdu_fpga_deskew_h) [expr $hold_slack - $default_hold_slack - $mp_hold_slack]
|
| 911 |
|
|
#######################################
|
| 912 |
|
|
|
| 913 |
|
|
# Remove external delays (add slack) that are fixed by the dynamic deskew
|
| 914 |
|
|
[catch {get_float_table_node_delay -src {DELAYCHAIN_T1} -dst {VTVARIATION} -parameters [list IO $interface_type]} t1_vt_variation_percent]
|
| 915 |
|
|
set extra_shift [expr $board(intra_DQS_group_skew) + [hps_sdram_p0_round_3dp [expr (1.0-$t1_vt_variation_percent)*$fpga(tDQS_PSERR)]]]
|
| 916 |
|
|
|
| 917 |
|
|
if {$extra_shift > [expr $max_read_deskew_setup - $max_shift]} {
|
| 918 |
|
|
set setup_slack [expr $setup_slack + $max_read_deskew_setup - $max_shift]
|
| 919 |
|
|
} else {
|
| 920 |
|
|
set setup_slack [expr $setup_slack + $extra_shift]
|
| 921 |
|
|
}
|
| 922 |
|
|
if {$extra_shift > [expr $max_read_deskew_hold + $min_shift]} {
|
| 923 |
|
|
set hold_slack [expr $hold_slack + $max_read_deskew_hold + $min_shift]
|
| 924 |
|
|
} else {
|
| 925 |
|
|
set hold_slack [expr $hold_slack + $extra_shift]
|
| 926 |
|
|
}
|
| 927 |
|
|
|
| 928 |
|
|
if { $debug } {
|
| 929 |
|
|
puts " $setup_slack $hold_slack"
|
| 930 |
|
|
}
|
| 931 |
|
|
set deskew_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack]
|
| 932 |
|
|
set deskew_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack]
|
| 933 |
|
|
lappend rc_summary [list " Deskew Read" [hps_sdram_p0_format_3dp $deskew_setup] [hps_sdram_p0_format_3dp $deskew_hold]]
|
| 934 |
|
|
|
| 935 |
|
|
#######################################
|
| 936 |
|
|
# Find values for uncertainty table
|
| 937 |
|
|
set t(rdu_external_deskew_s) [expr $deskew_setup - $t(rdu_fpga_deskew_s) + $mp_setup_slack]
|
| 938 |
|
|
set t(rdu_external_deskew_h) [expr $deskew_hold - $t(rdu_fpga_deskew_h) + $mp_hold_slack]
|
| 939 |
|
|
#######################################
|
| 940 |
|
|
|
| 941 |
|
|
# Consider errors in the dynamic deskew
|
| 942 |
|
|
set t1_quantization $IP(quantization_T1)
|
| 943 |
|
|
set setup_slack [expr $setup_slack - $t1_quantization]
|
| 944 |
|
|
set hold_slack [expr $hold_slack - $t1_quantization]
|
| 945 |
|
|
if { $debug } {
|
| 946 |
|
|
puts " $setup_slack $hold_slack"
|
| 947 |
|
|
}
|
| 948 |
|
|
lappend rc_summary [list " Quantization error" [hps_sdram_p0_format_3dp [expr 0-$t1_quantization]] [hps_sdram_p0_format_3dp [expr 0-$t1_quantization]]]
|
| 949 |
|
|
|
| 950 |
|
|
# Consider variation in the delay chains used during dynamic deksew
|
| 951 |
|
|
set dqs_period [ hps_sdram_p0_get_dqs_period $pins(dqs_pins) ]
|
| 952 |
|
|
set offset_from_90 [hps_sdram_p0_get_acv_read_offset $period $dqs_phase $dqs_period]
|
| 953 |
|
|
if {$IP(num_ranks) == 1} {
|
| 954 |
|
|
set t1_variation [expr [min [expr $offset_from_90 + [max [expr $MP(DQSQ)*$t(DQSQ)] [expr $MP(QH_time)*(0.5*$period - $t(QH_time))]] + 2*$board(intra_DQS_group_skew) + $max_package_skew + $fpga(tDQS_PSERR)] [max $max_read_deskew_setup $max_read_deskew_hold]]*2*$t1_vt_variation_percent*0.75]
|
| 955 |
|
|
} else {
|
| 956 |
|
|
set t1_variation [expr [min [expr $offset_from_90 + 2*$board(intra_DQS_group_skew) + $max_package_skew + $fpga(tDQS_PSERR)] [max $max_read_deskew_setup $max_read_deskew_hold]]*2*$t1_vt_variation_percent*0.75]
|
| 957 |
|
|
}
|
| 958 |
|
|
if {($dqs_period < 1.250) && ($family == "arria v")} {
|
| 959 |
|
|
set speedgrade [string trim [string range [get_speedgrade_string] 0 0]]
|
| 960 |
|
|
if {$speedgrade == 6} {
|
| 961 |
|
|
set further_dqs_pserr 0.025
|
| 962 |
|
|
set t1_variation [expr $t1_variation + $further_dqs_pserr]
|
| 963 |
|
|
}
|
| 964 |
|
|
}
|
| 965 |
|
|
set setup_slack [expr $setup_slack - $t1_variation]
|
| 966 |
|
|
set hold_slack [expr $hold_slack - $t1_variation]
|
| 967 |
|
|
if { $debug } {
|
| 968 |
|
|
puts " $setup_slack $hold_slack"
|
| 969 |
|
|
}
|
| 970 |
|
|
lappend rc_summary [list " Calibration uncertainty" [hps_sdram_p0_format_3dp [expr 0-$t1_variation]] [hps_sdram_p0_format_3dp [expr 0-$t1_variation]]]
|
| 971 |
|
|
|
| 972 |
|
|
#######################################
|
| 973 |
|
|
# Find values for uncertainty table
|
| 974 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 975 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 976 |
|
|
set t(rdu_calibration_uncertaintyerror_s) [expr 0 - $t1_variation - $t1_quantization]
|
| 977 |
|
|
set t(rdu_calibration_uncertaintyerror_h) [expr 0 - $t1_variation - $t1_quantization]
|
| 978 |
|
|
set t(rdu_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(rdu_input_max_delay_external)]
|
| 979 |
|
|
set t(rdu_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(rdu_input_min_delay_external)]
|
| 980 |
|
|
set t(rdu_extl_uncertainty_s) [expr $t(rdu_input_max_delay_external)]
|
| 981 |
|
|
set t(rdu_extl_uncertainty_h) [expr $t(rdu_input_min_delay_external)]
|
| 982 |
|
|
}
|
| 983 |
|
|
#######################################
|
| 984 |
|
|
|
| 985 |
|
|
} else {
|
| 986 |
|
|
set pessimism_setup [expr $setup_slack - $default_setup_slack - $mp_setup_slack]
|
| 987 |
|
|
set pessimism_hold [expr $hold_slack - $default_hold_slack - $mp_hold_slack]
|
| 988 |
|
|
lappend rc_summary [list " Spatial correlation pessimism removal" [hps_sdram_p0_format_3dp $pessimism_setup] [hps_sdram_p0_format_3dp $pessimism_hold]]
|
| 989 |
|
|
|
| 990 |
|
|
#######################################
|
| 991 |
|
|
# Find values for uncertainty table
|
| 992 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 993 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 994 |
|
|
set t(rdu_fpga_deskew_s) 0
|
| 995 |
|
|
set t(rdu_fpga_deskew_h) 0
|
| 996 |
|
|
set t(rdu_external_deskew_s) 0
|
| 997 |
|
|
set t(rdu_external_deskew_h) 0
|
| 998 |
|
|
set t(rdu_calibration_uncertaintyerror_s) 0
|
| 999 |
|
|
set t(rdu_calibration_uncertaintyerror_h) 0
|
| 1000 |
|
|
set t(rdu_fpga_uncertainty_s) [expr $t(CK)/4 - $default_setup_slack - $t(rdu_input_max_delay_external) - $pessimism_setup]
|
| 1001 |
|
|
set t(rdu_fpga_uncertainty_h) [expr $t(CK)/4 - $default_hold_slack - $t(rdu_input_min_delay_external) - $pessimism_hold]
|
| 1002 |
|
|
set t(rdu_extl_uncertainty_s) [expr $t(rdu_input_max_delay_external)]
|
| 1003 |
|
|
set t(rdu_extl_uncertainty_h) [expr $t(rdu_input_min_delay_external)]
|
| 1004 |
|
|
}
|
| 1005 |
|
|
#######################################
|
| 1006 |
|
|
}
|
| 1007 |
|
|
|
| 1008 |
|
|
#######################################
|
| 1009 |
|
|
# Create the read analysis panel
|
| 1010 |
|
|
set panel_name "$inst Read Capture"
|
| 1011 |
|
|
set root_folder_name [get_current_timequest_report_folder]
|
| 1012 |
|
|
|
| 1013 |
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
| 1014 |
|
|
set panel_name "${root_folder_name}||$panel_name"
|
| 1015 |
|
|
}
|
| 1016 |
|
|
# Create the root if it doesn't yet exist
|
| 1017 |
|
|
if {[get_report_panel_id $root_folder_name] == -1} {
|
| 1018 |
|
|
set panel_id [create_report_panel -folder $root_folder_name]
|
| 1019 |
|
|
}
|
| 1020 |
|
|
|
| 1021 |
|
|
# Delete any pre-existing summary panel
|
| 1022 |
|
|
set panel_id [get_report_panel_id $panel_name]
|
| 1023 |
|
|
if {$panel_id != -1} {
|
| 1024 |
|
|
delete_report_panel -id $panel_id
|
| 1025 |
|
|
}
|
| 1026 |
|
|
|
| 1027 |
|
|
if {($setup_slack < 0) || ($hold_slack <0)} {
|
| 1028 |
|
|
set panel_id [create_report_panel -table $panel_name -color red]
|
| 1029 |
|
|
} else {
|
| 1030 |
|
|
set panel_id [create_report_panel -table $panel_name]
|
| 1031 |
|
|
}
|
| 1032 |
|
|
add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"]
|
| 1033 |
|
|
|
| 1034 |
|
|
if {$IP(read_deskew_mode) == "dynamic"} {
|
| 1035 |
|
|
set fcolour [hps_sdram_p0_get_colours $setup_slack $hold_slack]
|
| 1036 |
|
|
add_row_to_table -id $panel_id [list "After Calibration Read Capture" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]] -fcolor $fcolour
|
| 1037 |
|
|
lappend summary [list $opcname 0 "Read Capture ($opcname)" $setup_slack $hold_slack]
|
| 1038 |
|
|
} else {
|
| 1039 |
|
|
set fcolour [hps_sdram_p0_get_colours $setup_slack $hold_slack]
|
| 1040 |
|
|
add_row_to_table -id $panel_id [list "Read Capture" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]] -fcolor $fcolour
|
| 1041 |
|
|
lappend summary [list $opcname 0 "Read Capture ($opcname)" $setup_slack $hold_slack]
|
| 1042 |
|
|
}
|
| 1043 |
|
|
|
| 1044 |
|
|
foreach summary_line $rc_summary {
|
| 1045 |
|
|
add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour
|
| 1046 |
|
|
}
|
| 1047 |
|
|
|
| 1048 |
|
|
#######################################
|
| 1049 |
|
|
# Create the Read uncertainty panel
|
| 1050 |
|
|
set uncertainty_reporting [get_ini_var -name "qsta_enable_uncertainty_ddr_reporting"]
|
| 1051 |
|
|
if {[string equal -nocase $uncertainty_reporting on]} {
|
| 1052 |
|
|
set panel_name "$inst Read Capture Uncertainty"
|
| 1053 |
|
|
set root_folder_name [get_current_timequest_report_folder]
|
| 1054 |
|
|
|
| 1055 |
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
| 1056 |
|
|
set panel_name "${root_folder_name}||$panel_name"
|
| 1057 |
|
|
}
|
| 1058 |
|
|
|
| 1059 |
|
|
# Delete any pre-existing summary panel
|
| 1060 |
|
|
set panel_id [get_report_panel_id $panel_name]
|
| 1061 |
|
|
if {$panel_id != -1} {
|
| 1062 |
|
|
delete_report_panel -id $panel_id
|
| 1063 |
|
|
}
|
| 1064 |
|
|
|
| 1065 |
|
|
set panel_id [create_report_panel -table $panel_name]
|
| 1066 |
|
|
add_row_to_table -id $panel_id [list "Value" "Setup Side" "Hold Side"]
|
| 1067 |
|
|
add_row_to_table -id $panel_id [list "Uncertainty" "" ""]
|
| 1068 |
|
|
add_row_to_table -id $panel_id [list " FPGA uncertainty" [hps_sdram_p0_format_3dp $t(rdu_fpga_uncertainty_s)] [hps_sdram_p0_format_3dp $t(rdu_fpga_uncertainty_h)]]
|
| 1069 |
|
|
add_row_to_table -id $panel_id [list " External uncertainty" [hps_sdram_p0_format_3dp $t(rdu_extl_uncertainty_s)] [hps_sdram_p0_format_3dp $t(rdu_extl_uncertainty_h)]]
|
| 1070 |
|
|
add_row_to_table -id $panel_id [list "Deskew" "" ""]
|
| 1071 |
|
|
add_row_to_table -id $panel_id [list " FPGA deskew" [hps_sdram_p0_format_3dp $t(rdu_fpga_deskew_s)] [hps_sdram_p0_format_3dp $t(rdu_fpga_deskew_h)]]
|
| 1072 |
|
|
add_row_to_table -id $panel_id [list " External deskew" [hps_sdram_p0_format_3dp $t(rdu_external_deskew_s)] [hps_sdram_p0_format_3dp $t(rdu_external_deskew_h)]]
|
| 1073 |
|
|
add_row_to_table -id $panel_id [list " Calibration uncertainty/error" [hps_sdram_p0_format_3dp $t(rdu_calibration_uncertaintyerror_s)] [hps_sdram_p0_format_3dp $t(rdu_calibration_uncertaintyerror_h)]]
|
| 1074 |
|
|
}
|
| 1075 |
|
|
}
|
| 1076 |
|
|
|
| 1077 |
|
|
#############################################################
|
| 1078 |
|
|
# Other Timing Analysis
|
| 1079 |
|
|
#############################################################
|
| 1080 |
|
|
|
| 1081 |
|
|
proc hps_sdram_p0_perform_phy_analyses {opcs opcname inst inst_controller pin_array_name timing_parameters_array_name summary_name IP_name} {
|
| 1082 |
|
|
|
| 1083 |
|
|
###############################################################################
|
| 1084 |
|
|
# The PHY analysis concerns the timing requirements of the PHY which includes
|
| 1085 |
|
|
# soft registers in the FPGA core as well as some registers in the hard periphery
|
| 1086 |
|
|
# The read capture and write registers are not analyzed here, even though they
|
| 1087 |
|
|
# are part of the PHY since they are timing analyzed separately.
|
| 1088 |
|
|
###############################################################################
|
| 1089 |
|
|
|
| 1090 |
|
|
#######################################
|
| 1091 |
|
|
# Need access to global variables
|
| 1092 |
|
|
upvar 1 $summary_name summary
|
| 1093 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 1094 |
|
|
upvar 1 $pin_array_name pins
|
| 1095 |
|
|
upvar 1 $IP_name IP
|
| 1096 |
|
|
|
| 1097 |
|
|
set num_failing_path $IP(num_report_paths)
|
| 1098 |
|
|
|
| 1099 |
|
|
set entity_names_on [ hps_sdram_p0_are_entity_names_on ]
|
| 1100 |
|
|
|
| 1101 |
|
|
set prefix [ string map "| |*:" $inst ]
|
| 1102 |
|
|
set prefix "*:$prefix"
|
| 1103 |
|
|
set prefix_controller [ string map "| |*:" $inst_controller ]
|
| 1104 |
|
|
set prefix_controller "*:$prefix_controller"
|
| 1105 |
|
|
|
| 1106 |
|
|
if { ! $entity_names_on } {
|
| 1107 |
|
|
set core_regs [remove_from_collection [get_registers $inst|*] [get_registers $pins(read_capture_ddio)]]
|
| 1108 |
|
|
} else {
|
| 1109 |
|
|
set core_regs [remove_from_collection [get_registers $prefix|*] [get_registers $pins(read_capture_ddio)]]
|
| 1110 |
|
|
}
|
| 1111 |
|
|
|
| 1112 |
|
|
# Core
|
| 1113 |
|
|
set res_0 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core (setup)" -setup]
|
| 1114 |
|
|
set res_1 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core (hold)" -hold]
|
| 1115 |
|
|
lappend summary [list $opcname 0 "Core ($opcname)" [lindex $res_0 1] [lindex $res_1 1] [lindex $res_0 0] [lindex $res_1 0]]
|
| 1116 |
|
|
|
| 1117 |
|
|
# Core Recovery/Removal
|
| 1118 |
|
|
set res_0 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core Recovery/Removal (recovery)" -recovery]
|
| 1119 |
|
|
set res_1 [report_timing -detail full_path -to $core_regs -npaths $num_failing_path -panel_name "$inst Core Recovery/Removal (removal)" -removal]
|
| 1120 |
|
|
lappend summary [list $opcname 0 "Core Recovery/Removal ($opcname)" [lindex $res_0 1] [lindex $res_1 1] [lindex $res_0 0] [lindex $res_1 0]]
|
| 1121 |
|
|
|
| 1122 |
|
|
|
| 1123 |
|
|
}
|
| 1124 |
|
|
|
| 1125 |
|
|
proc hps_sdram_p0_perform_ac_analyses {opcs opcname inst scale_factors_name pin_array_name timing_parameters_array_name summary_name IP_name} {
|
| 1126 |
|
|
|
| 1127 |
|
|
###############################################################################
|
| 1128 |
|
|
# The adress/command analysis concerns the timing requirements of the pins (other
|
| 1129 |
|
|
# than the D/Q pins) which go to the memory device/DIMM. These include address/command
|
| 1130 |
|
|
# pins, some of which are runing at Single-Data-Rate (SDR) and some which are
|
| 1131 |
|
|
# running at Half-Data-Rate (HDR).
|
| 1132 |
|
|
###############################################################################
|
| 1133 |
|
|
|
| 1134 |
|
|
#######################################
|
| 1135 |
|
|
# Need access to global variables
|
| 1136 |
|
|
upvar 1 $summary_name summary
|
| 1137 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 1138 |
|
|
upvar 1 $pin_array_name pins
|
| 1139 |
|
|
upvar 1 $IP_name IP
|
| 1140 |
|
|
upvar 1 $scale_factors_name scale_factors
|
| 1141 |
|
|
set eol_reduction_factor $IP(eol_reduction_factor_addr)
|
| 1142 |
|
|
|
| 1143 |
|
|
set num_failing_path $IP(num_report_paths)
|
| 1144 |
|
|
|
| 1145 |
|
|
set add_pins $pins(add_pins)
|
| 1146 |
|
|
set ba_pins $pins(ba_pins)
|
| 1147 |
|
|
set cmd_pins $pins(cmd_pins)
|
| 1148 |
|
|
set reset_pins $pins(reset_pins)
|
| 1149 |
|
|
set ac_pins [ concat $add_pins $ba_pins $cmd_pins ]
|
| 1150 |
|
|
|
| 1151 |
|
|
set entity_names_on [ hps_sdram_p0_are_entity_names_on ]
|
| 1152 |
|
|
|
| 1153 |
|
|
set prefix [ string map "| |*:" $inst ]
|
| 1154 |
|
|
set prefix "*:$prefix"
|
| 1155 |
|
|
|
| 1156 |
|
|
set panel_name_setup "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Address Command (setup)"
|
| 1157 |
|
|
set panel_name_hold "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst Address Command (hold)"
|
| 1158 |
|
|
|
| 1159 |
|
|
set panel_name_dqs_setup "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst DQS vs CK (setup)"
|
| 1160 |
|
|
set panel_name_dqs_hold "Before Extra Common Clock Pessimism Removal \u0028Negative slacks are OK\u0029||$inst DQS vs CK (hold)"
|
| 1161 |
|
|
|
| 1162 |
|
|
######################################################################
|
| 1163 |
|
|
##Default Address Command Analysis
|
| 1164 |
|
|
set res_0 [report_timing -detail full_path -to $ac_pins \
|
| 1165 |
|
|
-npaths $num_failing_path -panel_name $panel_name_setup -setup -disable_panel_color -quiet]
|
| 1166 |
|
|
set res_1 [report_timing -detail full_path -to $ac_pins \
|
| 1167 |
|
|
-npaths $num_failing_path -panel_name $panel_name_hold -hold -disable_panel_color -quiet]
|
| 1168 |
|
|
set default_setup_slack [lindex $res_0 1]
|
| 1169 |
|
|
set default_hold_slack [lindex $res_1 1]
|
| 1170 |
|
|
|
| 1171 |
|
|
# Perform the default A/C timing analysis to get required and arrival times
|
| 1172 |
|
|
set paths_setup [get_timing_paths -to [get_ports $ac_pins] -npaths 400 -setup -nworst 1]
|
| 1173 |
|
|
set paths_hold [get_timing_paths -to [get_ports $ac_pins] -npaths 400 -hold -nworst 1]
|
| 1174 |
|
|
|
| 1175 |
|
|
######################################################################
|
| 1176 |
|
|
##Default DQS vs CK Analysis
|
| 1177 |
|
|
set dqs_res_0 [report_timing -detail full_path -to [get_ports $pins(dqs_pins)] -npaths $num_failing_path -panel_name $panel_name_dqs_setup -setup -disable_panel_color -quiet]
|
| 1178 |
|
|
set dqs_res_1 [report_timing -detail full_path -to [get_ports $pins(dqs_pins)] -npaths $num_failing_path -panel_name $panel_name_dqs_hold -hold -disable_panel_color -quiet]
|
| 1179 |
|
|
set default_dqs_setup_slack [lindex $dqs_res_0 1]
|
| 1180 |
|
|
set default_dqs_hold_slack [lindex $dqs_res_1 1]
|
| 1181 |
|
|
|
| 1182 |
|
|
# Perform the default DQS vs CK timing analysis to get required and arrival times
|
| 1183 |
|
|
set dqs_paths_setup [get_timing_paths -to [get_ports $pins(dqs_pins)] -npaths 400 -setup -nworst 1]
|
| 1184 |
|
|
set dqs_paths_hold [get_timing_paths -to [get_ports $pins(dqs_pins)] -npaths 400 -hold -nworst 1]
|
| 1185 |
|
|
|
| 1186 |
|
|
######################################################################
|
| 1187 |
|
|
##Find portions of common clock pessimism removal
|
| 1188 |
|
|
|
| 1189 |
|
|
# Some regular expression matching to create the right strings
|
| 1190 |
|
|
set pll_clock $pins(pll_write_clock)
|
| 1191 |
|
|
|
| 1192 |
|
|
set ck_periphery_nodes [list]
|
| 1193 |
|
|
foreach ck_pin $pins(ck_pins) {
|
| 1194 |
|
|
set clk_clk_phase_select_node [hps_sdram_p0_traverse_to_clock_phase_select $ck_pin msg_list]
|
| 1195 |
|
|
set clk_periphery_node ${clk_clk_phase_select_node}|clkout
|
| 1196 |
|
|
lappend clk_periphery_nodes $clk_periphery_node
|
| 1197 |
|
|
}
|
| 1198 |
|
|
set clk_periphery_nodes [lsort -unique $clk_periphery_nodes]
|
| 1199 |
|
|
set clk_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $clk_periphery_nodes] "arrival_time"]
|
| 1200 |
|
|
if {$clk_max <= 0} {set clk_max -9999}
|
| 1201 |
|
|
set clk_min [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $clk_periphery_nodes -min_path] "arrival_time"]
|
| 1202 |
|
|
if {$clk_min <= 0} {set clk_min 9999}
|
| 1203 |
|
|
|
| 1204 |
|
|
set CKperiphery_min [get_path -rise_from $clk_periphery_nodes -rise_to $pins(ck_pins) -min_path -nworst 1]
|
| 1205 |
|
|
set CKperiphery_max [get_path -rise_from $clk_periphery_nodes -rise_to $pins(ck_pins) -nworst 1]
|
| 1206 |
|
|
set CKperiphery_min_delay [hps_sdram_p0_min_in_collection $CKperiphery_min "arrival_time"]
|
| 1207 |
|
|
set CKperiphery_max_delay [hps_sdram_p0_max_in_collection $CKperiphery_max "arrival_time"]
|
| 1208 |
|
|
set aiot_delay [hps_sdram_p0_round_3dp [expr [hps_sdram_p0_get_rise_aiot_delay [lindex $pins(ck_pins) 0]] * 1e9]]
|
| 1209 |
|
|
set CKperiphery_min_delay [expr $CKperiphery_min_delay - $aiot_delay]
|
| 1210 |
|
|
set CKperiphery_max_delay [expr $CKperiphery_max_delay - $aiot_delay]
|
| 1211 |
|
|
set CKpath_pessimism [expr $CKperiphery_min_delay*($scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor) + + ($CKperiphery_max_delay - $CKperiphery_min_delay)/2]
|
| 1212 |
|
|
|
| 1213 |
|
|
######################################################################
|
| 1214 |
|
|
##Loop over AC pins, and perform analysis
|
| 1215 |
|
|
|
| 1216 |
|
|
set pll_clock $pins(pll_write_clock)
|
| 1217 |
|
|
# The A/C CPS is set to inversion mode, so we require a RF path
|
| 1218 |
|
|
set rise_or_fall_to "fall_to"
|
| 1219 |
|
|
|
| 1220 |
|
|
set setup_slack 1000000000
|
| 1221 |
|
|
set hold_slack 1000000000
|
| 1222 |
|
|
foreach ac_pin $ac_pins {
|
| 1223 |
|
|
|
| 1224 |
|
|
set pin_setup_slack [hps_sdram_p0_min_in_collection_to_name $paths_setup "slack" $ac_pin]
|
| 1225 |
|
|
set pin_hold_slack [hps_sdram_p0_min_in_collection_to_name $paths_hold "slack" $ac_pin]
|
| 1226 |
|
|
set current_ccpr [hps_sdram_p0_min_in_collection_to_name $paths_hold "ccpp" $ac_pin]
|
| 1227 |
|
|
|
| 1228 |
|
|
set ac_clk_phase_select_node [hps_sdram_p0_traverse_to_clock_phase_select $ac_pin msg_list]
|
| 1229 |
|
|
set ac_periphery_node ${ac_clk_phase_select_node}|clkout
|
| 1230 |
|
|
|
| 1231 |
|
|
set ac_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -${rise_or_fall_to} $ac_periphery_node] "arrival_time"]
|
| 1232 |
|
|
if {$ac_max <= 0} {set ac_max -9999}
|
| 1233 |
|
|
set ac_min [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -${rise_or_fall_to} $ac_periphery_node -min_path] "arrival_time"]
|
| 1234 |
|
|
if {$ac_min <= 0} {set ac_min 9999}
|
| 1235 |
|
|
set extra_ccpr [hps_sdram_p0_round_3dp [expr ($clk_max - $clk_min + $ac_max - $ac_min)/2.0]]
|
| 1236 |
|
|
|
| 1237 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $extra_ccpr]
|
| 1238 |
|
|
set pin_hold_slack [expr $pin_hold_slack + $extra_ccpr]
|
| 1239 |
|
|
|
| 1240 |
|
|
set ACperiphery_min [get_path -rise_from $ac_periphery_node -rise_to $ac_pin -min_path -nworst 1 ]
|
| 1241 |
|
|
set ACperiphery_max [get_path -rise_from $ac_periphery_node -rise_to $ac_pin -nworst 1]
|
| 1242 |
|
|
set ACperiphery_min_delay [hps_sdram_p0_min_in_collection $ACperiphery_min "arrival_time"]
|
| 1243 |
|
|
set ACperiphery_max_delay [hps_sdram_p0_max_in_collection $ACperiphery_max "arrival_time"]
|
| 1244 |
|
|
set aiot_delay [hps_sdram_p0_round_3dp [expr [hps_sdram_p0_get_rise_aiot_delay [lindex $ac_pin 0]] * 1e9]]
|
| 1245 |
|
|
set ACperiphery_min_delay [expr $ACperiphery_min_delay - $aiot_delay]
|
| 1246 |
|
|
set ACperiphery_max_delay [expr $ACperiphery_max_delay - $aiot_delay]
|
| 1247 |
|
|
set ACpath_pessimism [expr $ACperiphery_min_delay*($scale_factors(eol) - $scale_factors(eol)/$eol_reduction_factor) + ($ACperiphery_max_delay - $ACperiphery_min_delay)/2]
|
| 1248 |
|
|
|
| 1249 |
|
|
set pin_setup_slack [expr $pin_setup_slack + $ACpath_pessimism]
|
| 1250 |
|
|
set pin_hold_slack [expr $pin_hold_slack + $CKpath_pessimism]
|
| 1251 |
|
|
|
| 1252 |
|
|
set setup_slack [min $setup_slack $pin_setup_slack]
|
| 1253 |
|
|
set hold_slack [min $hold_slack $pin_hold_slack]
|
| 1254 |
|
|
|
| 1255 |
|
|
}
|
| 1256 |
|
|
|
| 1257 |
|
|
########################################
|
| 1258 |
|
|
########################################
|
| 1259 |
|
|
##Create the a/c analysis panel
|
| 1260 |
|
|
set ac_summary [list]
|
| 1261 |
|
|
lappend ac_summary [list " Standard Address Command" [hps_sdram_p0_format_3dp $default_setup_slack] [hps_sdram_p0_format_3dp $default_hold_slack]]
|
| 1262 |
|
|
lappend ac_summary [list " Extra common clock and spatial correlation pessimism removal" [hps_sdram_p0_format_3dp [expr $setup_slack - $default_setup_slack]] [hps_sdram_p0_format_3dp [expr $hold_slack - $default_hold_slack]]]
|
| 1263 |
|
|
|
| 1264 |
|
|
set positive_fcolour [list "black" "blue" "blue"]
|
| 1265 |
|
|
set negative_fcolour [list "black" "red" "red"]
|
| 1266 |
|
|
set panel_name "$inst Address Command"
|
| 1267 |
|
|
set root_folder_name [get_current_timequest_report_folder]
|
| 1268 |
|
|
|
| 1269 |
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
| 1270 |
|
|
set panel_name "${root_folder_name}||$panel_name"
|
| 1271 |
|
|
}
|
| 1272 |
|
|
# Create the root if it doesn't yet exist
|
| 1273 |
|
|
if {[get_report_panel_id $root_folder_name] == -1} {
|
| 1274 |
|
|
set panel_id [create_report_panel -folder $root_folder_name]
|
| 1275 |
|
|
}
|
| 1276 |
|
|
|
| 1277 |
|
|
# Delete any pre-existing summary panel
|
| 1278 |
|
|
set panel_id [get_report_panel_id $panel_name]
|
| 1279 |
|
|
if {$panel_id != -1} {
|
| 1280 |
|
|
delete_report_panel -id $panel_id
|
| 1281 |
|
|
}
|
| 1282 |
|
|
|
| 1283 |
|
|
if {($setup_slack < 0) || ($hold_slack <0)} {
|
| 1284 |
|
|
set panel_id [create_report_panel -table $panel_name -color red]
|
| 1285 |
|
|
} else {
|
| 1286 |
|
|
set panel_id [create_report_panel -table $panel_name]
|
| 1287 |
|
|
}
|
| 1288 |
|
|
add_row_to_table -id $panel_id [list "Operation" "Setup Slack" "Hold Slack"]
|
| 1289 |
|
|
|
| 1290 |
|
|
set fcolour [hps_sdram_p0_get_colours $setup_slack $hold_slack]
|
| 1291 |
|
|
add_row_to_table -id $panel_id [list "Address Command" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]] -fcolor $fcolour
|
| 1292 |
|
|
lappend summary [list $opcname 0 "Address Command ($opcname)" [hps_sdram_p0_format_3dp $setup_slack] [hps_sdram_p0_format_3dp $hold_slack]]
|
| 1293 |
|
|
|
| 1294 |
|
|
foreach summary_line $ac_summary {
|
| 1295 |
|
|
add_row_to_table -id $panel_id $summary_line -fcolors $positive_fcolour
|
| 1296 |
|
|
}
|
| 1297 |
|
|
|
| 1298 |
|
|
######################################################################
|
| 1299 |
|
|
##Loop over DQS pins, and perform analysis
|
| 1300 |
|
|
|
| 1301 |
|
|
set pll_clock $pins(pll_write_clock)
|
| 1302 |
|
|
|
| 1303 |
|
|
set dqs_setup_slack 1000000000
|
| 1304 |
|
|
set dqs_hold_slack 1000000000
|
| 1305 |
|
|
foreach dqs_pin $pins(dqs_pins) {
|
| 1306 |
|
|
|
| 1307 |
|
|
set dqs_pin_setup_slack [hps_sdram_p0_min_in_collection_to_name $dqs_paths_setup "slack" $dqs_pin]
|
| 1308 |
|
|
set dqs_pin_hold_slack [hps_sdram_p0_min_in_collection_to_name $dqs_paths_hold "slack" $dqs_pin]
|
| 1309 |
|
|
|
| 1310 |
|
|
set dqs_clk_phase_select_node [hps_sdram_p0_traverse_to_clock_phase_select $dqs_pin msg_list]
|
| 1311 |
|
|
set dqs_periphery_node ${dqs_clk_phase_select_node}|clkout
|
| 1312 |
|
|
|
| 1313 |
|
|
set dqs_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $dqs_periphery_node] "arrival_time"]
|
| 1314 |
|
|
if {$dqs_max <= 0} {set dqs_max -9999}
|
| 1315 |
|
|
set dqs_min [hps_sdram_p0_max_in_collection [get_path -rise_from $pll_clock -rise_to $dqs_periphery_node -min_path] "arrival_time"]
|
| 1316 |
|
|
if {$dqs_min <= 0} {set dqs_min 9999}
|
| 1317 |
|
|
|
| 1318 |
|
|
set extra_ccpr [hps_sdram_p0_round_3dp [expr ($clk_max - $clk_min + $dqs_max - $dqs_min)/2.0]]
|
| 1319 |
|
|
|
| 1320 |
|
|
set dqs_pin_setup_slack [expr $dqs_pin_setup_slack + $extra_ccpr]
|
| 1321 |
|
|
set dqs_pin_hold_slack [expr $dqs_pin_hold_slack + $extra_ccpr]
|
| 1322 |
|
|
|
| 1323 |
|
|
set dqs_setup_slack [min $dqs_setup_slack $dqs_pin_setup_slack]
|
| 1324 |
|
|
set dqs_hold_slack [min $dqs_hold_slack $dqs_pin_hold_slack]
|
| 1325 |
|
|
}
|
| 1326 |
|
|
|
| 1327 |
|
|
########################################
|
| 1328 |
|
|
########################################
|
| 1329 |
|
|
##Create the DQS vs CK analysis panel
|
| 1330 |
|
|
|
| 1331 |
|
|
set dqs_summary [list]
|
| 1332 |
|
|
|
| 1333 |
|
|
lappend dqs_summary [list " Standard DQS vs CK" [hps_sdram_p0_format_3dp $default_dqs_setup_slack] [hps_sdram_p0_format_3dp $default_dqs_hold_slack]]
|
| 1334 |
|
|
lappend dqs_summary [list " Extra common clock pessimism removal" [hps_sdram_p0_format_3dp [expr $dqs_setup_slack - $default_dqs_setup_slack]] [hps_sdram_p0_format_3dp [expr $dqs_hold_slack - $default_dqs_hold_slack]]]
|
| 1335 |
|
|
|
| 1336 |
|
|
set dqs_panel_name "$inst DQS vs CK"
|
| 1337 |
|
|
|
| 1338 |
|
|
if { ! [string match "${root_folder_name}*" $dqs_panel_name] } {
|
| 1339 |
|
|
set dqs_panel_name "${root_folder_name}||$dqs_panel_name"
|
| 1340 |
|
|
}
|
| 1341 |
|
|
|
| 1342 |
|
|
# Delete any pre-existing summary panel
|
| 1343 |
|
|
set dqs_panel_id [get_report_panel_id $dqs_panel_name]
|
| 1344 |
|
|
if {$dqs_panel_id != -1} {
|
| 1345 |
|
|
delete_report_panel -id $dqs_panel_id
|
| 1346 |
|
|
}
|
| 1347 |
|
|
|
| 1348 |
|
|
if {($dqs_setup_slack < 0) || ($dqs_hold_slack <0)} {
|
| 1349 |
|
|
set dqs_panel_id [create_report_panel -table $dqs_panel_name -color red]
|
| 1350 |
|
|
} else {
|
| 1351 |
|
|
set dqs_panel_id [create_report_panel -table $dqs_panel_name]
|
| 1352 |
|
|
}
|
| 1353 |
|
|
add_row_to_table -id $dqs_panel_id [list "Operation" "Setup Slack" "Hold Slack"]
|
| 1354 |
|
|
|
| 1355 |
|
|
set fcolour [hps_sdram_p0_get_colours $dqs_setup_slack $dqs_hold_slack]
|
| 1356 |
|
|
add_row_to_table -id $dqs_panel_id [list "DQS vs CK" [hps_sdram_p0_format_3dp $dqs_setup_slack] [hps_sdram_p0_format_3dp $dqs_hold_slack]] -fcolor $fcolour
|
| 1357 |
|
|
lappend summary [list $opcname 0 "DQS vs CK ($opcname)" [hps_sdram_p0_format_3dp $dqs_setup_slack] [hps_sdram_p0_format_3dp $dqs_hold_slack]]
|
| 1358 |
|
|
|
| 1359 |
|
|
foreach summary_line $dqs_summary {
|
| 1360 |
|
|
add_row_to_table -id $dqs_panel_id $summary_line -fcolors $positive_fcolour
|
| 1361 |
|
|
}
|
| 1362 |
|
|
}
|
| 1363 |
|
|
|
| 1364 |
|
|
|
| 1365 |
|
|
#############################################################
|
| 1366 |
|
|
# Bus Turnaround Time Analysis
|
| 1367 |
|
|
#############################################################
|
| 1368 |
|
|
|
| 1369 |
|
|
proc hps_sdram_p0_perform_flexible_bus_turnaround_time_analysis {opcs opcname instname family period dll_length interface_type tJITper tJITdty tDCD pll_steps pin_array_name timing_parameters_array_name summary_name MP_name IP_name SSN_name board_name ISI_parameters_name} {
|
| 1370 |
|
|
|
| 1371 |
|
|
###############################################################################
|
| 1372 |
|
|
# The bus-turnaround time analysis concerns making sure there is no contention on
|
| 1373 |
|
|
# on the DQ bus when a read command is followed by a write command. When a read
|
| 1374 |
|
|
# command is issued, some cycles later the memory takes control of the DQS bus and
|
| 1375 |
|
|
# starts sending back data to the controller. If the controller issues a write
|
| 1376 |
|
|
# command too early then the read command data may not have fully read and there
|
| 1377 |
|
|
# may be contention on the bus. This analysis determines how much margin there
|
| 1378 |
|
|
# is on the switchover time and if the slack is negative, either the controller's
|
| 1379 |
|
|
# bus turnaround time must be increased (which reduces effeciency), or the
|
| 1380 |
|
|
# absolute delays on the board traces must be reduced.
|
| 1381 |
|
|
###############################################################################
|
| 1382 |
|
|
|
| 1383 |
|
|
#######################################
|
| 1384 |
|
|
# Need access to global variables
|
| 1385 |
|
|
upvar 1 $summary_name summary
|
| 1386 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 1387 |
|
|
upvar 1 $IP_name IP
|
| 1388 |
|
|
upvar 1 $pin_array_name pins
|
| 1389 |
|
|
upvar 1 $board_name board
|
| 1390 |
|
|
upvar 1 $MP_name MP
|
| 1391 |
|
|
upvar 1 $SSN_name SSN
|
| 1392 |
|
|
upvar 1 $ISI_parameters_name ISI
|
| 1393 |
|
|
|
| 1394 |
|
|
# Derived parameters
|
| 1395 |
|
|
if {$t(DWIDTH_RATIO) == 2} {
|
| 1396 |
|
|
set burst_length 4
|
| 1397 |
|
|
} elseif {$t(DWIDTH_RATIO) == 4} {
|
| 1398 |
|
|
set burst_length 8
|
| 1399 |
|
|
} else {
|
| 1400 |
|
|
set burst_length 16
|
| 1401 |
|
|
}
|
| 1402 |
|
|
|
| 1403 |
|
|
######################################################################
|
| 1404 |
|
|
# Find the maximum delay of the CK issuing a read command followed by
|
| 1405 |
|
|
# read data coming back
|
| 1406 |
|
|
|
| 1407 |
|
|
# Maximum clock delay
|
| 1408 |
|
|
set ac_hold [get_timing_paths -to $pins(add_pins) -hold -npaths 100]
|
| 1409 |
|
|
set max_dly [expr [hps_sdram_p0_max_in_collection $ac_hold "clock_skew"]]
|
| 1410 |
|
|
|
| 1411 |
|
|
# SSO and Jitter pushout on clock
|
| 1412 |
|
|
set max_dly [expr $max_dly + $SSN(pushout_o) + $tJITper/2]
|
| 1413 |
|
|
|
| 1414 |
|
|
# CK Board delay
|
| 1415 |
|
|
set max_dly [expr $max_dly + $board(abs_max_CK_delay)]
|
| 1416 |
|
|
|
| 1417 |
|
|
# Read Latency and Burst Lenght
|
| 1418 |
|
|
set max_dly [expr $max_dly + ($t(RL) + $burst_length/2)*$t(CK)]
|
| 1419 |
|
|
|
| 1420 |
|
|
# DQS Board delay
|
| 1421 |
|
|
set max_dly [expr $max_dly + $board(abs_max_DQS_delay)]
|
| 1422 |
|
|
|
| 1423 |
|
|
# Time for DQS to go high impedance relative to the CK
|
| 1424 |
|
|
set max_dly [expr $max_dly + $t(DQSCK)]
|
| 1425 |
|
|
|
| 1426 |
|
|
# SSI pushout on DQS
|
| 1427 |
|
|
set max_dly [expr $max_dly + $SSN(pushout_i)]
|
| 1428 |
|
|
|
| 1429 |
|
|
######################################################################
|
| 1430 |
|
|
# Find the minimum delay of the issuing a write command after read
|
| 1431 |
|
|
# command has been issued and the FPGA taking hold of the DQS trace
|
| 1432 |
|
|
|
| 1433 |
|
|
# Because of the levelling operation we assume that the output delay of
|
| 1434 |
|
|
# the clock is the same as the output delay of the write (other than
|
| 1435 |
|
|
# board delays and transient delays
|
| 1436 |
|
|
set ac_setup [get_timing_paths -to $pins(add_pins) -setup -npaths 100]
|
| 1437 |
|
|
set min_dly [expr [hps_sdram_p0_min_in_collection $ac_setup "clock_skew"]]
|
| 1438 |
|
|
|
| 1439 |
|
|
# SSO pullin on write data
|
| 1440 |
|
|
set min_dly [expr $min_dly - $SSN(pullin_o)]
|
| 1441 |
|
|
|
| 1442 |
|
|
# Jitter and other effects on write data
|
| 1443 |
|
|
set min_dly [expr $min_dly - $t(WL_DCD) - $t(WL_JITTER) - $t(WL_PSE)]
|
| 1444 |
|
|
|
| 1445 |
|
|
# Quantization error on levelling
|
| 1446 |
|
|
set min_dly [expr $min_dly - $IP(quantization_WL)]
|
| 1447 |
|
|
|
| 1448 |
|
|
# Difference in board delay
|
| 1449 |
|
|
set min_dly [expr $min_dly - $board(minCK_DQS_skew)]
|
| 1450 |
|
|
|
| 1451 |
|
|
# Delay between the read command and write command
|
| 1452 |
|
|
set num_clocks_read_to_write [expr $t(RL) - $t(WL) + $burst_length/2 + 2 + $t(rd_to_wr_turnaround_oct)]
|
| 1453 |
|
|
set min_dly [expr $min_dly + $num_clocks_read_to_write*$t(CK)]
|
| 1454 |
|
|
|
| 1455 |
|
|
# Delay between write command and write data on the bus
|
| 1456 |
|
|
set min_dly [expr $min_dly + $t(WL)*$t(CK)]
|
| 1457 |
|
|
|
| 1458 |
|
|
# Adjustment for when the DQS preamble is driven
|
| 1459 |
|
|
set min_dly [expr $min_dly - $t(CK)]
|
| 1460 |
|
|
|
| 1461 |
|
|
# Adjustment for when the OCT is enabled (one cycle berfore DQS preamble)
|
| 1462 |
|
|
set min_dly [expr $min_dly - $t(CK)]
|
| 1463 |
|
|
|
| 1464 |
|
|
set setup_slack [expr $min_dly - $max_dly]
|
| 1465 |
|
|
set hold_slack "--"
|
| 1466 |
|
|
|
| 1467 |
|
|
lappend summary [list $opcname 0 "Bus Turnaround Time ($opcname)" $setup_slack $hold_slack]
|
| 1468 |
|
|
|
| 1469 |
|
|
}
|
| 1470 |
|
|
|
| 1471 |
|
|
|
| 1472 |
|
|
proc hps_sdram_p0_perform_resync_timing_analysis {opcs opcname inst fbasename family scale_factors_name io_std interface_type period pin_array_name timing_parameters_array_name summary_name MP_name IP_name board_name fpga_name SSN_name} {
|
| 1473 |
|
|
|
| 1474 |
|
|
###############################################################################
|
| 1475 |
|
|
# The resynchronization timing analysis concerns transferring read data that
|
| 1476 |
|
|
# has been captured with a DQS strobe to a clock domain under the control of
|
| 1477 |
|
|
# the UniPHY. A special FIFO is used to resynchronize the data which has a wide
|
| 1478 |
|
|
# tolerance to any changes in the arrival time of data from DQS groups
|
| 1479 |
|
|
###############################################################################
|
| 1480 |
|
|
|
| 1481 |
|
|
#######################################
|
| 1482 |
|
|
# Need access to global variables
|
| 1483 |
|
|
upvar 1 $summary_name summary
|
| 1484 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 1485 |
|
|
upvar 1 $pin_array_name pins
|
| 1486 |
|
|
upvar 1 $MP_name MP
|
| 1487 |
|
|
upvar 1 $IP_name IP
|
| 1488 |
|
|
upvar 1 $board_name board
|
| 1489 |
|
|
upvar 1 $fpga_name fpga
|
| 1490 |
|
|
upvar 1 $SSN_name SSN
|
| 1491 |
|
|
upvar 1 $scale_factors_name scale_factors
|
| 1492 |
|
|
|
| 1493 |
|
|
set num_paths 5000
|
| 1494 |
|
|
|
| 1495 |
|
|
set prefix [ string map "| |*:" $inst ]
|
| 1496 |
|
|
set prefix "*:$prefix"
|
| 1497 |
|
|
|
| 1498 |
|
|
lappend summary [list $opcname 0 "Read Resync ($opcname)" 1.000 1.000]
|
| 1499 |
|
|
|
| 1500 |
|
|
return
|
| 1501 |
|
|
#######################################
|
| 1502 |
|
|
# Node names
|
| 1503 |
|
|
set dqs_pins $pins(dqs_pins)
|
| 1504 |
|
|
set fifo ${prefix}*${fbasename}_flop_mem:read_buffering[*].read_subgroup[*].uread_fifo|data_stored[*][*]
|
| 1505 |
|
|
set reg_in_rd_clk_domain ${prefix}*${fbasename}_flop_mem:read_buffering[*].read_subgroup[*].uread_fifo|rd_data[*]
|
| 1506 |
|
|
set reg_wr_address ${prefix}*${fbasename}_read_datapath:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
|
| 1507 |
|
|
set reg_rd_address ${prefix}*${fbasename}_read_datapath:uread_datapath|read_buffering[*].read_subgroup[*].rdaddress[*]
|
| 1508 |
|
|
|
| 1509 |
|
|
#######################################
|
| 1510 |
|
|
# Paths
|
| 1511 |
|
|
set max_DQS_to_fifo_paths [get_path -from $dqs_pins -to $fifo -npaths $num_paths -nworst 1]
|
| 1512 |
|
|
set min_DQS_to_fifo_paths [get_path -from $dqs_pins -to $fifo -npaths $num_paths -min_path -nworst 1]
|
| 1513 |
|
|
|
| 1514 |
|
|
set max_fifo_to_rd_clk_domain_paths [get_path -from $fifo -to $reg_in_rd_clk_domain -npaths $num_paths -nworst 1]
|
| 1515 |
|
|
set min_fifo_to_rd_clk_domain_paths [get_path -from $fifo -to $reg_in_rd_clk_domain -npaths $num_paths -min_path -nworst 1]
|
| 1516 |
|
|
|
| 1517 |
|
|
set max_DQS_to_wr_address_paths [get_path -from $dqs_pins -to $reg_wr_address -npaths $num_paths -nworst 1]
|
| 1518 |
|
|
set min_DQS_to_wr_address_paths [get_path -from $dqs_pins -to $reg_wr_address -npaths $num_paths -min_path -nworst 1]
|
| 1519 |
|
|
|
| 1520 |
|
|
set max_rd_address_to_rd_data_paths [get_path -from $reg_rd_address -to $reg_in_rd_clk_domain -npaths $num_paths -nworst 1]
|
| 1521 |
|
|
set min_rd_address_to_rd_data_paths [get_path -from $reg_rd_address -to $reg_in_rd_clk_domain -npaths $num_paths -min_path -nworst 1]
|
| 1522 |
|
|
|
| 1523 |
|
|
set max_dqs_common_to_fifo [hps_sdram_p0_max_in_collection [get_path -from $dqs_pins -to $fifo -nworst 1] "arrival_time"]
|
| 1524 |
|
|
|
| 1525 |
|
|
#########################################
|
| 1526 |
|
|
# Limit to one endpoint/startpoint
|
| 1527 |
|
|
|
| 1528 |
|
|
foreach_in_collection path $max_DQS_to_fifo_paths {
|
| 1529 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1530 |
|
|
set startpoint [get_node_info -name [get_path_info $path -from]]
|
| 1531 |
|
|
if {[info exist max_DQS_to_fifo_paths_max($startpoint)]} {
|
| 1532 |
|
|
if {$arrival_time > $max_DQS_to_fifo_paths_max($startpoint)} {
|
| 1533 |
|
|
set max_DQS_to_fifo_paths_max($startpoint) $arrival_time
|
| 1534 |
|
|
}
|
| 1535 |
|
|
} else {
|
| 1536 |
|
|
set max_DQS_to_fifo_paths_max($startpoint) $arrival_time
|
| 1537 |
|
|
}
|
| 1538 |
|
|
}
|
| 1539 |
|
|
|
| 1540 |
|
|
foreach_in_collection path $min_DQS_to_fifo_paths {
|
| 1541 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1542 |
|
|
set startpoint [get_node_info -name [get_path_info $path -from]]
|
| 1543 |
|
|
if {[info exist min_DQS_to_fifo_paths_min($startpoint)]} {
|
| 1544 |
|
|
if {$arrival_time < $min_DQS_to_fifo_paths_min($startpoint)} {
|
| 1545 |
|
|
set min_DQS_to_fifo_paths_min($startpoint) $arrival_time
|
| 1546 |
|
|
}
|
| 1547 |
|
|
} else {
|
| 1548 |
|
|
set min_DQS_to_fifo_paths_min($startpoint) $arrival_time
|
| 1549 |
|
|
}
|
| 1550 |
|
|
}
|
| 1551 |
|
|
|
| 1552 |
|
|
|
| 1553 |
|
|
foreach_in_collection path $max_fifo_to_rd_clk_domain_paths {
|
| 1554 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1555 |
|
|
set endpoint [get_node_info -name [get_path_info $path -to]]
|
| 1556 |
|
|
if {[info exist max_fifo_to_rd_clk_domain_paths_max($endpoint)]} {
|
| 1557 |
|
|
if {$arrival_time > $max_fifo_to_rd_clk_domain_paths_max($endpoint)} {
|
| 1558 |
|
|
set max_fifo_to_rd_clk_domain_paths_max($endpoint) $arrival_time
|
| 1559 |
|
|
}
|
| 1560 |
|
|
} else {
|
| 1561 |
|
|
set max_fifo_to_rd_clk_domain_paths_max($endpoint) $arrival_time
|
| 1562 |
|
|
}
|
| 1563 |
|
|
}
|
| 1564 |
|
|
|
| 1565 |
|
|
foreach_in_collection path $min_fifo_to_rd_clk_domain_paths {
|
| 1566 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1567 |
|
|
set endpoint [get_node_info -name [get_path_info $path -to]]
|
| 1568 |
|
|
if {[info exist min_fifo_to_rd_clk_domain_paths_min($endpoint)]} {
|
| 1569 |
|
|
if {$arrival_time < $min_fifo_to_rd_clk_domain_paths_min($endpoint)} {
|
| 1570 |
|
|
set min_fifo_to_rd_clk_domain_paths_min($endpoint) $arrival_time
|
| 1571 |
|
|
}
|
| 1572 |
|
|
} else {
|
| 1573 |
|
|
set min_fifo_to_rd_clk_domain_paths_min($endpoint) $arrival_time
|
| 1574 |
|
|
}
|
| 1575 |
|
|
}
|
| 1576 |
|
|
|
| 1577 |
|
|
foreach_in_collection path $max_rd_address_to_rd_data_paths {
|
| 1578 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1579 |
|
|
set endpoint [get_node_info -name [get_path_info $path -to]]
|
| 1580 |
|
|
if {[info exist max_rd_address_to_rd_data_paths_max($endpoint)]} {
|
| 1581 |
|
|
if {$arrival_time > $max_rd_address_to_rd_data_paths_max($endpoint)} {
|
| 1582 |
|
|
set max_rd_address_to_rd_data_paths_max($endpoint) $arrival_time
|
| 1583 |
|
|
}
|
| 1584 |
|
|
} else {
|
| 1585 |
|
|
set max_rd_address_to_rd_data_paths_max($endpoint) $arrival_time
|
| 1586 |
|
|
}
|
| 1587 |
|
|
}
|
| 1588 |
|
|
|
| 1589 |
|
|
foreach_in_collection path $min_rd_address_to_rd_data_paths {
|
| 1590 |
|
|
set arrival_time [get_path_info $path -arrival_time]
|
| 1591 |
|
|
set endpoint [get_node_info -name [get_path_info $path -to]]
|
| 1592 |
|
|
if {[info exist min_rd_address_to_rd_data_paths_min($endpoint)]} {
|
| 1593 |
|
|
if {$arrival_time < $min_rd_address_to_rd_data_paths_min($endpoint)} {
|
| 1594 |
|
|
set min_rd_address_to_rd_data_paths_min($endpoint) $arrival_time
|
| 1595 |
|
|
}
|
| 1596 |
|
|
} else {
|
| 1597 |
|
|
set min_rd_address_to_rd_data_paths_min($endpoint) $arrival_time
|
| 1598 |
|
|
}
|
| 1599 |
|
|
}
|
| 1600 |
|
|
|
| 1601 |
|
|
#######################################
|
| 1602 |
|
|
# TCO times
|
| 1603 |
|
|
set i 0
|
| 1604 |
|
|
set tco_fifo_min 0
|
| 1605 |
|
|
set tco_fifo_max 0
|
| 1606 |
|
|
foreach_in_collection register [get_keepers $fifo] {
|
| 1607 |
|
|
set tcotemp [get_register_info $register -tco]
|
| 1608 |
|
|
if {$i == 0} {
|
| 1609 |
|
|
set tco_fifo_min $tcotemp
|
| 1610 |
|
|
set tco_fifo_max $tcotemp
|
| 1611 |
|
|
} else {
|
| 1612 |
|
|
if {$tcotemp < $tco_fifo_min} {
|
| 1613 |
|
|
set tco_fifo_min $tcotemp
|
| 1614 |
|
|
} elseif {$tcotemp > $tco_fifo_max} {
|
| 1615 |
|
|
set tco_fifo_max $tcotemp
|
| 1616 |
|
|
}
|
| 1617 |
|
|
}
|
| 1618 |
|
|
incr i
|
| 1619 |
|
|
}
|
| 1620 |
|
|
set i 0
|
| 1621 |
|
|
set tco_wr_address_min 0
|
| 1622 |
|
|
set tco_wr_address_max 0
|
| 1623 |
|
|
foreach_in_collection register [get_keepers $reg_wr_address] {
|
| 1624 |
|
|
set tcotemp [get_register_info $register -tco]
|
| 1625 |
|
|
if {$i == 0} {
|
| 1626 |
|
|
set tco_wr_address_min $tcotemp
|
| 1627 |
|
|
set tco_wr_address_max $tcotemp
|
| 1628 |
|
|
} else {
|
| 1629 |
|
|
if {$tcotemp < $tco_wr_address_min} {
|
| 1630 |
|
|
set tco_wr_address_min $tcotemp
|
| 1631 |
|
|
} elseif {$tcotemp > $tco_wr_address_max} {
|
| 1632 |
|
|
set tco_wr_addressmax $tcotemp
|
| 1633 |
|
|
}
|
| 1634 |
|
|
}
|
| 1635 |
|
|
incr i
|
| 1636 |
|
|
}
|
| 1637 |
|
|
|
| 1638 |
|
|
#######################################
|
| 1639 |
|
|
# Other parameters
|
| 1640 |
|
|
set entity_names_on [ hps_sdram_p0_are_entity_names_on ]
|
| 1641 |
|
|
set fly_by_wire 1.6
|
| 1642 |
|
|
set min_latency 1
|
| 1643 |
|
|
set max_latency 2
|
| 1644 |
|
|
if { ! $entity_names_on } {
|
| 1645 |
|
|
set fifo_depth [get_collection_size [get_keepers $inst*read_buffering[0].read_subgroup[0].uread_fifo|data_stored[*][0]]]
|
| 1646 |
|
|
} else {
|
| 1647 |
|
|
set fifo_depth [get_collection_size [get_keepers $prefix*read_buffering[0].read_subgroup[0].uread_fifo|data_stored[*][0]]]
|
| 1648 |
|
|
}
|
| 1649 |
|
|
if {($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
|
| 1650 |
|
|
# Reduce the effect of tDQSCK
|
| 1651 |
|
|
set mp_DQSCK [expr $MP(DQSCK)*$t(DQSCK)]
|
| 1652 |
|
|
} else {
|
| 1653 |
|
|
set mp_DQSCK 0
|
| 1654 |
|
|
}
|
| 1655 |
|
|
set hf_DQS_variation [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -in_fitter -period $period]/1000.0*2/2]
|
| 1656 |
|
|
set hf_DQS_variation [expr $hf_DQS_variation + $SSN(pushout_o) + $SSN(pullin_o) + 2*$t(DQSCK) - 2*$mp_DQSCK + $SSN(pullin_i)]
|
| 1657 |
|
|
set hf_DQS_variation [expr $hf_DQS_variation + [get_float_table_node_delay -src {DELAYCHAIN_T9} -dst {VTVARIATION} -parameters [list IO $interface_type]]*$max_dqs_common_to_fifo/2]
|
| 1658 |
|
|
|
| 1659 |
|
|
#######################################
|
| 1660 |
|
|
# Board parameters
|
| 1661 |
|
|
set board_skew [expr $board(inter_DQS_group_skew)/2.0]
|
| 1662 |
|
|
if {$IP(num_ranks) > 1} {
|
| 1663 |
|
|
set board_skew [expr $board_skew + $board(tpd_inter_DIMM)]
|
| 1664 |
|
|
}
|
| 1665 |
|
|
|
| 1666 |
|
|
#######################################
|
| 1667 |
|
|
# Body of Resync analysis
|
| 1668 |
|
|
# Go over each DQ pin
|
| 1669 |
|
|
|
| 1670 |
|
|
set total_setup_slack 10000000
|
| 1671 |
|
|
set total_hold_slack 10000000
|
| 1672 |
|
|
|
| 1673 |
|
|
set regs [get_keepers $reg_in_rd_clk_domain]
|
| 1674 |
|
|
|
| 1675 |
|
|
foreach_in_collection reg $regs {
|
| 1676 |
|
|
|
| 1677 |
|
|
set reg_name [get_register_info -name $reg]
|
| 1678 |
|
|
|
| 1679 |
|
|
if {[info exists max_rd_address_to_rd_data_paths_max($reg_name)]==0} {
|
| 1680 |
|
|
# not all registers have arcs for the hard read fifo, depending upon full/half rate
|
| 1681 |
|
|
continue
|
| 1682 |
|
|
}
|
| 1683 |
|
|
|
| 1684 |
|
|
regexp {read_buffering\[(\d+)\]\.read_subgroup} $reg_name match dqs_group_number
|
| 1685 |
|
|
|
| 1686 |
|
|
set dqs_pin [lindex $pins(dqs_pins) $dqs_group_number]
|
| 1687 |
|
|
if {!([info exists max_DQS_to_fifo_paths_max($dqs_pin)] &&
|
| 1688 |
|
|
[info exists min_DQS_to_fifo_paths_min($dqs_pin)] &&
|
| 1689 |
|
|
[info exists max_fifo_to_rd_clk_domain_paths_max($reg_name_fifo_data_rd_clk_domain)] &&
|
| 1690 |
|
|
[info exists min_fifo_to_rd_clk_domain_paths_min($reg_name_fifo_data_rd_clk_domain)] &&
|
| 1691 |
|
|
[info exists max_rd_address_to_rd_data_paths_max($reg_name)] &&
|
| 1692 |
|
|
[info exists min_rd_address_to_rd_data_paths_min($reg_name)])} {
|
| 1693 |
|
|
post_message -type error "Paths not found for resync analysis."
|
| 1694 |
|
|
return 1
|
| 1695 |
|
|
}
|
| 1696 |
|
|
set max_DQS_to_fifo $max_DQS_to_fifo_paths_max($dqs_pin)
|
| 1697 |
|
|
set min_DQS_to_fifo $min_DQS_to_fifo_paths_min($dqs_pin)
|
| 1698 |
|
|
set max_fifo_to_rd_clk_domain $max_fifo_to_rd_clk_domain_paths_max($reg_name)
|
| 1699 |
|
|
set min_fifo_to_rd_clk_domain $min_fifo_to_rd_clk_domain_paths_min($reg_name)
|
| 1700 |
|
|
set max_rd_address_to_rd_data $max_rd_address_to_rd_data_paths_max($reg_name)
|
| 1701 |
|
|
set min_rd_address_to_rd_data $min_rd_address_to_rd_data_paths_min($reg_name)
|
| 1702 |
|
|
|
| 1703 |
|
|
|
| 1704 |
|
|
###############
|
| 1705 |
|
|
# Setup analysis
|
| 1706 |
|
|
set setup_arrival_time [expr ($max_DQS_to_fifo - $min_DQS_to_fifo) + $tco_fifo_max + $max_fifo_to_rd_clk_domain]
|
| 1707 |
|
|
set setup_required_time [expr $min_latency*$period + $tco_wr_address_min + $min_rd_address_to_rd_data]
|
| 1708 |
|
|
set setup_slack [expr $setup_required_time - $setup_arrival_time - $board_skew]
|
| 1709 |
|
|
|
| 1710 |
|
|
###############
|
| 1711 |
|
|
# Hold analysis
|
| 1712 |
|
|
set hold_arrival_time [expr ($min_DQS_to_fifo - $max_DQS_to_fifo) + $tco_fifo_min + $min_fifo_to_rd_clk_domain + $fifo_depth*$period]
|
| 1713 |
|
|
set hold_required_time [expr $hf_DQS_variation + $max_rd_address_to_rd_data + $tco_wr_address_max + $max_latency*$period + $fly_by_wire]
|
| 1714 |
|
|
set hold_slack [expr -$hold_required_time + $hold_arrival_time - $board_skew]
|
| 1715 |
|
|
|
| 1716 |
|
|
if {$setup_slack < $total_setup_slack} {
|
| 1717 |
|
|
set total_setup_slack $setup_slack
|
| 1718 |
|
|
}
|
| 1719 |
|
|
|
| 1720 |
|
|
if {$hold_slack < $total_hold_slack} {
|
| 1721 |
|
|
set total_hold_slack $hold_slack
|
| 1722 |
|
|
}
|
| 1723 |
|
|
}
|
| 1724 |
|
|
|
| 1725 |
|
|
lappend summary [list $opcname 0 "Read Resync ($opcname)" $total_setup_slack $total_hold_slack]
|
| 1726 |
|
|
|
| 1727 |
|
|
}
|
| 1728 |
|
|
|
| 1729 |
|
|
#############################################################
|
| 1730 |
|
|
# Postamble Timing Analysis
|
| 1731 |
|
|
#############################################################
|
| 1732 |
|
|
|
| 1733 |
|
|
proc hps_sdram_p0_perform_flexible_postamble_timing_analysis {opcs opcname instname scale_factors_name family period dll_length interface_type tJITper tJITdty tDCD DQSpathjitter pin_array_name timing_parameters_array_name summary_name MP_name IP_name SSN_name board_name ISI_parameters_name} {
|
| 1734 |
|
|
|
| 1735 |
|
|
###############################################################################
|
| 1736 |
|
|
# The postamble analysis concerns gating the DQS signal within the device
|
| 1737 |
|
|
# in the allotated time before DQS goes tri-state, such that spurious data is not
|
| 1738 |
|
|
# registered if there is noise on DQS. Altera devices have dedicated register that
|
| 1739 |
|
|
# can be used to ground the DQS signal, and the timing analysis below considers
|
| 1740 |
|
|
# the timing margins for the clock that is used to reset that register.
|
| 1741 |
|
|
###############################################################################
|
| 1742 |
|
|
|
| 1743 |
|
|
|
| 1744 |
|
|
#######################################
|
| 1745 |
|
|
# Need access to global variables
|
| 1746 |
|
|
upvar 1 $summary_name summary
|
| 1747 |
|
|
upvar 1 $timing_parameters_array_name t
|
| 1748 |
|
|
upvar 1 $IP_name IP
|
| 1749 |
|
|
upvar 1 $pin_array_name pins
|
| 1750 |
|
|
upvar 1 $board_name board
|
| 1751 |
|
|
upvar 1 $MP_name MP
|
| 1752 |
|
|
upvar 1 $SSN_name SSN
|
| 1753 |
|
|
upvar 1 $ISI_parameters_name ISI
|
| 1754 |
|
|
upvar 1 $scale_factors_name scale_factors
|
| 1755 |
|
|
|
| 1756 |
|
|
# Ideal setup and hold slacks is half the postamble time (full clock cycle)
|
| 1757 |
|
|
set setup_slack [expr 0.5*$t(CK)]
|
| 1758 |
|
|
set hold_slack [expr 0.5*$t(CK)]
|
| 1759 |
|
|
|
| 1760 |
|
|
###############################
|
| 1761 |
|
|
# Memory Parameters
|
| 1762 |
|
|
###############################
|
| 1763 |
|
|
|
| 1764 |
|
|
# Remove the variation in the clock coming back from the memory
|
| 1765 |
|
|
set tDQSCK $t(DQSCK)
|
| 1766 |
|
|
if {($IP(mp_calibration) == 1) && ($IP(num_ranks) == 1)} {
|
| 1767 |
|
|
if {$IP(tracking_enabled) == 1} {
|
| 1768 |
|
|
set tDQSCK [expr (1.0-($MP(DQSCK)+$MP(DQSCK_T)))*$tDQSCK]
|
| 1769 |
|
|
} else {
|
| 1770 |
|
|
set tDQSCK [expr (1.0-$MP(DQSCK))*$tDQSCK]
|
| 1771 |
|
|
}
|
| 1772 |
|
|
} elseif {$IP(mp_calibration) == 1} {
|
| 1773 |
|
|
set tDQSCK [expr (1.0-$MP(DQSCK)/2.5)*$tDQSCK]
|
| 1774 |
|
|
}
|
| 1775 |
|
|
|
| 1776 |
|
|
set setup_slack [expr $setup_slack - $tDQSCK]
|
| 1777 |
|
|
set hold_slack [expr $hold_slack - $tDQSCK]
|
| 1778 |
|
|
|
| 1779 |
|
|
##############################
|
| 1780 |
|
|
# Jitter/SSN Effects
|
| 1781 |
|
|
##############################
|
| 1782 |
|
|
|
| 1783 |
|
|
# Remove the jitter on the clock out to the memory, and the DQS enable clock
|
| 1784 |
|
|
set setup_slack [expr $setup_slack - $tJITper/2 - $tJITper/2]
|
| 1785 |
|
|
set hold_slack [expr $hold_slack - $tJITper/2 - $tJITper/2]
|
| 1786 |
|
|
|
| 1787 |
|
|
# Remove the jitter on the DQS path
|
| 1788 |
|
|
set setup_slack [expr $setup_slack - $DQSpathjitter/2]
|
| 1789 |
|
|
set hold_slack [expr $hold_slack - $DQSpathjitter/2]
|
| 1790 |
|
|
|
| 1791 |
|
|
# Remove SSN effects
|
| 1792 |
|
|
if {$IP(tracking_enabled) == 1} {
|
| 1793 |
|
|
set total_ssn [expr $SSN(pushout_o) + $SSN(pushout_i) + $SSN(pullin_o) + $SSN(pullin_i)]
|
| 1794 |
|
|
set setup_slack [expr $setup_slack - $total_ssn/2]
|
| 1795 |
|
|
set hold_slack [expr $hold_slack - $total_ssn/2]
|
| 1796 |
|
|
} else {
|
| 1797 |
|
|
set setup_slack [expr $setup_slack - $SSN(pushout_o) - $SSN(pushout_i)]
|
| 1798 |
|
|
set hold_slack [expr $hold_slack - $SSN(pullin_o) - $SSN(pullin_i)]
|
| 1799 |
|
|
}
|
| 1800 |
|
|
|
| 1801 |
|
|
##############################
|
| 1802 |
|
|
# VT/Aging effects
|
| 1803 |
|
|
##############################
|
| 1804 |
|
|
|
| 1805 |
|
|
set coarse_delay [expr $t(CK)/$dll_length]
|
| 1806 |
|
|
set dqsenableextend_regs [list *dq_ddio[*].ubidir_dq_dqs|*|dqs_enable_ctrl~DFFEXTENDDQSENABLE *dq_ddio[*].ubidir_dq_dqs|*|dqs_enable_ctrl~DQSENABLEOUT_DFF]
|
| 1807 |
|
|
if {$family == "arria v"} {
|
| 1808 |
|
|
set hps_compensation [expr 0.250 - [hps_sdram_p0_max_in_collection [get_path -rise_to ${instname}|pll|pll|clk_out[0]] "arrival_time"]]
|
| 1809 |
|
|
} else {
|
| 1810 |
|
|
set hps_compensation [expr 0.350 - [hps_sdram_p0_max_in_collection [get_path -rise_to ${instname}|pll|pll|clk_out[0]] "arrival_time"]]
|
| 1811 |
|
|
}
|
| 1812 |
|
|
# Clock out to DQS path coming back into the FPGA
|
| 1813 |
|
|
set mem_clock_delay_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $pins(ck_pins)] "arrival_time"]
|
| 1814 |
|
|
set mem_clock_delay_min [hps_sdram_p0_min_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $pins(ck_pins) -min_path] "arrival_time"]
|
| 1815 |
|
|
|
| 1816 |
|
|
set mem_clock_delay_max [expr $mem_clock_delay_max + $hps_compensation]
|
| 1817 |
|
|
|
| 1818 |
|
|
set dqs_delay_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pins(dqs_pins) -fall_to *POSTAMBLE_DFF] "arrival_time"]
|
| 1819 |
|
|
set dqs_delay_min [hps_sdram_p0_min_in_collection [get_path -rise_from $pins(dqs_pins) -fall_to *POSTAMBLE_DFF -min_path] "arrival_time"]
|
| 1820 |
|
|
set ck_pin_buffer_delay [hps_sdram_p0_round_3dp [expr [hps_sdram_p0_get_min_aiot_delay [lindex $pins(ck_pins) 0]] * 1e9]]
|
| 1821 |
|
|
|
| 1822 |
|
|
set return_path_delay_max [expr $mem_clock_delay_max + $dqs_delay_max - ($ck_pin_buffer_delay*1.55)]
|
| 1823 |
|
|
set return_path_delay_min [expr $mem_clock_delay_min + $dqs_delay_min - ($ck_pin_buffer_delay*1.55)]
|
| 1824 |
|
|
|
| 1825 |
|
|
# DQS Enable clk to DQS Enable register
|
| 1826 |
|
|
set clock_delay_max [hps_sdram_p0_max_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $dqsenableextend_regs] "arrival_time"]
|
| 1827 |
|
|
set clock_delay_min [hps_sdram_p0_min_in_collection [get_path -rise_from $pins(pll_write_clock) -rise_to $dqsenableextend_regs -min_path] "arrival_time"]
|
| 1828 |
|
|
set clock_delay_max [expr $clock_delay_max + $hps_compensation]
|
| 1829 |
|
|
set t11_delay_max [hps_sdram_p0_max_in_collection [get_path -rise_from $dqsenableextend_regs -fall_to *POSTAMBLE_DFF] "arrival_time"]
|
| 1830 |
|
|
set t11_delay_min [hps_sdram_p0_min_in_collection [get_path -rise_from $dqsenableextend_regs -fall_to *POSTAMBLE_DFF -min_path] "arrival_time"]
|
| 1831 |
|
|
|
| 1832 |
|
|
set t11_setting_delay_max_base [expr [get_integer_node_delay -integer 0 -parameters {DQS_ENABLE RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0]
|
| 1833 |
|
|
set t11_setting_delay_max [expr [get_integer_node_delay -integer 15 -parameters {DQS_ENABLE RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0]
|
| 1834 |
|
|
set t11_setting_delay_max [expr {$t11_setting_delay_max - $t11_setting_delay_max_base}]
|
| 1835 |
|
|
set t11_setting_delay_min_base [expr [get_integer_node_delay -integer 0 -parameters {DQS_ENABLE MIN RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0]
|
| 1836 |
|
|
set t11_setting_delay_min [expr [get_integer_node_delay -integer 15 -parameters {DQS_ENABLE MIN RC_RISE RC_RISE} -src DELAYCHAIN_T11 -in_fitter]/1000.0]
|
| 1837 |
|
|
set t11_setting_delay_min [expr {$t11_setting_delay_min - $t11_setting_delay_min_base}]
|
| 1838 |
|
|
|
| 1839 |
|
|
set dqs_enable_signal_delay_max [expr $clock_delay_max + $t11_delay_max + $t11_setting_delay_max]
|
| 1840 |
|
|
set dqs_enable_signal_delay_min [expr $clock_delay_min + $t11_delay_min + $t11_setting_delay_min]
|
| 1841 |
|
|
|
| 1842 |
|
|
if {($mem_clock_delay_max == 0) || ($clock_delay_max == 0) || ($dqs_delay_max == 0)} {
|
| 1843 |
|
|
lappend summary [list $opcname 0 "Postamble ($opcname)" -1.999 -1.999]
|
| 1844 |
|
|
return
|
| 1845 |
|
|
}
|
| 1846 |
|
|
|
| 1847 |
|
|
# Determine the worst-case difference between the two paths
|
| 1848 |
|
|
set t11_delay_difference 0
|
| 1849 |
|
|
set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_min - $dqs_enable_signal_delay_min)}]]
|
| 1850 |
|
|
set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_min - $dqs_enable_signal_delay_max)}]]
|
| 1851 |
|
|
set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_max - $dqs_enable_signal_delay_min)}]]
|
| 1852 |
|
|
set t11_delay_difference [max $t11_delay_difference [expr {abs($return_path_delay_max - $dqs_enable_signal_delay_max)}]]
|
| 1853 |
|
|
if {$t11_delay_difference < 0} {
|
| 1854 |
|
|
# If the DQS Enable path is longer, then any T11 setting picked for centering will make the delay mismatch worse
|
| 1855 |
|
|
set t11_delay_difference [expr {abs($t11_delay_difference) + $coarse_delay}]
|
| 1856 |
|
|
}
|
| 1857 |
|
|
|
| 1858 |
|
|
# Determine worst-case V or VT variation as a % of delay
|
| 1859 |
|
|
set lf_vt_drift_derating 0.75
|
| 1860 |
|
|
if {$IP(tracking_enabled) == 1} {
|
| 1861 |
|
|
# Just V variation
|
| 1862 |
|
|
set vt_variation_percent [expr 2*[get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]]]
|
| 1863 |
|
|
} else {
|
| 1864 |
|
|
# Both V and T variation
|
| 1865 |
|
|
#TODO, get T variation
|
| 1866 |
|
|
set vt_variation_percent [expr 0.10 + 2*[get_float_table_node_delay -src {DELAYCHAIN_DUTY_CYCLE} -dst {VTVARIATION} -parameters [list IO $interface_type]]]
|
| 1867 |
|
|
}
|
| 1868 |
|
|
|
| 1869 |
|
|
# Determine aging variation as a % of delay
|
| 1870 |
|
|
set age_variation_derating 0.7
|
| 1871 |
|
|
set age_variation_percent [expr $scale_factors(eol)/$IP(eol_reduction_factor_write)]
|
| 1872 |
|
|
|
| 1873 |
|
|
# Determine total on-chip variation
|
| 1874 |
|
|
set delay_variation_percent [expr 2*$vt_variation_percent*$lf_vt_drift_derating + $age_variation_derating*$age_variation_percent]
|
| 1875 |
|
|
set delay_variation [expr $t11_delay_difference*$delay_variation_percent]
|
| 1876 |
|
|
|
| 1877 |
|
|
set setup_slack [expr $setup_slack - $delay_variation/2]
|
| 1878 |
|
|
set hold_slack [expr $hold_slack - $delay_variation/2]
|
| 1879 |
|
|
|
| 1880 |
|
|
# Voltage variation across matched clocks (this is not included above because the matched clock paths are subtracted out)
|
| 1881 |
|
|
#Below values for delay miscorrelation matched paths are obtained from the FLS
|
| 1882 |
|
|
set delay_miscorrelation_matched_paths_just_v 0.014
|
| 1883 |
|
|
set delay_miscorrelation_matched_paths 0.02
|
| 1884 |
|
|
set matched_path_voltage_variation [expr $clock_delay_max*$delay_miscorrelation_matched_paths_just_v*2]
|
| 1885 |
|
|
set setup_slack [expr $setup_slack - $matched_path_voltage_variation/2]
|
| 1886 |
|
|
set hold_slack [expr $hold_slack - $matched_path_voltage_variation/2]
|
| 1887 |
|
|
|
| 1888 |
|
|
# DCD effects
|
| 1889 |
|
|
#1.25 is the period @ 800MHz
|
| 1890 |
|
|
set dcd_effect [expr 1.25*$tDCD*2]
|
| 1891 |
|
|
set setup_slack [expr $setup_slack - $dcd_effect/2]
|
| 1892 |
|
|
set hold_slack [expr $hold_slack - $dcd_effect/2]
|
| 1893 |
|
|
|
| 1894 |
|
|
##############################
|
| 1895 |
|
|
# PVT compensated tracking uncertainties
|
| 1896 |
|
|
##############################
|
| 1897 |
|
|
|
| 1898 |
|
|
set dll_update_latency 9000.0
|
| 1899 |
|
|
set hf_rate_of_change 0.00001029
|
| 1900 |
|
|
set ldc_tracking_error_percent [min $vt_variation_percent [expr $dll_update_latency*$hf_rate_of_change]]
|
| 1901 |
|
|
set ldc_tracking_error [expr 2*$t(CK)*3/$dll_length*$ldc_tracking_error_percent]
|
| 1902 |
|
|
set ldc_absolute_error [expr 2*$IP(quantization_WL)*3+2*$t(CK)*0.375*$delay_miscorrelation_matched_paths]
|
| 1903 |
|
|
|
| 1904 |
|
|
set setup_slack [expr $setup_slack - $ldc_tracking_error/2 - $ldc_absolute_error/2]
|
| 1905 |
|
|
set hold_slack [expr $hold_slack - $ldc_tracking_error/2 - $ldc_absolute_error/2]
|
| 1906 |
|
|
|
| 1907 |
|
|
|
| 1908 |
|
|
##############################
|
| 1909 |
|
|
# Quantization error
|
| 1910 |
|
|
##############################
|
| 1911 |
|
|
|
| 1912 |
|
|
set quantization_step [expr 2*$IP(quantization_T11)*1.5]
|
| 1913 |
|
|
set setup_slack [expr $setup_slack - $quantization_step/2]
|
| 1914 |
|
|
set hold_slack [expr $hold_slack - $quantization_step/2]
|
| 1915 |
|
|
|
| 1916 |
|
|
##############################
|
| 1917 |
|
|
# Tracking algorithm uncertainties
|
| 1918 |
|
|
##############################
|
| 1919 |
|
|
|
| 1920 |
|
|
if {$IP(tracking_enabled) == 1} {
|
| 1921 |
|
|
set mistake_tracking_jitter [expr 0.025*(2*$tDQSCK + 2*$tJITper + $total_ssn + $delay_variation + $quantization_step + $ldc_tracking_error + $matched_path_voltage_variation)]
|
| 1922 |
|
|
set setup_slack [expr $setup_slack - $mistake_tracking_jitter/2]
|
| 1923 |
|
|
set hold_slack [expr $hold_slack - $mistake_tracking_jitter/2]
|
| 1924 |
|
|
}
|
| 1925 |
|
|
|
| 1926 |
|
|
##############################
|
| 1927 |
|
|
# Multirank effects
|
| 1928 |
|
|
##############################
|
| 1929 |
|
|
|
| 1930 |
|
|
|
| 1931 |
|
|
# Remove Multirank board skew effects - Calibration will calibrate to the average of multiple ranks
|
| 1932 |
|
|
if {$IP(num_ranks) > 1} {
|
| 1933 |
|
|
set setup_slack [expr $setup_slack - $board(tpd_inter_DIMM)]
|
| 1934 |
|
|
set hold_slack [expr $hold_slack - $board(tpd_inter_DIMM)]
|
| 1935 |
|
|
}
|
| 1936 |
|
|
|
| 1937 |
|
|
lappend summary [list $opcname 0 "Postamble ($opcname)" $setup_slack $hold_slack]
|
| 1938 |
|
|
}
|
| 1939 |
|
|
|
