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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_reset.v] - Blame information for rev 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other 
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// software and tools, and its AMPP partner logic functions, and any output 
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// files from any of the foregoing (including device programming or simulation 
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// files), and any associated documentation or information are expressly subject 
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// to the terms and conditions of the Intel Program License Subscription 
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// Agreement, Intel FPGA IP License Agreement, or other applicable 
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// license agreement, including, without limitation, that your use is for the 
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// sole purpose of programming logic devices manufactured by Intel and sold by 
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// Intel or its authorized distributors.  Please refer to the applicable 
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// agreement for further details.
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
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module hps_sdram_p0_reset(
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        seq_reset_mem_stable,
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        pll_afi_clk,
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        pll_addr_cmd_clk,
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        pll_dqs_ena_clk,
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        seq_clk,
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        scc_clk,
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        pll_avl_clk,
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        reset_n_scc_clk,
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        reset_n_avl_clk,
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        read_capture_clk,
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        pll_locked,
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        global_reset_n,
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        soft_reset_n,
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        ctl_reset_n,
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        ctl_reset_export_n,
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        reset_n_afi_clk,
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        reset_n_addr_cmd_clk,
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        reset_n_resync_clk,
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        reset_n_seq_clk,
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        reset_n_read_capture_clk
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);
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parameter MEM_READ_DQS_WIDTH = "";
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parameter NUM_AFI_RESET = 1;
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input   seq_reset_mem_stable;
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input   pll_afi_clk;
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input   pll_addr_cmd_clk;
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input   pll_dqs_ena_clk;
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input   seq_clk;
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input   scc_clk;
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input   pll_avl_clk;
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output  reset_n_scc_clk;
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output  reset_n_avl_clk;
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input   [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
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input   pll_locked;
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input   global_reset_n;
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input   soft_reset_n;
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output  ctl_reset_n;
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output  ctl_reset_export_n;
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output  [NUM_AFI_RESET-1:0] reset_n_afi_clk;
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output  reset_n_addr_cmd_clk;
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output  reset_n_resync_clk;
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output  reset_n_seq_clk;
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output  [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
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// Apply the synthesis keep attribute on the synchronized reset wires
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// so that these names can be constrained using QSF settings to keep
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// the resets on local routing.
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wire    phy_reset_n /* synthesis keep = 1 */;
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wire    phy_reset_mem_stable_n /* synthesis keep = 1*/;
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wire    [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
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        assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
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        assign reset_n_read_capture_clk = reset_n_read_capture;
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        assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
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        hps_sdram_p0_reset_sync ureset_afi_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (pll_afi_clk),
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                .reset_n_sync   (reset_n_afi_clk)
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        );
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        defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
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        hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (pll_afi_clk),
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                .reset_n_sync   ({ctl_reset_n, ctl_reset_export_n})
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        );
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        defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
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        hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
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                .reset_n                        (phy_reset_n),
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                .clk                            (pll_addr_cmd_clk),
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                .reset_n_sync   (reset_n_addr_cmd_clk)
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        );
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        defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
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        hps_sdram_p0_reset_sync ureset_resync_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (pll_dqs_ena_clk),
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                .reset_n_sync   (reset_n_resync_clk)
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        );
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        defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
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        hps_sdram_p0_reset_sync ureset_seq_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (seq_clk),
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                .reset_n_sync   (reset_n_seq_clk)
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        );
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        defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
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        hps_sdram_p0_reset_sync ureset_scc_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (scc_clk),
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                .reset_n_sync   (reset_n_scc_clk)
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        );
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        defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
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        defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
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        hps_sdram_p0_reset_sync ureset_avl_clk(
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                .reset_n                (phy_reset_n),
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                .clk                    (pll_avl_clk),
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                .reset_n_sync   (reset_n_avl_clk)
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        );
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        defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
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        defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
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generate
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genvar i;
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        for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
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        begin: read_capture_reset
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                hps_sdram_p0_reset_sync #(
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                        .RESET_SYNC_STAGES(15),
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                        .NUM_RESET_OUTPUT(1)
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                 )
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                ureset_read_capture_clk(
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                        .reset_n                        (phy_reset_mem_stable_n),
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                        .clk                            (read_capture_clk[i]),
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                        .reset_n_sync   (reset_n_read_capture[i])
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                );
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        end
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endgenerate
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endmodule

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