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#ifndef TCLRPT_H_
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#define TCLRPT_H_
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/*
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sequencer.h"
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#if ENABLE_TCL_DEBUG
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#define TCLRPT_SET(item, value) item = value
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#else
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#define TCLRPT_SET(item, value)
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#endif
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// None of the rest of the file should be referenced if ENABLE_TCL_DEBUG is not
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// set (although it's not a problem if it is, but this helps catch errors)
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#if ENABLE_TCL_DEBUG
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#define PRINTF_READ_BUFFER_SIZE 128/4
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#define PRINTF_READ_BUFFER_FIFO_WORDS 32
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#define NUM_DI_SAMPLE 100
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#define DI_REPORT_FLAGS_READY 0x00000001
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#define DI_REPORT_FLAGS_DONE 0x00000002
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//*****************************************************************************
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// TCL Commands
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//*****************************************************************************
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// The wait command
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#define TCLDBG_CMD_WAIT_CMD 1000
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// No operation command
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#define TCLDBG_CMD_NOP 0
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// Command response acknowledged
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#define TCLDBG_CMD_RESPONSE_ACK 1
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// Run the full test
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#define TCLDBG_RUN_FULLTEST 2
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// Query the parameterization info
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#define TCLDBG_PARAM_INFO 3
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// Query the status of calibration
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#define TCLDBG_CAL_STATUS 4
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// Run memory calibration
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#define TCLDBG_RUN_MEM_CALIBRATE 5
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// Run pattern to generate eye diagrams
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#define TCLDBG_RUN_EYE_DIAGRAM_PATTERN 6
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// Run full test and see how far we can push DQ delay on input and output sides
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#define TCLDBG_FIND_FULL_TEST_DQ 7
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// Run full test and see how far we can push DQS delay on input and output sides
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#define TCLDBG_FIND_FULL_TEST_DQS 8
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// Run full test and see how far we can push DM delay on output sides
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#define TCLDBG_FIND_FULL_TEST_DM 9
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// Query the margins found during read and write calibration
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#define TCLDBG_QUERY_CALIB_MARGINS 10
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// Query the settings applied during calibration on DQ pins
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#define TCLDBG_QUERY_DQ_SETTINGS 11
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// Query the settings applied during calibration on DQS groups
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#define TCLDBG_QUERY_DQS_SETTINGS 12
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// Query the state of the PHY. User mode or debug mode
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#define TCLDBG_QUERY_PHY_USER_DEBUG_MODE 13
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// Mark all groups as being valid for calibration
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#define TCLDBG_MARK_ALL_DQS_GROUPS_AS_VALID 14
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// Mark a specific group to be skipped for calibration
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#define TCLDBG_MARK_GROUP_AS_SKIP 15
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// Query the DQS skip group mask
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#define TCLDBG_QUERY_GROUP_AS_SKIP 16
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// Mark all ranks as being valid for calibration
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#define TCLDBG_MARK_ALL_RANKS_AS_VALID 17
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// Mark a specific rank to be skipped for calibration
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#define TCLDBG_MARK_RANK_AS_SKIP 18
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// Query the rank skip mask
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#define TCLDBG_QUERY_RANK_AS_SKIP 19
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// Query the settings applied during calibration on DM pins
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#define TCLDBG_QUERY_DM_SETTINGS 20
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// Enable the margining report as part of calibration
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#define TCLDBG_ENABLE_MARGIN_REPORT 21
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// Enable sweeping all groups of calibration
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#define TCLDBG_ENABLE_SWEEP_ALL_GROUPS 22
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// Enable the guaranteed read test as part of calibration
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#define TCLDBG_DISABLE_GUARANTEED_READ 23
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// Enable/disable non-destructive calibration
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#define TCLDBG_SET_NON_DESTRUCTIVE_CALIBRATION 24
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#if ENABLE_DELAY_CHAIN_WRITE
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// Set DQ D1 Delay (I/O buffer to input register)
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#define TCLDBG_SET_DQ_D1_DELAY 25
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// Set DQ D5 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DQ_D5_DELAY 26
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// Set DQ D6 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DQ_D6_DELAY 27
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// Set DQS D4 Delay (DQS delay chain)
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#define TCLDBG_SET_DQS_D4_DELAY 28
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// Set DQS DQ Output Phase (deg)
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#define TCLDBG_SET_DQDQS_OUTPUT_PHASE 29
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// Set DQS D5 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DQS_D5_DELAY 30
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// Set DQS D6 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DQS_D6_DELAY 31
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// Set DQS DQS Enable Phase (deg)
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#define TCLDBG_SET_DQS_EN_PHASE 32
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// Set DQS T11 Delay (DQS post-amble delay)
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#define TCLDBG_SET_DQS_T11_DELAY 33
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// Set DM D5 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DM_D5_DELAY 34
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// Set DM D6 Delay (output register to I/O buffer)
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#define TCLDBG_SET_DM_D6_DELAY 35
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// Rerun DQ margining without calibrating
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#define TCLDBG_REMARGIN_DQ 36
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// Rerun DM margining without calibrating
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#define TCLDBG_REMARGIN_DM 37
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// Increment VFIFO
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#define TCLDBG_INCR_VFIFO 38
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// Decrement VFIFO
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#define TCLDBG_DECR_VFIFO 39
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// Select shadow register
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#define TCLDBG_SELECT_SHADOW_REG 40
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#endif // ENABLE_DELAY_CHAIN_WRITE
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// Update RDIMM Control Word
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#define TCLDBG_SET_UPDATE_PARAMETERS 41
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// Run memory calibration
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#define TCLDBG_RUN_NON_DES_MEM_CALIBRATE 42
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//*****************************************************************************
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// TCL RX Status Codes
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//*****************************************************************************
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// RX interface waiting for command
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#define TCLDBG_RX_STATUS_WAIT_CMD 0
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// RX interface command ready for operation.
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#define TCLDBG_RX_STATUS_CMD_READY 1
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// RX interface command executing
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#define TCLDBG_RX_STATUS_CMD_EXE 2
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//*****************************************************************************
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// TCL TX Status Codes
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//*****************************************************************************
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// RX interface ready to accept commands in debug mode
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#define TCLDBG_TX_STATUS_CMD_READY 0
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// TX interface response not ready as command is running
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#define TCLDBG_TX_STATUS_CMD_EXE 1
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// RX interface illegal command
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#define TCLDBG_TX_STATUS_ILLEGAL_CMD 2
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// TX interface response ready
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#define TCLDBG_TX_STATUS_RESPONSE_READY 3
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//*****************************************************************************
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// Main report status bits
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//*****************************************************************************
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#define DEBUG_STATUS_PRINTF_ENABLED_BIT 0
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#define DEBUG_STATUS_CALIBRATION_STARTED 1
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#define DEBUG_STATUS_CALIBRATION_ENDED 2
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//*****************************************************************************
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// Individual reports status bits
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//*****************************************************************************
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#define DEBUG_REPORT_STATUS_REPORT_READY 0x00000001
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#define DEBUG_REPORT_STATUS_REPORT_GEN_ENABLED 0x00000002
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#define DEBUG_REPORT_DTAP_PER_PTAP_DYNAMIC 0x00000004
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//*****************************************************************************
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// Debug report sizes
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//*****************************************************************************
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#define NUM_RANK_MASK_WORDS ((RW_MGR_MEM_NUMBER_OF_RANKS % 32) == 0 ? (RW_MGR_MEM_NUMBER_OF_RANKS/32) : (RW_MGR_MEM_NUMBER_OF_RANKS/32)+1)
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#define NUM_GROUP_MASK_WORDS ((RW_MGR_MEM_IF_READ_DQS_WIDTH % 32) == 0 ? (RW_MGR_MEM_IF_READ_DQS_WIDTH/32) : (RW_MGR_MEM_IF_READ_DQS_WIDTH/32)+1)
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#define COMMAND_PARAM_WORDS 4
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//*****************************************************************************
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// Debug report structs
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// Margins are reported in terms of delay chain taps.
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//*****************************************************************************
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typedef struct debug_cal_observed_dq_margins_struct {
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alt_32 left_edge;
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alt_32 right_edge;
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} debug_cal_observed_dq_margins_t;
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typedef struct debug_cal_observed_dqs_in_margins_struct {
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alt_32 dq_margin;
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alt_32 dqs_margin;
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alt_u32 dqsen_margin;
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} debug_cal_observed_dqs_in_margins_t;
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typedef struct debug_cal_observed_dqsen_margins_struct {
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alt_u32 vfifo_begin;
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alt_u32 phase_begin;
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alt_u32 delay_begin;
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alt_u32 work_begin;
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alt_u32 vfifo_end;
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alt_u32 phase_end;
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alt_u32 delay_end;
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alt_u32 work_end;
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} debug_cal_observed_dqsen_margins_t;
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typedef struct debug_cal_observed_dqs_out_margins_struct {
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alt_32 dq_margin;
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alt_32 dqs_margin;
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alt_32 dm_margin;
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alt_u32 dqdqs_start;
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alt_u32 dqdqs_end;
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} debug_cal_observed_dqs_out_margins_t;
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typedef struct debug_cal_dq_settings_struct {
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alt_u32 dq_in_delay;
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alt_u32 dq_out_delay1;
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alt_u32 dq_out_delay2;
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} debug_cal_dq_settings_t;
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typedef struct debug_cal_dqs_in_settings_struct {
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alt_u32 dqs_bus_in_delay;
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alt_u32 dqs_en_phase;
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alt_u32 dqs_en_delay;
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#if TRACKING_ERROR_TEST || TRACKING_WATCH_TEST
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alt_u32 sample_count;
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alt_u32 dtaps_per_ptap;
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#endif
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} debug_cal_dqs_in_settings_t;
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typedef struct debug_cal_dqs_out_settings_struct {
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alt_u32 dqdqs_out_phase;
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alt_u32 dqs_out_delay1;
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alt_u32 dqs_out_delay2;
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alt_u32 oct_out_delay1;
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alt_u32 oct_out_delay2;
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alt_u32 dqs_io_in_delay;
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} debug_cal_dqs_out_settings_t;
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typedef struct debug_cal_dm_settings_struct {
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alt_u32 dm_in_delay;
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alt_u32 dm_out_delay1;
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alt_u32 dm_out_delay2;
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} debug_cal_dm_settings_t;
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/* Error stages are defined in sequencer.h */
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typedef struct debug_cal_status_per_group_struct {
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alt_u32 error_stage;
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alt_u32 error_sub_stage;
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alt_u32 fom_in;
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alt_u32 fom_out;
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} debug_cal_status_per_group_t;
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/* Summary report */
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typedef struct debug_summary_report_struct {
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// Size in 32-bit words of the report
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alt_u32 data_size;
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alt_u32 report_flags;
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alt_u32 sequencer_signature;
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alt_u32 protocol;
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alt_u32 error_stage;
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alt_u32 error_sub_stage;
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alt_u32 error_group;
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alt_u32 fom_in;
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alt_u32 fom_out;
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alt_u32 mem_address_width;
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alt_u32 mem_bank_width;
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alt_u32 mem_control_width;
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alt_u32 mem_cs_width;
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alt_u32 mem_cke_width;
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alt_u32 mem_odt_width;
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alt_u32 mem_data_width;
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alt_u32 mem_dm_width;
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alt_u32 mem_read_dqs_width;
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alt_u32 mem_write_dqs_width;
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alt_u32 mem_dq_per_read_dqs;
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alt_u32 mem_num_ranks;
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alt_u32 num_shadow_regs;
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alt_u32 mem_mmr_burst_len;
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alt_u32 mem_mmr_cas;
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348 |
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alt_u32 mem_num_dm_per_write_group;
|
349 |
|
|
|
350 |
|
|
alt_u32 rate;
|
351 |
|
|
|
352 |
|
|
alt_u32 cal_write_latency;
|
353 |
|
|
alt_u32 cal_read_latency;
|
354 |
|
|
|
355 |
|
|
alt_u32 dll_length;
|
356 |
|
|
|
357 |
|
|
alt_u32 rank_mask_size;
|
358 |
|
|
alt_u32 active_ranks;
|
359 |
|
|
alt_u32 rank_mask[NUM_RANK_MASK_WORDS];
|
360 |
|
|
|
361 |
|
|
alt_u32 group_mask_size;
|
362 |
|
|
alt_u32 active_groups;
|
363 |
|
|
alt_u32 group_mask[NUM_GROUP_MASK_WORDS];
|
364 |
|
|
|
365 |
|
|
alt_u32 groups_attempted_calibration[NUM_GROUP_MASK_WORDS];
|
366 |
|
|
|
367 |
|
|
alt_u32 computed_dtap_per_ptap;
|
368 |
|
|
// The delay per phase tap is the period/dll_length
|
369 |
|
|
alt_u32 io_delay_per_opa_tap;
|
370 |
|
|
// The delay per delay tap is the delay per phase tap
|
371 |
|
|
// divided by the number of delay taps per phase tap
|
372 |
|
|
// (i.e. io_delay_per_opa_tap / computed_dtap_per_ptap)
|
373 |
|
|
// The value of computed_dtap_per_ptap is computed during calibration.
|
374 |
|
|
|
375 |
|
|
alt_u32 margin_dq_in_left_delay_chain_len;
|
376 |
|
|
alt_u32 margin_dq_in_right_delay_chain_len;
|
377 |
|
|
alt_u32 margin_dq_out_left_delay_chain_len;
|
378 |
|
|
alt_u32 margin_dq_out_right_delay_chain_len;
|
379 |
|
|
|
380 |
|
|
} debug_summary_report_t;
|
381 |
|
|
|
382 |
|
|
/* Calibration report: The calibration status per group is here (cal_status_per_group)*/
|
383 |
|
|
typedef struct debug_cal_report_struct {
|
384 |
|
|
// Size in 32-bit words of the report
|
385 |
|
|
alt_u32 data_size;
|
386 |
|
|
|
387 |
|
|
alt_u32 report_flags;
|
388 |
|
|
|
389 |
|
|
alt_u32 mem_data_width;
|
390 |
|
|
alt_u32 mem_dm_width;
|
391 |
|
|
alt_u32 mem_num_dm_per_write_group;
|
392 |
|
|
alt_u32 mem_read_dqs_width;
|
393 |
|
|
alt_u32 mem_write_dqs_width;
|
394 |
|
|
|
395 |
|
|
alt_u32 num_shadow_regs;
|
396 |
|
|
|
397 |
|
|
/* Pass/fail status per group */
|
398 |
|
|
debug_cal_status_per_group_t cal_status_per_group[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
|
399 |
|
|
|
400 |
|
|
/* Margins observed before calibration. */
|
401 |
|
|
debug_cal_observed_dq_margins_t cal_dq_in_margins[NUM_SHADOW_REGS][RW_MGR_MEM_DATA_WIDTH];
|
402 |
|
|
debug_cal_observed_dq_margins_t cal_dq_out_margins[NUM_SHADOW_REGS][RW_MGR_MEM_DATA_WIDTH];
|
403 |
|
|
debug_cal_observed_dq_margins_t cal_dm_margins[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP];
|
404 |
|
|
debug_cal_observed_dqsen_margins_t cal_dqsen_margins[NUM_SHADOW_REGS][RW_MGR_MEM_IF_READ_DQS_WIDTH];
|
405 |
|
|
|
406 |
|
|
debug_cal_observed_dqs_in_margins_t cal_dqs_in_margins[NUM_SHADOW_REGS][RW_MGR_MEM_IF_READ_DQS_WIDTH];
|
407 |
|
|
debug_cal_observed_dqs_out_margins_t cal_dqs_out_margins[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
|
408 |
|
|
|
409 |
|
|
/* Phase, delay chain settings */
|
410 |
|
|
debug_cal_dq_settings_t cal_dq_settings[NUM_SHADOW_REGS][RW_MGR_MEM_DATA_WIDTH];
|
411 |
|
|
debug_cal_dqs_in_settings_t cal_dqs_in_settings[NUM_SHADOW_REGS][RW_MGR_MEM_IF_READ_DQS_WIDTH];
|
412 |
|
|
debug_cal_dqs_out_settings_t cal_dqs_out_settings[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
|
413 |
|
|
debug_cal_dm_settings_t cal_dm_settings[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP];
|
414 |
|
|
|
415 |
|
|
} debug_cal_report_t;
|
416 |
|
|
|
417 |
|
|
/* Left and right edges of the data valid window, in units of delay taps. */
|
418 |
|
|
typedef struct debug_margin_min_max_margins_struct {
|
419 |
|
|
alt_u32 min_working_setting;
|
420 |
|
|
alt_u32 max_working_setting;
|
421 |
|
|
} debug_margin_min_max_margins_t;
|
422 |
|
|
|
423 |
|
|
/* Post-calibration margin report (must be enabled using the TCLDBG_ENABLE_MARGIN_REPORT command first)*/
|
424 |
|
|
typedef struct debug_margin_report_struct {
|
425 |
|
|
// Size in 32-bit words of the report
|
426 |
|
|
alt_u32 data_size;
|
427 |
|
|
|
428 |
|
|
alt_u32 report_flags;
|
429 |
|
|
|
430 |
|
|
alt_u32 mem_data_width;
|
431 |
|
|
alt_u32 mem_write_dqs_width;
|
432 |
|
|
|
433 |
|
|
alt_u32 num_shadow_regs;
|
434 |
|
|
|
435 |
|
|
debug_margin_min_max_margins_t margin_dm_margins[NUM_SHADOW_REGS][RW_MGR_MEM_IF_WRITE_DQS_WIDTH][RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP];
|
436 |
|
|
|
437 |
|
|
debug_margin_min_max_margins_t margin_dq_in_margins[NUM_SHADOW_REGS][RW_MGR_MEM_DATA_WIDTH];
|
438 |
|
|
debug_margin_min_max_margins_t margin_dq_out_margins[NUM_SHADOW_REGS][RW_MGR_MEM_DATA_WIDTH];
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
} debug_margin_report_t;
|
442 |
|
|
|
443 |
|
|
typedef alt_u32 printf_read_buffer_t[PRINTF_READ_BUFFER_SIZE];
|
444 |
|
|
|
445 |
|
|
typedef struct debug_printf_output {
|
446 |
|
|
alt_u32 data_size;
|
447 |
|
|
|
448 |
|
|
alt_u32 fifo_size;
|
449 |
|
|
alt_u32 word_size;
|
450 |
|
|
|
451 |
|
|
alt_u32 head;
|
452 |
|
|
alt_u32 count;
|
453 |
|
|
alt_u32 slave_lock;
|
454 |
|
|
alt_u32 master_lock;
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
printf_read_buffer_t read_buffer[PRINTF_READ_BUFFER_FIFO_WORDS];
|
458 |
|
|
printf_read_buffer_t active_word;
|
459 |
|
|
|
460 |
|
|
} debug_printf_output_t;
|
461 |
|
|
|
462 |
|
|
typedef struct rw_manager_di_buffer {
|
463 |
|
|
alt_u32 bit_chk;
|
464 |
|
|
alt_u32 delay;
|
465 |
|
|
alt_u32 v;
|
466 |
|
|
alt_u32 p;
|
467 |
|
|
alt_u32 d;
|
468 |
|
|
alt_u32 di_buffer_0a;
|
469 |
|
|
alt_u32 di_buffer_0b;
|
470 |
|
|
alt_u32 di_buffer_1a;
|
471 |
|
|
alt_u32 di_buffer_1b;
|
472 |
|
|
alt_u32 di_buffer_2a;
|
473 |
|
|
alt_u32 di_buffer_2b;
|
474 |
|
|
alt_u32 di_buffer_3a;
|
475 |
|
|
alt_u32 di_buffer_3b;
|
476 |
|
|
alt_u32 di_buffer_4a;
|
477 |
|
|
alt_u32 di_buffer_4b;
|
478 |
|
|
} rw_manager_di_buffer_t;
|
479 |
|
|
|
480 |
|
|
typedef struct rw_manager_di_report {
|
481 |
|
|
alt_u32 data_size;
|
482 |
|
|
alt_u32 flags;
|
483 |
|
|
alt_u32 cur_samples;
|
484 |
|
|
alt_u32 max_samples;
|
485 |
|
|
rw_manager_di_buffer_t di_buffer[NUM_DI_SAMPLE];
|
486 |
|
|
} rw_manager_di_report_t;
|
487 |
|
|
|
488 |
|
|
typedef struct emif_toolkit_debug_data {
|
489 |
|
|
// Size in 32-bit words of all the emif toolkit debug data
|
490 |
|
|
alt_u32 data_size;
|
491 |
|
|
|
492 |
|
|
alt_u32 dqs_write_width_ptr;
|
493 |
|
|
alt_u32 group_mask_ptr;
|
494 |
|
|
alt_u32 num_ranks_ptr;
|
495 |
|
|
alt_u32 rank_mask_ptr;
|
496 |
|
|
alt_u32 active_groups_ptr;
|
497 |
|
|
alt_u32 active_ranks_ptr;
|
498 |
|
|
alt_u32 group_mask_size_ptr;
|
499 |
|
|
alt_u32 rank_mask_size_ptr;
|
500 |
|
|
} emif_toolkit_debug_data_t;
|
501 |
|
|
|
502 |
|
|
/* This the main debug data structure. This is where you write
|
503 |
|
|
commands, poll command status, pass command parameters, etc. Contained
|
504 |
|
|
within this data structure are the reports. The memory address of this
|
505 |
|
|
data structure is in core_debug_defines.h (it is dynamic). For example:
|
506 |
|
|
#define SEQ_CORE_DEBUG_BASE 0x000140c4
|
507 |
|
|
The sizes of all the data structures are dynamic, as they depend on
|
508 |
|
|
interface size and other parameters. Accessing them outside a software
|
509 |
|
|
context is trickier but it can be done by looking at the "data_size"
|
510 |
|
|
field of the reports.
|
511 |
|
|
*/
|
512 |
|
|
typedef struct debug_data_struct {
|
513 |
|
|
// Size in 32-bit words of all the debug data
|
514 |
|
|
alt_u32 data_size;
|
515 |
|
|
|
516 |
|
|
// Status bits
|
517 |
|
|
alt_u32 status;
|
518 |
|
|
|
519 |
|
|
// Command interaction
|
520 |
|
|
alt_u32 requested_command;
|
521 |
|
|
alt_u32 command_status;
|
522 |
|
|
alt_u32 command_parameters[COMMAND_PARAM_WORDS];
|
523 |
|
|
|
524 |
|
|
// Pointers to the reports
|
525 |
|
|
alt_u32 summary_report_ptr;
|
526 |
|
|
alt_u32 cal_report_ptr;
|
527 |
|
|
alt_u32 margin_report_ptr;
|
528 |
|
|
|
529 |
|
|
// Printf output report
|
530 |
|
|
alt_u32 printf_output_ptr;
|
531 |
|
|
|
532 |
|
|
// Debug toolkit debugging data
|
533 |
|
|
alt_u32 emif_toolkit_debug_data_ptr;
|
534 |
|
|
|
535 |
|
|
#if ENABLE_DQSEN_SWEEP
|
536 |
|
|
// di report
|
537 |
|
|
alt_u32 di_report_ptr;
|
538 |
|
|
#endif
|
539 |
|
|
|
540 |
|
|
// Report data structures
|
541 |
|
|
debug_summary_report_t summary_report;
|
542 |
|
|
debug_cal_report_t cal_report;
|
543 |
|
|
debug_margin_report_t margin_report;
|
544 |
|
|
|
545 |
|
|
#if ENABLE_PRINTF_LOG
|
546 |
|
|
debug_printf_output_t printf_output;
|
547 |
|
|
#endif
|
548 |
|
|
|
549 |
|
|
#if ENABLE_DQSEN_SWEEP
|
550 |
|
|
rw_manager_di_report_t di_report;
|
551 |
|
|
#endif
|
552 |
|
|
|
553 |
|
|
emif_toolkit_debug_data_t emif_toolkit_debug_data;
|
554 |
|
|
|
555 |
|
|
} debug_data_t;
|
556 |
|
|
|
557 |
|
|
/* TCL io memory */
|
558 |
|
|
|
559 |
|
|
volatile extern debug_summary_report_t *debug_summary_report;
|
560 |
|
|
volatile extern debug_cal_report_t *debug_cal_report;
|
561 |
|
|
volatile extern debug_margin_report_t *debug_margin_report;
|
562 |
|
|
volatile extern debug_printf_output_t *debug_printf_output;
|
563 |
|
|
volatile extern debug_data_t *debug_data;
|
564 |
|
|
|
565 |
|
|
volatile extern emif_toolkit_debug_data_t *debug_emif_toolkit_debug_data;
|
566 |
|
|
|
567 |
|
|
|
568 |
|
|
extern void tclrpt_initialize_debug_status (void);
|
569 |
|
|
extern void tclrpt_initialize (debug_data_t *);
|
570 |
|
|
extern void tclrpt_loop(void);
|
571 |
|
|
extern void tclrpt_initialize_data(void);
|
572 |
|
|
extern void tclrpt_set_group_as_calibration_attempted(alt_u32 write_group);
|
573 |
|
|
|
574 |
|
|
#if BFM_MODE
|
575 |
|
|
extern void tclrpt_dump_internal_data(void);
|
576 |
|
|
extern void tclrpt_populate_fake_margin_data(void);
|
577 |
|
|
#endif
|
578 |
|
|
|
579 |
|
|
#endif // ENABLE_TCL_DEBUG
|
580 |
|
|
|
581 |
|
|
#endif
|