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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_hps_0_fpga_interfaces.sv] - Blame information for rev 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors.  Please refer to the applicable
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// agreement for further details.
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module ulight_fifo_hps_0_fpga_interfaces(
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// h2f_reset
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  output wire [1 - 1 : 0 ] h2f_rst_n
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// h2f_axi_clock
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 ,input wire [1 - 1 : 0 ] h2f_axi_clk
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// h2f_axi_master
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 ,output wire [12 - 1 : 0 ] h2f_AWID
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 ,output wire [30 - 1 : 0 ] h2f_AWADDR
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 ,output wire [4 - 1 : 0 ] h2f_AWLEN
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 ,output wire [3 - 1 : 0 ] h2f_AWSIZE
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 ,output wire [2 - 1 : 0 ] h2f_AWBURST
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 ,output wire [2 - 1 : 0 ] h2f_AWLOCK
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 ,output wire [4 - 1 : 0 ] h2f_AWCACHE
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 ,output wire [3 - 1 : 0 ] h2f_AWPROT
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 ,output wire [1 - 1 : 0 ] h2f_AWVALID
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 ,input wire [1 - 1 : 0 ] h2f_AWREADY
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 ,output wire [12 - 1 : 0 ] h2f_WID
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 ,output wire [32 - 1 : 0 ] h2f_WDATA
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 ,output wire [4 - 1 : 0 ] h2f_WSTRB
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 ,output wire [1 - 1 : 0 ] h2f_WLAST
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 ,output wire [1 - 1 : 0 ] h2f_WVALID
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 ,input wire [1 - 1 : 0 ] h2f_WREADY
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 ,input wire [12 - 1 : 0 ] h2f_BID
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 ,input wire [2 - 1 : 0 ] h2f_BRESP
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 ,input wire [1 - 1 : 0 ] h2f_BVALID
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 ,output wire [1 - 1 : 0 ] h2f_BREADY
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 ,output wire [12 - 1 : 0 ] h2f_ARID
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 ,output wire [30 - 1 : 0 ] h2f_ARADDR
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 ,output wire [4 - 1 : 0 ] h2f_ARLEN
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 ,output wire [3 - 1 : 0 ] h2f_ARSIZE
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 ,output wire [2 - 1 : 0 ] h2f_ARBURST
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 ,output wire [2 - 1 : 0 ] h2f_ARLOCK
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 ,output wire [4 - 1 : 0 ] h2f_ARCACHE
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 ,output wire [3 - 1 : 0 ] h2f_ARPROT
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 ,output wire [1 - 1 : 0 ] h2f_ARVALID
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 ,input wire [1 - 1 : 0 ] h2f_ARREADY
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 ,input wire [12 - 1 : 0 ] h2f_RID
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 ,input wire [32 - 1 : 0 ] h2f_RDATA
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 ,input wire [2 - 1 : 0 ] h2f_RRESP
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 ,input wire [1 - 1 : 0 ] h2f_RLAST
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 ,input wire [1 - 1 : 0 ] h2f_RVALID
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 ,output wire [1 - 1 : 0 ] h2f_RREADY
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);
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cyclonev_hps_interface_clocks_resets clocks_resets(
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 .f2h_pending_rst_ack({
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    1'b1 // 0:0
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  })
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,.f2h_warm_rst_req_n({
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    1'b1 // 0:0
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  })
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,.f2h_dbg_rst_req_n({
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    1'b1 // 0:0
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  })
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,.h2f_rst_n({
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    h2f_rst_n[0:0] // 0:0
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  })
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,.f2h_cold_rst_req_n({
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    1'b1 // 0:0
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  })
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);
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cyclonev_hps_interface_dbg_apb debug_apb(
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 .DBG_APB_DISABLE({
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    1'b0 // 0:0
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  })
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,.P_CLK_EN({
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    1'b0 // 0:0
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  })
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);
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cyclonev_hps_interface_tpiu_trace tpiu(
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 .traceclk_ctl({
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    1'b1 // 0:0
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  })
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);
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cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
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 .boot_from_fpga_ready({
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    1'b0 // 0:0
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  })
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,.boot_from_fpga_on_failure({
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    1'b0 // 0:0
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  })
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,.bsel_en({
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    1'b0 // 0:0
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  })
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,.csel_en({
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    1'b0 // 0:0
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  })
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,.csel({
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    2'b01 // 1:0
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  })
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,.bsel({
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    3'b001 // 2:0
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  })
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);
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cyclonev_hps_interface_fpga2hps fpga2hps(
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 .port_size_config({
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    2'b11 // 1:0
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  })
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);
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cyclonev_hps_interface_hps2fpga hps2fpga(
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 .port_size_config({
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    2'b00 // 1:0
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  })
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,.arsize({
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    h2f_ARSIZE[2:0] // 2:0
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  })
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,.wvalid({
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    h2f_WVALID[0:0] // 0:0
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  })
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,.rlast({
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    h2f_RLAST[0:0] // 0:0
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  })
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,.clk({
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    h2f_axi_clk[0:0] // 0:0
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  })
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,.rresp({
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    h2f_RRESP[1:0] // 1:0
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  })
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,.arready({
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    h2f_ARREADY[0:0] // 0:0
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  })
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,.arprot({
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    h2f_ARPROT[2:0] // 2:0
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  })
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,.araddr({
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    h2f_ARADDR[29:0] // 29:0
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  })
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,.bvalid({
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    h2f_BVALID[0:0] // 0:0
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  })
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,.arid({
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    h2f_ARID[11:0] // 11:0
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  })
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,.bid({
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    h2f_BID[11:0] // 11:0
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  })
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,.arburst({
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    h2f_ARBURST[1:0] // 1:0
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  })
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,.arcache({
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    h2f_ARCACHE[3:0] // 3:0
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  })
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,.awvalid({
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    h2f_AWVALID[0:0] // 0:0
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  })
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,.wdata({
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    h2f_WDATA[31:0] // 31:0
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  })
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,.rid({
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    h2f_RID[11:0] // 11:0
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  })
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,.rvalid({
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    h2f_RVALID[0:0] // 0:0
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  })
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,.wready({
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    h2f_WREADY[0:0] // 0:0
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  })
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,.awlock({
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    h2f_AWLOCK[1:0] // 1:0
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  })
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,.bresp({
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    h2f_BRESP[1:0] // 1:0
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  })
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,.arlen({
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    h2f_ARLEN[3:0] // 3:0
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  })
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,.awsize({
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    h2f_AWSIZE[2:0] // 2:0
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  })
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,.awlen({
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    h2f_AWLEN[3:0] // 3:0
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  })
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,.bready({
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    h2f_BREADY[0:0] // 0:0
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  })
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,.awid({
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    h2f_AWID[11:0] // 11:0
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  })
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,.rdata({
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    h2f_RDATA[31:0] // 31:0
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  })
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,.awready({
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    h2f_AWREADY[0:0] // 0:0
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  })
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,.arvalid({
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    h2f_ARVALID[0:0] // 0:0
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  })
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,.wlast({
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    h2f_WLAST[0:0] // 0:0
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  })
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,.awprot({
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    h2f_AWPROT[2:0] // 2:0
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  })
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,.awaddr({
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    h2f_AWADDR[29:0] // 29:0
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  })
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,.wid({
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    h2f_WID[11:0] // 11:0
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  })
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,.awcache({
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    h2f_AWCACHE[3:0] // 3:0
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  })
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,.arlock({
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    h2f_ARLOCK[1:0] // 1:0
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  })
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,.awburst({
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    h2f_AWBURST[1:0] // 1:0
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  })
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,.rready({
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    h2f_RREADY[0:0] // 0:0
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  })
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,.wstrb({
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    h2f_WSTRB[3:0] // 3:0
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  })
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);
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cyclonev_hps_interface_fpga2sdram f2sdram(
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 .cfg_cport_rfifo_map({
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    18'b000000000000000000 // 17:0
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  })
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,.cfg_axi_mm_select({
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    6'b000000 // 5:0
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  })
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,.cfg_wfifo_cport_map({
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    16'b0000000000000000 // 15:0
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  })
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,.cfg_cport_type({
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    12'b000000000000 // 11:0
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  })
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,.cfg_rfifo_cport_map({
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    16'b0000000000000000 // 15:0
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  })
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,.cfg_port_width({
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    12'b000000000000 // 11:0
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  })
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,.cfg_cport_wfifo_map({
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    18'b000000000000000000 // 17:0
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  })
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);
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endmodule
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