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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_mm_interconnect_0_cmd_demux.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4 40 redbear
// files from any of the foregoing (including device programming or simulation
5 32 redbear
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable
8 32 redbear
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14 40 redbear
// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
15 32 redbear
// $Revision: #1 $
16 40 redbear
// $Date: 2017/07/30 $
17 32 redbear
// $Author: swbranch $
18
 
19
// -------------------------------------
20
// Merlin Demultiplexer
21
//
22
// Asserts valid on the appropriate output
23
// given a one-hot channel signal.
24
// -------------------------------------
25
 
26
`timescale 1 ns / 1 ns
27
 
28
// ------------------------------------------
29
// Generation parameters:
30
//   output_name:         ulight_fifo_mm_interconnect_0_cmd_demux
31
//   ST_DATA_W:           129
32
//   ST_CHANNEL_W:        22
33
//   NUM_OUTPUTS:         22
34
//   VALID_WIDTH:         22
35
// ------------------------------------------
36
 
37
//------------------------------------------
38
// Message Supression Used
39
// QIS Warnings
40
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
41
//------------------------------------------
42
 
43
module ulight_fifo_mm_interconnect_0_cmd_demux
44
(
45
    // -------------------
46
    // Sink
47
    // -------------------
48
    input  [22-1      : 0]   sink_valid,
49
    input  [129-1    : 0]   sink_data, // ST_DATA_W=129
50
    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
51
    input                         sink_startofpacket,
52
    input                         sink_endofpacket,
53
    output                        sink_ready,
54
 
55
    // -------------------
56
    // Sources
57
    // -------------------
58
    output reg                      src0_valid,
59
    output reg [129-1    : 0] src0_data, // ST_DATA_W=129
60
    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
61
    output reg                      src0_startofpacket,
62
    output reg                      src0_endofpacket,
63
    input                           src0_ready,
64
 
65
    output reg                      src1_valid,
66
    output reg [129-1    : 0] src1_data, // ST_DATA_W=129
67
    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
68
    output reg                      src1_startofpacket,
69
    output reg                      src1_endofpacket,
70
    input                           src1_ready,
71
 
72
    output reg                      src2_valid,
73
    output reg [129-1    : 0] src2_data, // ST_DATA_W=129
74
    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
75
    output reg                      src2_startofpacket,
76
    output reg                      src2_endofpacket,
77
    input                           src2_ready,
78
 
79
    output reg                      src3_valid,
80
    output reg [129-1    : 0] src3_data, // ST_DATA_W=129
81
    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
82
    output reg                      src3_startofpacket,
83
    output reg                      src3_endofpacket,
84
    input                           src3_ready,
85
 
86
    output reg                      src4_valid,
87
    output reg [129-1    : 0] src4_data, // ST_DATA_W=129
88
    output reg [22-1 : 0] src4_channel, // ST_CHANNEL_W=22
89
    output reg                      src4_startofpacket,
90
    output reg                      src4_endofpacket,
91
    input                           src4_ready,
92
 
93
    output reg                      src5_valid,
94
    output reg [129-1    : 0] src5_data, // ST_DATA_W=129
95
    output reg [22-1 : 0] src5_channel, // ST_CHANNEL_W=22
96
    output reg                      src5_startofpacket,
97
    output reg                      src5_endofpacket,
98
    input                           src5_ready,
99
 
100
    output reg                      src6_valid,
101
    output reg [129-1    : 0] src6_data, // ST_DATA_W=129
102
    output reg [22-1 : 0] src6_channel, // ST_CHANNEL_W=22
103
    output reg                      src6_startofpacket,
104
    output reg                      src6_endofpacket,
105
    input                           src6_ready,
106
 
107
    output reg                      src7_valid,
108
    output reg [129-1    : 0] src7_data, // ST_DATA_W=129
109
    output reg [22-1 : 0] src7_channel, // ST_CHANNEL_W=22
110
    output reg                      src7_startofpacket,
111
    output reg                      src7_endofpacket,
112
    input                           src7_ready,
113
 
114
    output reg                      src8_valid,
115
    output reg [129-1    : 0] src8_data, // ST_DATA_W=129
116
    output reg [22-1 : 0] src8_channel, // ST_CHANNEL_W=22
117
    output reg                      src8_startofpacket,
118
    output reg                      src8_endofpacket,
119
    input                           src8_ready,
120
 
121
    output reg                      src9_valid,
122
    output reg [129-1    : 0] src9_data, // ST_DATA_W=129
123
    output reg [22-1 : 0] src9_channel, // ST_CHANNEL_W=22
124
    output reg                      src9_startofpacket,
125
    output reg                      src9_endofpacket,
126
    input                           src9_ready,
127
 
128
    output reg                      src10_valid,
129
    output reg [129-1    : 0] src10_data, // ST_DATA_W=129
130
    output reg [22-1 : 0] src10_channel, // ST_CHANNEL_W=22
131
    output reg                      src10_startofpacket,
132
    output reg                      src10_endofpacket,
133
    input                           src10_ready,
134
 
135
    output reg                      src11_valid,
136
    output reg [129-1    : 0] src11_data, // ST_DATA_W=129
137
    output reg [22-1 : 0] src11_channel, // ST_CHANNEL_W=22
138
    output reg                      src11_startofpacket,
139
    output reg                      src11_endofpacket,
140
    input                           src11_ready,
141
 
142
    output reg                      src12_valid,
143
    output reg [129-1    : 0] src12_data, // ST_DATA_W=129
144
    output reg [22-1 : 0] src12_channel, // ST_CHANNEL_W=22
145
    output reg                      src12_startofpacket,
146
    output reg                      src12_endofpacket,
147
    input                           src12_ready,
148
 
149
    output reg                      src13_valid,
150
    output reg [129-1    : 0] src13_data, // ST_DATA_W=129
151
    output reg [22-1 : 0] src13_channel, // ST_CHANNEL_W=22
152
    output reg                      src13_startofpacket,
153
    output reg                      src13_endofpacket,
154
    input                           src13_ready,
155
 
156
    output reg                      src14_valid,
157
    output reg [129-1    : 0] src14_data, // ST_DATA_W=129
158
    output reg [22-1 : 0] src14_channel, // ST_CHANNEL_W=22
159
    output reg                      src14_startofpacket,
160
    output reg                      src14_endofpacket,
161
    input                           src14_ready,
162
 
163
    output reg                      src15_valid,
164
    output reg [129-1    : 0] src15_data, // ST_DATA_W=129
165
    output reg [22-1 : 0] src15_channel, // ST_CHANNEL_W=22
166
    output reg                      src15_startofpacket,
167
    output reg                      src15_endofpacket,
168
    input                           src15_ready,
169
 
170
    output reg                      src16_valid,
171
    output reg [129-1    : 0] src16_data, // ST_DATA_W=129
172
    output reg [22-1 : 0] src16_channel, // ST_CHANNEL_W=22
173
    output reg                      src16_startofpacket,
174
    output reg                      src16_endofpacket,
175
    input                           src16_ready,
176
 
177
    output reg                      src17_valid,
178
    output reg [129-1    : 0] src17_data, // ST_DATA_W=129
179
    output reg [22-1 : 0] src17_channel, // ST_CHANNEL_W=22
180
    output reg                      src17_startofpacket,
181
    output reg                      src17_endofpacket,
182
    input                           src17_ready,
183
 
184
    output reg                      src18_valid,
185
    output reg [129-1    : 0] src18_data, // ST_DATA_W=129
186
    output reg [22-1 : 0] src18_channel, // ST_CHANNEL_W=22
187
    output reg                      src18_startofpacket,
188
    output reg                      src18_endofpacket,
189
    input                           src18_ready,
190
 
191
    output reg                      src19_valid,
192
    output reg [129-1    : 0] src19_data, // ST_DATA_W=129
193
    output reg [22-1 : 0] src19_channel, // ST_CHANNEL_W=22
194
    output reg                      src19_startofpacket,
195
    output reg                      src19_endofpacket,
196
    input                           src19_ready,
197
 
198
    output reg                      src20_valid,
199
    output reg [129-1    : 0] src20_data, // ST_DATA_W=129
200
    output reg [22-1 : 0] src20_channel, // ST_CHANNEL_W=22
201
    output reg                      src20_startofpacket,
202
    output reg                      src20_endofpacket,
203
    input                           src20_ready,
204
 
205
    output reg                      src21_valid,
206
    output reg [129-1    : 0] src21_data, // ST_DATA_W=129
207
    output reg [22-1 : 0] src21_channel, // ST_CHANNEL_W=22
208
    output reg                      src21_startofpacket,
209
    output reg                      src21_endofpacket,
210
    input                           src21_ready,
211
 
212
 
213
    // -------------------
214
    // Clock & Reset
215
    // -------------------
216
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
217
    input clk,
218
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
219
    input reset
220
 
221
);
222
 
223
    localparam NUM_OUTPUTS = 22;
224
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
225
 
226
    // -------------------
227
    // Demux
228
    // -------------------
229
    always @* begin
230
        src0_data          = sink_data;
231
        src0_startofpacket = sink_startofpacket;
232
        src0_endofpacket   = sink_endofpacket;
233
        src0_channel       = sink_channel >> NUM_OUTPUTS;
234
 
235
        src0_valid         = sink_channel[0] && sink_valid[0];
236
 
237
        src1_data          = sink_data;
238
        src1_startofpacket = sink_startofpacket;
239
        src1_endofpacket   = sink_endofpacket;
240
        src1_channel       = sink_channel >> NUM_OUTPUTS;
241
 
242
        src1_valid         = sink_channel[1] && sink_valid[1];
243
 
244
        src2_data          = sink_data;
245
        src2_startofpacket = sink_startofpacket;
246
        src2_endofpacket   = sink_endofpacket;
247
        src2_channel       = sink_channel >> NUM_OUTPUTS;
248
 
249
        src2_valid         = sink_channel[2] && sink_valid[2];
250
 
251
        src3_data          = sink_data;
252
        src3_startofpacket = sink_startofpacket;
253
        src3_endofpacket   = sink_endofpacket;
254
        src3_channel       = sink_channel >> NUM_OUTPUTS;
255
 
256
        src3_valid         = sink_channel[3] && sink_valid[3];
257
 
258
        src4_data          = sink_data;
259
        src4_startofpacket = sink_startofpacket;
260
        src4_endofpacket   = sink_endofpacket;
261
        src4_channel       = sink_channel >> NUM_OUTPUTS;
262
 
263
        src4_valid         = sink_channel[4] && sink_valid[4];
264
 
265
        src5_data          = sink_data;
266
        src5_startofpacket = sink_startofpacket;
267
        src5_endofpacket   = sink_endofpacket;
268
        src5_channel       = sink_channel >> NUM_OUTPUTS;
269
 
270
        src5_valid         = sink_channel[5] && sink_valid[5];
271
 
272
        src6_data          = sink_data;
273
        src6_startofpacket = sink_startofpacket;
274
        src6_endofpacket   = sink_endofpacket;
275
        src6_channel       = sink_channel >> NUM_OUTPUTS;
276
 
277
        src6_valid         = sink_channel[6] && sink_valid[6];
278
 
279
        src7_data          = sink_data;
280
        src7_startofpacket = sink_startofpacket;
281
        src7_endofpacket   = sink_endofpacket;
282
        src7_channel       = sink_channel >> NUM_OUTPUTS;
283
 
284
        src7_valid         = sink_channel[7] && sink_valid[7];
285
 
286
        src8_data          = sink_data;
287
        src8_startofpacket = sink_startofpacket;
288
        src8_endofpacket   = sink_endofpacket;
289
        src8_channel       = sink_channel >> NUM_OUTPUTS;
290
 
291
        src8_valid         = sink_channel[8] && sink_valid[8];
292
 
293
        src9_data          = sink_data;
294
        src9_startofpacket = sink_startofpacket;
295
        src9_endofpacket   = sink_endofpacket;
296
        src9_channel       = sink_channel >> NUM_OUTPUTS;
297
 
298
        src9_valid         = sink_channel[9] && sink_valid[9];
299
 
300
        src10_data          = sink_data;
301
        src10_startofpacket = sink_startofpacket;
302
        src10_endofpacket   = sink_endofpacket;
303
        src10_channel       = sink_channel >> NUM_OUTPUTS;
304
 
305
        src10_valid         = sink_channel[10] && sink_valid[10];
306
 
307
        src11_data          = sink_data;
308
        src11_startofpacket = sink_startofpacket;
309
        src11_endofpacket   = sink_endofpacket;
310
        src11_channel       = sink_channel >> NUM_OUTPUTS;
311
 
312
        src11_valid         = sink_channel[11] && sink_valid[11];
313
 
314
        src12_data          = sink_data;
315
        src12_startofpacket = sink_startofpacket;
316
        src12_endofpacket   = sink_endofpacket;
317
        src12_channel       = sink_channel >> NUM_OUTPUTS;
318
 
319
        src12_valid         = sink_channel[12] && sink_valid[12];
320
 
321
        src13_data          = sink_data;
322
        src13_startofpacket = sink_startofpacket;
323
        src13_endofpacket   = sink_endofpacket;
324
        src13_channel       = sink_channel >> NUM_OUTPUTS;
325
 
326
        src13_valid         = sink_channel[13] && sink_valid[13];
327
 
328
        src14_data          = sink_data;
329
        src14_startofpacket = sink_startofpacket;
330
        src14_endofpacket   = sink_endofpacket;
331
        src14_channel       = sink_channel >> NUM_OUTPUTS;
332
 
333
        src14_valid         = sink_channel[14] && sink_valid[14];
334
 
335
        src15_data          = sink_data;
336
        src15_startofpacket = sink_startofpacket;
337
        src15_endofpacket   = sink_endofpacket;
338
        src15_channel       = sink_channel >> NUM_OUTPUTS;
339
 
340
        src15_valid         = sink_channel[15] && sink_valid[15];
341
 
342
        src16_data          = sink_data;
343
        src16_startofpacket = sink_startofpacket;
344
        src16_endofpacket   = sink_endofpacket;
345
        src16_channel       = sink_channel >> NUM_OUTPUTS;
346
 
347
        src16_valid         = sink_channel[16] && sink_valid[16];
348
 
349
        src17_data          = sink_data;
350
        src17_startofpacket = sink_startofpacket;
351
        src17_endofpacket   = sink_endofpacket;
352
        src17_channel       = sink_channel >> NUM_OUTPUTS;
353
 
354
        src17_valid         = sink_channel[17] && sink_valid[17];
355
 
356
        src18_data          = sink_data;
357
        src18_startofpacket = sink_startofpacket;
358
        src18_endofpacket   = sink_endofpacket;
359
        src18_channel       = sink_channel >> NUM_OUTPUTS;
360
 
361
        src18_valid         = sink_channel[18] && sink_valid[18];
362
 
363
        src19_data          = sink_data;
364
        src19_startofpacket = sink_startofpacket;
365
        src19_endofpacket   = sink_endofpacket;
366
        src19_channel       = sink_channel >> NUM_OUTPUTS;
367
 
368
        src19_valid         = sink_channel[19] && sink_valid[19];
369
 
370
        src20_data          = sink_data;
371
        src20_startofpacket = sink_startofpacket;
372
        src20_endofpacket   = sink_endofpacket;
373
        src20_channel       = sink_channel >> NUM_OUTPUTS;
374
 
375
        src20_valid         = sink_channel[20] && sink_valid[20];
376
 
377
        src21_data          = sink_data;
378
        src21_startofpacket = sink_startofpacket;
379
        src21_endofpacket   = sink_endofpacket;
380
        src21_channel       = sink_channel >> NUM_OUTPUTS;
381
 
382
        src21_valid         = sink_channel[21] && sink_valid[21];
383
 
384
    end
385
 
386
    // -------------------
387
    // Backpressure
388
    // -------------------
389
    assign ready_vector[0] = src0_ready;
390
    assign ready_vector[1] = src1_ready;
391
    assign ready_vector[2] = src2_ready;
392
    assign ready_vector[3] = src3_ready;
393
    assign ready_vector[4] = src4_ready;
394
    assign ready_vector[5] = src5_ready;
395
    assign ready_vector[6] = src6_ready;
396
    assign ready_vector[7] = src7_ready;
397
    assign ready_vector[8] = src8_ready;
398
    assign ready_vector[9] = src9_ready;
399
    assign ready_vector[10] = src10_ready;
400
    assign ready_vector[11] = src11_ready;
401
    assign ready_vector[12] = src12_ready;
402
    assign ready_vector[13] = src13_ready;
403
    assign ready_vector[14] = src14_ready;
404
    assign ready_vector[15] = src15_ready;
405
    assign ready_vector[16] = src16_ready;
406
    assign ready_vector[17] = src17_ready;
407
    assign ready_vector[18] = src18_ready;
408
    assign ready_vector[19] = src19_ready;
409
    assign ready_vector[20] = src20_ready;
410
    assign ready_vector[21] = src21_ready;
411
 
412
    assign sink_ready = |(sink_channel & ready_vector);
413
 
414
endmodule
415
 

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