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redbear |
// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/17.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2017/01/22 $
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// $Author: swbranch $
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// -------------------------------------------------------
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// Merlin Router
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//
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// Asserts the appropriate one-hot encoded channel based on
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// either (a) the address or (b) the dest id. The DECODER_TYPE
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// parameter controls this behaviour. 0 means address decoder,
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// 1 means dest id decoder.
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//
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// In the case of (a), it also sets the destination id.
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// -------------------------------------------------------
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`timescale 1 ns / 1 ns
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module ulight_fifo_mm_interconnect_0_router_default_decode
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#(
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parameter DEFAULT_CHANNEL = 0,
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DEFAULT_WR_CHANNEL = -1,
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DEFAULT_RD_CHANNEL = -1,
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DEFAULT_DESTID = 12
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)
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(output [104 - 100 : 0] default_destination_id,
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output [22-1 : 0] default_wr_channel,
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output [22-1 : 0] default_rd_channel,
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output [22-1 : 0] default_src_channel
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);
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assign default_destination_id =
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DEFAULT_DESTID[104 - 100 : 0];
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generate
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if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
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assign default_src_channel = '0;
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end
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else begin : default_channel_assignment
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assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
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end
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endgenerate
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generate
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if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
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assign default_wr_channel = '0;
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assign default_rd_channel = '0;
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end
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else begin : default_rw_channel_assignment
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assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
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assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
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end
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endgenerate
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endmodule
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module ulight_fifo_mm_interconnect_0_router
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(
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// -------------------
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// Clock & Reset
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// -------------------
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input clk,
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input reset,
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// -------------------
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// Command Sink (Input)
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// -------------------
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input sink_valid,
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input [129-1 : 0] sink_data,
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input sink_startofpacket,
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input sink_endofpacket,
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output sink_ready,
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// -------------------
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// Command Source (Output)
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// -------------------
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output src_valid,
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output reg [129-1 : 0] src_data,
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output reg [22-1 : 0] src_channel,
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output src_startofpacket,
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output src_endofpacket,
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input src_ready
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);
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// -------------------------------------------------------
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// Local parameters and variables
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// -------------------------------------------------------
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localparam PKT_ADDR_H = 65;
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localparam PKT_ADDR_L = 36;
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localparam PKT_DEST_ID_H = 104;
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localparam PKT_DEST_ID_L = 100;
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localparam PKT_PROTECTION_H = 119;
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localparam PKT_PROTECTION_L = 117;
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localparam ST_DATA_W = 129;
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localparam ST_CHANNEL_W = 22;
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localparam DECODER_TYPE = 0;
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localparam PKT_TRANS_WRITE = 68;
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localparam PKT_TRANS_READ = 69;
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localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
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localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
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// -------------------------------------------------------
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// Figure out the number of bits to mask off for each slave span
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// during address decoding
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// -------------------------------------------------------
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localparam PAD0 = log2ceil(64'h10 - 64'h0);
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localparam PAD1 = log2ceil(64'h10010 - 64'h10000);
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localparam PAD2 = log2ceil(64'h1a010 - 64'h1a000);
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localparam PAD3 = log2ceil(64'h20010 - 64'h20000);
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localparam PAD4 = log2ceil(64'h2a010 - 64'h2a000);
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localparam PAD5 = log2ceil(64'h30010 - 64'h30000);
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localparam PAD6 = log2ceil(64'h3a010 - 64'h3a000);
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localparam PAD7 = log2ceil(64'h40010 - 64'h40000);
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localparam PAD8 = log2ceil(64'h4a010 - 64'h4a000);
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localparam PAD9 = log2ceil(64'h50010 - 64'h50000);
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localparam PAD10 = log2ceil(64'h5a010 - 64'h5a000);
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localparam PAD11 = log2ceil(64'h60010 - 64'h60000);
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localparam PAD12 = log2ceil(64'h6a010 - 64'h6a000);
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localparam PAD13 = log2ceil(64'h70010 - 64'h70000);
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localparam PAD14 = log2ceil(64'h80010 - 64'h80000);
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localparam PAD15 = log2ceil(64'h90010 - 64'h90000);
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localparam PAD16 = log2ceil(64'ha0010 - 64'ha0000);
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localparam PAD17 = log2ceil(64'hb0010 - 64'hb0000);
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localparam PAD18 = log2ceil(64'hc0010 - 64'hc0000);
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localparam PAD19 = log2ceil(64'hd0010 - 64'hd0000);
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localparam PAD20 = log2ceil(64'he0010 - 64'he0000);
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localparam PAD21 = log2ceil(64'hf0010 - 64'hf0000);
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// -------------------------------------------------------
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// Work out which address bits are significant based on the
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// address range of the slaves. If the required width is too
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// large or too small, we use the address field width instead.
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// -------------------------------------------------------
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localparam ADDR_RANGE = 64'hf0010;
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localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
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localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
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(RANGE_ADDR_WIDTH == 0) ?
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PKT_ADDR_H :
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PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
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localparam RG = RANGE_ADDR_WIDTH-1;
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localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
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reg [PKT_ADDR_W-1 : 0] address;
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always @* begin
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address = {PKT_ADDR_W{1'b0}};
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address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
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end
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// -------------------------------------------------------
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// Pass almost everything through, untouched
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// -------------------------------------------------------
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assign sink_ready = src_ready;
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assign src_valid = sink_valid;
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assign src_startofpacket = sink_startofpacket;
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assign src_endofpacket = sink_endofpacket;
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wire [PKT_DEST_ID_W-1:0] default_destid;
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wire [22-1 : 0] default_src_channel;
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// -------------------------------------------------------
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// Write and read transaction signals
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// -------------------------------------------------------
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wire read_transaction;
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assign read_transaction = sink_data[PKT_TRANS_READ];
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ulight_fifo_mm_interconnect_0_router_default_decode the_default_decode(
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.default_destination_id (default_destid),
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.default_wr_channel (),
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.default_rd_channel (),
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.default_src_channel (default_src_channel)
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);
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always @* begin
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src_data = sink_data;
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src_channel = default_src_channel;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
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// --------------------------------------------------
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// Address Decoder
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// Sets the channel and destination ID based on the address
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// --------------------------------------------------
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// ( 0x0 .. 0x10 )
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if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h0 ) begin
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src_channel = 22'b0000000000000000000001;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
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end
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// ( 0x10000 .. 0x10010 )
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if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h10000 && read_transaction ) begin
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src_channel = 22'b0000000000000000000010;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16;
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end
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// ( 0x1a000 .. 0x1a010 )
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if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h1a000 && read_transaction ) begin
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src_channel = 22'b0000010000000000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 19;
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end
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// ( 0x20000 .. 0x20010 )
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if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h20000 && read_transaction ) begin
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src_channel = 22'b0000000000000000000100;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
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end
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// ( 0x2a000 .. 0x2a010 )
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if ( {address[RG:PAD4],{PAD4{1'b0}}} == 20'h2a000 && read_transaction ) begin
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src_channel = 22'b0000100000000000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
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end
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// ( 0x30000 .. 0x30010 )
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if ( {address[RG:PAD5],{PAD5{1'b0}}} == 20'h30000 && read_transaction ) begin
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src_channel = 22'b0000000000000000001000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
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end
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// ( 0x3a000 .. 0x3a010 )
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if ( {address[RG:PAD6],{PAD6{1'b0}}} == 20'h3a000 ) begin
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src_channel = 22'b0001000000000000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
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end
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// ( 0x40000 .. 0x40010 )
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if ( {address[RG:PAD7],{PAD7{1'b0}}} == 20'h40000 ) begin
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src_channel = 22'b0000000000000000010000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
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end
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264 |
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// ( 0x4a000 .. 0x4a010 )
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if ( {address[RG:PAD8],{PAD8{1'b0}}} == 20'h4a000 && read_transaction ) begin
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src_channel = 22'b0010000000000000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
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end
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// ( 0x50000 .. 0x50010 )
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if ( {address[RG:PAD9],{PAD9{1'b0}}} == 20'h50000 && read_transaction ) begin
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src_channel = 22'b0000000000000000100000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
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end
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276 |
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277 |
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// ( 0x5a000 .. 0x5a010 )
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278 |
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if ( {address[RG:PAD10],{PAD10{1'b0}}} == 20'h5a000 && read_transaction ) begin
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src_channel = 22'b0100000000000000000000;
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280 |
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
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end
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282 |
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283 |
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// ( 0x60000 .. 0x60010 )
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284 |
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if ( {address[RG:PAD11],{PAD11{1'b0}}} == 20'h60000 && read_transaction ) begin
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285 |
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src_channel = 22'b0000000000000001000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
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287 |
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end
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288 |
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289 |
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// ( 0x6a000 .. 0x6a010 )
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290 |
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if ( {address[RG:PAD12],{PAD12{1'b0}}} == 20'h6a000 && read_transaction ) begin
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291 |
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src_channel = 22'b1000000000000000000000;
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292 |
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
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end
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294 |
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295 |
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// ( 0x70000 .. 0x70010 )
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296 |
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if ( {address[RG:PAD13],{PAD13{1'b0}}} == 20'h70000 ) begin
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297 |
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src_channel = 22'b0000000000000010000000;
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298 |
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
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end
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300 |
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// ( 0x80000 .. 0x80010 )
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302 |
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if ( {address[RG:PAD14],{PAD14{1'b0}}} == 20'h80000 ) begin
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303 |
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src_channel = 22'b0000000000000100000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
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305 |
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end
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306 |
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307 |
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// ( 0x90000 .. 0x90010 )
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308 |
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if ( {address[RG:PAD15],{PAD15{1'b0}}} == 20'h90000 ) begin
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src_channel = 22'b0000000000001000000000;
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
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311 |
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end
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312 |
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313 |
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// ( 0xa0000 .. 0xa0010 )
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314 |
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if ( {address[RG:PAD16],{PAD16{1'b0}}} == 20'ha0000 ) begin
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315 |
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src_channel = 22'b0000000000010000000000;
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316 |
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src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 20;
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317 |
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end
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318 |
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319 |
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// ( 0xb0000 .. 0xb0010 )
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320 |
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if ( {address[RG:PAD17],{PAD17{1'b0}}} == 20'hb0000 ) begin
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321 |
|
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src_channel = 22'b0000000000100000000000;
|
322 |
|
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 21;
|
323 |
|
|
end
|
324 |
|
|
|
325 |
|
|
// ( 0xc0000 .. 0xc0010 )
|
326 |
|
|
if ( {address[RG:PAD18],{PAD18{1'b0}}} == 20'hc0000 && read_transaction ) begin
|
327 |
|
|
src_channel = 22'b0000000001000000000000;
|
328 |
|
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
|
329 |
|
|
end
|
330 |
|
|
|
331 |
|
|
// ( 0xd0000 .. 0xd0010 )
|
332 |
|
|
if ( {address[RG:PAD19],{PAD19{1'b0}}} == 20'hd0000 && read_transaction ) begin
|
333 |
|
|
src_channel = 22'b0000000010000000000000;
|
334 |
|
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
// ( 0xe0000 .. 0xe0010 )
|
338 |
|
|
if ( {address[RG:PAD20],{PAD20{1'b0}}} == 20'he0000 ) begin
|
339 |
|
|
src_channel = 22'b0000000100000000000000;
|
340 |
|
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17;
|
341 |
|
|
end
|
342 |
|
|
|
343 |
|
|
// ( 0xf0000 .. 0xf0010 )
|
344 |
|
|
if ( {address[RG:PAD21],{PAD21{1'b0}}} == 20'hf0000 ) begin
|
345 |
|
|
src_channel = 22'b0000001000000000000000;
|
346 |
|
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 18;
|
347 |
|
|
end
|
348 |
|
|
|
349 |
|
|
end
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
// --------------------------------------------------
|
353 |
|
|
// Ceil(log2()) function
|
354 |
|
|
// --------------------------------------------------
|
355 |
|
|
function integer log2ceil;
|
356 |
|
|
input reg[65:0] val;
|
357 |
|
|
reg [65:0] i;
|
358 |
|
|
|
359 |
|
|
begin
|
360 |
|
|
i = 1;
|
361 |
|
|
log2ceil = 0;
|
362 |
|
|
|
363 |
|
|
while (i < val) begin
|
364 |
|
|
log2ceil = log2ceil + 1;
|
365 |
|
|
i = i << 1;
|
366 |
|
|
end
|
367 |
|
|
end
|
368 |
|
|
endfunction
|
369 |
|
|
|
370 |
|
|
endmodule
|
371 |
|
|
|
372 |
|
|
|