| 1 |
32 |
redbear |
// ulight_fifo.v
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| 2 |
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| 3 |
40 |
redbear |
// Generated using ACDS version 17.1 593
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| 4 |
32 |
redbear |
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| 5 |
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`timescale 1 ps / 1 ps
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| 6 |
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module ulight_fifo (
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| 7 |
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output wire auto_start_external_connection_export, // auto_start_external_connection.export
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| 8 |
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input wire clk_clk, // clk.clk
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| 9 |
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output wire [2:0] clock_sel_external_connection_export, // clock_sel_external_connection.export
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| 10 |
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input wire [5:0] counter_rx_fifo_external_connection_export, // counter_rx_fifo_external_connection.export
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| 11 |
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input wire [5:0] counter_tx_fifo_external_connection_export, // counter_tx_fifo_external_connection.export
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| 12 |
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input wire [8:0] data_flag_rx_external_connection_export, // data_flag_rx_external_connection.export
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| 13 |
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input wire [13:0] data_info_external_connection_export, // data_info_external_connection.export
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| 14 |
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output wire data_read_en_rx_external_connection_export, // data_read_en_rx_external_connection.export
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| 15 |
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input wire fifo_empty_rx_status_external_connection_export, // fifo_empty_rx_status_external_connection.export
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| 16 |
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input wire fifo_empty_tx_status_external_connection_export, // fifo_empty_tx_status_external_connection.export
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| 17 |
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input wire fifo_full_rx_status_external_connection_export, // fifo_full_rx_status_external_connection.export
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| 18 |
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input wire fifo_full_tx_status_external_connection_export, // fifo_full_tx_status_external_connection.export
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| 19 |
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input wire [5:0] fsm_info_external_connection_export, // fsm_info_external_connection.export
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| 20 |
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output wire [4:0] led_pio_test_external_connection_export, // led_pio_test_external_connection.export
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| 21 |
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output wire link_disable_external_connection_export, // link_disable_external_connection.export
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| 22 |
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output wire link_start_external_connection_export, // link_start_external_connection.export
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| 23 |
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output wire [12:0] memory_mem_a, // memory.mem_a
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| 24 |
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output wire [2:0] memory_mem_ba, // .mem_ba
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| 25 |
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output wire memory_mem_ck, // .mem_ck
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| 26 |
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output wire memory_mem_ck_n, // .mem_ck_n
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| 27 |
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output wire memory_mem_cke, // .mem_cke
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| 28 |
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output wire memory_mem_cs_n, // .mem_cs_n
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| 29 |
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output wire memory_mem_ras_n, // .mem_ras_n
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| 30 |
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output wire memory_mem_cas_n, // .mem_cas_n
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| 31 |
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output wire memory_mem_we_n, // .mem_we_n
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| 32 |
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output wire memory_mem_reset_n, // .mem_reset_n
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| 33 |
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inout wire [7:0] memory_mem_dq, // .mem_dq
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| 34 |
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inout wire memory_mem_dqs, // .mem_dqs
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| 35 |
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inout wire memory_mem_dqs_n, // .mem_dqs_n
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| 36 |
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output wire memory_mem_odt, // .mem_odt
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| 37 |
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output wire memory_mem_dm, // .mem_dm
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| 38 |
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input wire memory_oct_rzqin, // .oct_rzqin
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| 39 |
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output wire pll_0_locked_export, // pll_0_locked.export
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| 40 |
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output wire pll_0_outclk0_clk, // pll_0_outclk0.clk
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| 41 |
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input wire reset_reset_n, // reset.reset_n
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| 42 |
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input wire timecode_ready_rx_external_connection_export, // timecode_ready_rx_external_connection.export
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| 43 |
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input wire [7:0] timecode_rx_external_connection_export, // timecode_rx_external_connection.export
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| 44 |
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output wire [7:0] timecode_tx_data_external_connection_export, // timecode_tx_data_external_connection.export
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| 45 |
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output wire timecode_tx_enable_external_connection_export, // timecode_tx_enable_external_connection.export
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| 46 |
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input wire timecode_tx_ready_external_connection_export, // timecode_tx_ready_external_connection.export
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| 47 |
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output wire [8:0] write_data_fifo_tx_external_connection_export, // write_data_fifo_tx_external_connection.export
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| 48 |
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output wire write_en_tx_external_connection_export // write_en_tx_external_connection.export
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| 49 |
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);
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| 50 |
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| 51 |
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wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
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| 52 |
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wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
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| 53 |
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wire [3:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
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| 54 |
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wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
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| 55 |
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wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
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| 56 |
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wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
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| 57 |
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wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
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| 58 |
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wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
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| 59 |
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wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
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| 60 |
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wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
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| 61 |
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wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
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| 62 |
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wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
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| 63 |
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wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
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| 64 |
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wire [31:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
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| 65 |
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wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
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| 66 |
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wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
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| 67 |
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wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
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| 68 |
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wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
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| 69 |
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wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
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| 70 |
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wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
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| 71 |
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wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
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| 72 |
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wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
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| 73 |
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wire [31:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
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| 74 |
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wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
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| 75 |
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wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
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| 76 |
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wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
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| 77 |
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wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
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| 78 |
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wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
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| 79 |
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wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
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| 80 |
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wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
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| 81 |
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wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
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| 82 |
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wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
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| 83 |
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wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
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| 84 |
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wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
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| 85 |
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wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
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| 86 |
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wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
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| 87 |
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wire mm_interconnect_0_led_pio_test_s1_chipselect; // mm_interconnect_0:led_pio_test_s1_chipselect -> led_pio_test:chipselect
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| 88 |
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wire [31:0] mm_interconnect_0_led_pio_test_s1_readdata; // led_pio_test:readdata -> mm_interconnect_0:led_pio_test_s1_readdata
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| 89 |
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wire [1:0] mm_interconnect_0_led_pio_test_s1_address; // mm_interconnect_0:led_pio_test_s1_address -> led_pio_test:address
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| 90 |
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wire mm_interconnect_0_led_pio_test_s1_write; // mm_interconnect_0:led_pio_test_s1_write -> led_pio_test:write_n
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| 91 |
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wire [31:0] mm_interconnect_0_led_pio_test_s1_writedata; // mm_interconnect_0:led_pio_test_s1_writedata -> led_pio_test:writedata
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| 92 |
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wire [31:0] mm_interconnect_0_timecode_rx_s1_readdata; // timecode_rx:readdata -> mm_interconnect_0:timecode_rx_s1_readdata
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| 93 |
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wire [1:0] mm_interconnect_0_timecode_rx_s1_address; // mm_interconnect_0:timecode_rx_s1_address -> timecode_rx:address
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| 94 |
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wire [31:0] mm_interconnect_0_timecode_ready_rx_s1_readdata; // timecode_ready_rx:readdata -> mm_interconnect_0:timecode_ready_rx_s1_readdata
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| 95 |
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wire [1:0] mm_interconnect_0_timecode_ready_rx_s1_address; // mm_interconnect_0:timecode_ready_rx_s1_address -> timecode_ready_rx:address
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| 96 |
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wire [31:0] mm_interconnect_0_data_flag_rx_s1_readdata; // data_flag_rx:readdata -> mm_interconnect_0:data_flag_rx_s1_readdata
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| 97 |
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wire [1:0] mm_interconnect_0_data_flag_rx_s1_address; // mm_interconnect_0:data_flag_rx_s1_address -> data_flag_rx:address
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| 98 |
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wire mm_interconnect_0_data_read_en_rx_s1_chipselect; // mm_interconnect_0:data_read_en_rx_s1_chipselect -> data_read_en_rx:chipselect
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| 99 |
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wire [31:0] mm_interconnect_0_data_read_en_rx_s1_readdata; // data_read_en_rx:readdata -> mm_interconnect_0:data_read_en_rx_s1_readdata
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| 100 |
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wire [1:0] mm_interconnect_0_data_read_en_rx_s1_address; // mm_interconnect_0:data_read_en_rx_s1_address -> data_read_en_rx:address
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| 101 |
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wire mm_interconnect_0_data_read_en_rx_s1_write; // mm_interconnect_0:data_read_en_rx_s1_write -> data_read_en_rx:write_n
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| 102 |
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wire [31:0] mm_interconnect_0_data_read_en_rx_s1_writedata; // mm_interconnect_0:data_read_en_rx_s1_writedata -> data_read_en_rx:writedata
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| 103 |
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wire [31:0] mm_interconnect_0_fifo_full_rx_status_s1_readdata; // fifo_full_rx_status:readdata -> mm_interconnect_0:fifo_full_rx_status_s1_readdata
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| 104 |
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wire [1:0] mm_interconnect_0_fifo_full_rx_status_s1_address; // mm_interconnect_0:fifo_full_rx_status_s1_address -> fifo_full_rx_status:address
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| 105 |
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wire [31:0] mm_interconnect_0_fifo_empty_rx_status_s1_readdata; // fifo_empty_rx_status:readdata -> mm_interconnect_0:fifo_empty_rx_status_s1_readdata
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| 106 |
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wire [1:0] mm_interconnect_0_fifo_empty_rx_status_s1_address; // mm_interconnect_0:fifo_empty_rx_status_s1_address -> fifo_empty_rx_status:address
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| 107 |
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wire mm_interconnect_0_link_start_s1_chipselect; // mm_interconnect_0:link_start_s1_chipselect -> link_start:chipselect
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| 108 |
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wire [31:0] mm_interconnect_0_link_start_s1_readdata; // link_start:readdata -> mm_interconnect_0:link_start_s1_readdata
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| 109 |
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wire [1:0] mm_interconnect_0_link_start_s1_address; // mm_interconnect_0:link_start_s1_address -> link_start:address
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| 110 |
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wire mm_interconnect_0_link_start_s1_write; // mm_interconnect_0:link_start_s1_write -> link_start:write_n
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| 111 |
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wire [31:0] mm_interconnect_0_link_start_s1_writedata; // mm_interconnect_0:link_start_s1_writedata -> link_start:writedata
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| 112 |
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wire mm_interconnect_0_auto_start_s1_chipselect; // mm_interconnect_0:auto_start_s1_chipselect -> auto_start:chipselect
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| 113 |
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wire [31:0] mm_interconnect_0_auto_start_s1_readdata; // auto_start:readdata -> mm_interconnect_0:auto_start_s1_readdata
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| 114 |
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wire [1:0] mm_interconnect_0_auto_start_s1_address; // mm_interconnect_0:auto_start_s1_address -> auto_start:address
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| 115 |
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wire mm_interconnect_0_auto_start_s1_write; // mm_interconnect_0:auto_start_s1_write -> auto_start:write_n
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| 116 |
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wire [31:0] mm_interconnect_0_auto_start_s1_writedata; // mm_interconnect_0:auto_start_s1_writedata -> auto_start:writedata
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| 117 |
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wire mm_interconnect_0_link_disable_s1_chipselect; // mm_interconnect_0:link_disable_s1_chipselect -> link_disable:chipselect
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| 118 |
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wire [31:0] mm_interconnect_0_link_disable_s1_readdata; // link_disable:readdata -> mm_interconnect_0:link_disable_s1_readdata
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| 119 |
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wire [1:0] mm_interconnect_0_link_disable_s1_address; // mm_interconnect_0:link_disable_s1_address -> link_disable:address
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| 120 |
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wire mm_interconnect_0_link_disable_s1_write; // mm_interconnect_0:link_disable_s1_write -> link_disable:write_n
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| 121 |
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wire [31:0] mm_interconnect_0_link_disable_s1_writedata; // mm_interconnect_0:link_disable_s1_writedata -> link_disable:writedata
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| 122 |
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wire mm_interconnect_0_write_data_fifo_tx_s1_chipselect; // mm_interconnect_0:write_data_fifo_tx_s1_chipselect -> write_data_fifo_tx:chipselect
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| 123 |
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wire [31:0] mm_interconnect_0_write_data_fifo_tx_s1_readdata; // write_data_fifo_tx:readdata -> mm_interconnect_0:write_data_fifo_tx_s1_readdata
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| 124 |
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wire [1:0] mm_interconnect_0_write_data_fifo_tx_s1_address; // mm_interconnect_0:write_data_fifo_tx_s1_address -> write_data_fifo_tx:address
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| 125 |
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wire mm_interconnect_0_write_data_fifo_tx_s1_write; // mm_interconnect_0:write_data_fifo_tx_s1_write -> write_data_fifo_tx:write_n
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| 126 |
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wire [31:0] mm_interconnect_0_write_data_fifo_tx_s1_writedata; // mm_interconnect_0:write_data_fifo_tx_s1_writedata -> write_data_fifo_tx:writedata
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| 127 |
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wire mm_interconnect_0_write_en_tx_s1_chipselect; // mm_interconnect_0:write_en_tx_s1_chipselect -> write_en_tx:chipselect
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| 128 |
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wire [31:0] mm_interconnect_0_write_en_tx_s1_readdata; // write_en_tx:readdata -> mm_interconnect_0:write_en_tx_s1_readdata
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| 129 |
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wire [1:0] mm_interconnect_0_write_en_tx_s1_address; // mm_interconnect_0:write_en_tx_s1_address -> write_en_tx:address
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| 130 |
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wire mm_interconnect_0_write_en_tx_s1_write; // mm_interconnect_0:write_en_tx_s1_write -> write_en_tx:write_n
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| 131 |
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wire [31:0] mm_interconnect_0_write_en_tx_s1_writedata; // mm_interconnect_0:write_en_tx_s1_writedata -> write_en_tx:writedata
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| 132 |
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wire [31:0] mm_interconnect_0_fifo_full_tx_status_s1_readdata; // fifo_full_tx_status:readdata -> mm_interconnect_0:fifo_full_tx_status_s1_readdata
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| 133 |
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wire [1:0] mm_interconnect_0_fifo_full_tx_status_s1_address; // mm_interconnect_0:fifo_full_tx_status_s1_address -> fifo_full_tx_status:address
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| 134 |
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wire [31:0] mm_interconnect_0_fifo_empty_tx_status_s1_readdata; // fifo_empty_tx_status:readdata -> mm_interconnect_0:fifo_empty_tx_status_s1_readdata
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| 135 |
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wire [1:0] mm_interconnect_0_fifo_empty_tx_status_s1_address; // mm_interconnect_0:fifo_empty_tx_status_s1_address -> fifo_empty_tx_status:address
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| 136 |
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wire mm_interconnect_0_timecode_tx_data_s1_chipselect; // mm_interconnect_0:timecode_tx_data_s1_chipselect -> timecode_tx_data:chipselect
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| 137 |
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wire [31:0] mm_interconnect_0_timecode_tx_data_s1_readdata; // timecode_tx_data:readdata -> mm_interconnect_0:timecode_tx_data_s1_readdata
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| 138 |
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wire [1:0] mm_interconnect_0_timecode_tx_data_s1_address; // mm_interconnect_0:timecode_tx_data_s1_address -> timecode_tx_data:address
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| 139 |
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wire mm_interconnect_0_timecode_tx_data_s1_write; // mm_interconnect_0:timecode_tx_data_s1_write -> timecode_tx_data:write_n
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| 140 |
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wire [31:0] mm_interconnect_0_timecode_tx_data_s1_writedata; // mm_interconnect_0:timecode_tx_data_s1_writedata -> timecode_tx_data:writedata
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| 141 |
|
|
wire mm_interconnect_0_timecode_tx_enable_s1_chipselect; // mm_interconnect_0:timecode_tx_enable_s1_chipselect -> timecode_tx_enable:chipselect
|
| 142 |
|
|
wire [31:0] mm_interconnect_0_timecode_tx_enable_s1_readdata; // timecode_tx_enable:readdata -> mm_interconnect_0:timecode_tx_enable_s1_readdata
|
| 143 |
|
|
wire [1:0] mm_interconnect_0_timecode_tx_enable_s1_address; // mm_interconnect_0:timecode_tx_enable_s1_address -> timecode_tx_enable:address
|
| 144 |
|
|
wire mm_interconnect_0_timecode_tx_enable_s1_write; // mm_interconnect_0:timecode_tx_enable_s1_write -> timecode_tx_enable:write_n
|
| 145 |
|
|
wire [31:0] mm_interconnect_0_timecode_tx_enable_s1_writedata; // mm_interconnect_0:timecode_tx_enable_s1_writedata -> timecode_tx_enable:writedata
|
| 146 |
|
|
wire [31:0] mm_interconnect_0_timecode_tx_ready_s1_readdata; // timecode_tx_ready:readdata -> mm_interconnect_0:timecode_tx_ready_s1_readdata
|
| 147 |
|
|
wire [1:0] mm_interconnect_0_timecode_tx_ready_s1_address; // mm_interconnect_0:timecode_tx_ready_s1_address -> timecode_tx_ready:address
|
| 148 |
|
|
wire [31:0] mm_interconnect_0_data_info_s1_readdata; // data_info:readdata -> mm_interconnect_0:data_info_s1_readdata
|
| 149 |
|
|
wire [1:0] mm_interconnect_0_data_info_s1_address; // mm_interconnect_0:data_info_s1_address -> data_info:address
|
| 150 |
|
|
wire mm_interconnect_0_clock_sel_s1_chipselect; // mm_interconnect_0:clock_sel_s1_chipselect -> clock_sel:chipselect
|
| 151 |
|
|
wire [31:0] mm_interconnect_0_clock_sel_s1_readdata; // clock_sel:readdata -> mm_interconnect_0:clock_sel_s1_readdata
|
| 152 |
|
|
wire [1:0] mm_interconnect_0_clock_sel_s1_address; // mm_interconnect_0:clock_sel_s1_address -> clock_sel:address
|
| 153 |
|
|
wire mm_interconnect_0_clock_sel_s1_write; // mm_interconnect_0:clock_sel_s1_write -> clock_sel:write_n
|
| 154 |
|
|
wire [31:0] mm_interconnect_0_clock_sel_s1_writedata; // mm_interconnect_0:clock_sel_s1_writedata -> clock_sel:writedata
|
| 155 |
|
|
wire [31:0] mm_interconnect_0_fsm_info_s1_readdata; // fsm_info:readdata -> mm_interconnect_0:fsm_info_s1_readdata
|
| 156 |
|
|
wire [1:0] mm_interconnect_0_fsm_info_s1_address; // mm_interconnect_0:fsm_info_s1_address -> fsm_info:address
|
| 157 |
|
|
wire [31:0] mm_interconnect_0_counter_tx_fifo_s1_readdata; // counter_tx_fifo:readdata -> mm_interconnect_0:counter_tx_fifo_s1_readdata
|
| 158 |
|
|
wire [1:0] mm_interconnect_0_counter_tx_fifo_s1_address; // mm_interconnect_0:counter_tx_fifo_s1_address -> counter_tx_fifo:address
|
| 159 |
|
|
wire [31:0] mm_interconnect_0_counter_rx_fifo_s1_readdata; // counter_rx_fifo:readdata -> mm_interconnect_0:counter_rx_fifo_s1_readdata
|
| 160 |
|
|
wire [1:0] mm_interconnect_0_counter_rx_fifo_s1_address; // mm_interconnect_0:counter_rx_fifo_s1_address -> counter_rx_fifo:address
|
| 161 |
|
|
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [auto_start:reset_n, clock_sel:reset_n, counter_rx_fifo:reset_n, counter_tx_fifo:reset_n, data_flag_rx:reset_n, data_info:reset_n, data_read_en_rx:reset_n, fifo_empty_rx_status:reset_n, fifo_empty_tx_status:reset_n, fifo_full_rx_status:reset_n, fifo_full_tx_status:reset_n, fsm_info:reset_n, led_pio_test:reset_n, link_disable:reset_n, link_start:reset_n, mm_interconnect_0:led_pio_test_reset_reset_bridge_in_reset_reset, timecode_ready_rx:reset_n, timecode_rx:reset_n, timecode_tx_data:reset_n, timecode_tx_enable:reset_n, timecode_tx_ready:reset_n, write_data_fifo_tx:reset_n, write_en_tx:reset_n]
|
| 162 |
|
|
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
|
| 163 |
|
|
wire hps_0_h2f_reset_reset; // hps_0:h2f_rst_n -> rst_controller_001:reset_in0
|
| 164 |
|
|
|
| 165 |
|
|
ulight_fifo_auto_start auto_start (
|
| 166 |
|
|
.clk (clk_clk), // clk.clk
|
| 167 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 168 |
|
|
.address (mm_interconnect_0_auto_start_s1_address), // s1.address
|
| 169 |
|
|
.write_n (~mm_interconnect_0_auto_start_s1_write), // .write_n
|
| 170 |
|
|
.writedata (mm_interconnect_0_auto_start_s1_writedata), // .writedata
|
| 171 |
|
|
.chipselect (mm_interconnect_0_auto_start_s1_chipselect), // .chipselect
|
| 172 |
|
|
.readdata (mm_interconnect_0_auto_start_s1_readdata), // .readdata
|
| 173 |
|
|
.out_port (auto_start_external_connection_export) // external_connection.export
|
| 174 |
|
|
);
|
| 175 |
|
|
|
| 176 |
|
|
ulight_fifo_clock_sel clock_sel (
|
| 177 |
|
|
.clk (clk_clk), // clk.clk
|
| 178 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 179 |
|
|
.address (mm_interconnect_0_clock_sel_s1_address), // s1.address
|
| 180 |
|
|
.write_n (~mm_interconnect_0_clock_sel_s1_write), // .write_n
|
| 181 |
|
|
.writedata (mm_interconnect_0_clock_sel_s1_writedata), // .writedata
|
| 182 |
|
|
.chipselect (mm_interconnect_0_clock_sel_s1_chipselect), // .chipselect
|
| 183 |
|
|
.readdata (mm_interconnect_0_clock_sel_s1_readdata), // .readdata
|
| 184 |
|
|
.out_port (clock_sel_external_connection_export) // external_connection.export
|
| 185 |
|
|
);
|
| 186 |
|
|
|
| 187 |
|
|
ulight_fifo_counter_rx_fifo counter_rx_fifo (
|
| 188 |
|
|
.clk (clk_clk), // clk.clk
|
| 189 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 190 |
|
|
.address (mm_interconnect_0_counter_rx_fifo_s1_address), // s1.address
|
| 191 |
|
|
.readdata (mm_interconnect_0_counter_rx_fifo_s1_readdata), // .readdata
|
| 192 |
|
|
.in_port (counter_rx_fifo_external_connection_export) // external_connection.export
|
| 193 |
|
|
);
|
| 194 |
|
|
|
| 195 |
|
|
ulight_fifo_counter_rx_fifo counter_tx_fifo (
|
| 196 |
|
|
.clk (clk_clk), // clk.clk
|
| 197 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 198 |
|
|
.address (mm_interconnect_0_counter_tx_fifo_s1_address), // s1.address
|
| 199 |
|
|
.readdata (mm_interconnect_0_counter_tx_fifo_s1_readdata), // .readdata
|
| 200 |
|
|
.in_port (counter_tx_fifo_external_connection_export) // external_connection.export
|
| 201 |
|
|
);
|
| 202 |
|
|
|
| 203 |
|
|
ulight_fifo_data_flag_rx data_flag_rx (
|
| 204 |
|
|
.clk (clk_clk), // clk.clk
|
| 205 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 206 |
|
|
.address (mm_interconnect_0_data_flag_rx_s1_address), // s1.address
|
| 207 |
|
|
.readdata (mm_interconnect_0_data_flag_rx_s1_readdata), // .readdata
|
| 208 |
|
|
.in_port (data_flag_rx_external_connection_export) // external_connection.export
|
| 209 |
|
|
);
|
| 210 |
|
|
|
| 211 |
|
|
ulight_fifo_data_info data_info (
|
| 212 |
|
|
.clk (clk_clk), // clk.clk
|
| 213 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 214 |
|
|
.address (mm_interconnect_0_data_info_s1_address), // s1.address
|
| 215 |
|
|
.readdata (mm_interconnect_0_data_info_s1_readdata), // .readdata
|
| 216 |
|
|
.in_port (data_info_external_connection_export) // external_connection.export
|
| 217 |
|
|
);
|
| 218 |
|
|
|
| 219 |
|
|
ulight_fifo_auto_start data_read_en_rx (
|
| 220 |
|
|
.clk (clk_clk), // clk.clk
|
| 221 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 222 |
|
|
.address (mm_interconnect_0_data_read_en_rx_s1_address), // s1.address
|
| 223 |
|
|
.write_n (~mm_interconnect_0_data_read_en_rx_s1_write), // .write_n
|
| 224 |
|
|
.writedata (mm_interconnect_0_data_read_en_rx_s1_writedata), // .writedata
|
| 225 |
|
|
.chipselect (mm_interconnect_0_data_read_en_rx_s1_chipselect), // .chipselect
|
| 226 |
|
|
.readdata (mm_interconnect_0_data_read_en_rx_s1_readdata), // .readdata
|
| 227 |
|
|
.out_port (data_read_en_rx_external_connection_export) // external_connection.export
|
| 228 |
|
|
);
|
| 229 |
|
|
|
| 230 |
|
|
ulight_fifo_fifo_empty_rx_status fifo_empty_rx_status (
|
| 231 |
|
|
.clk (clk_clk), // clk.clk
|
| 232 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 233 |
|
|
.address (mm_interconnect_0_fifo_empty_rx_status_s1_address), // s1.address
|
| 234 |
|
|
.readdata (mm_interconnect_0_fifo_empty_rx_status_s1_readdata), // .readdata
|
| 235 |
|
|
.in_port (fifo_empty_rx_status_external_connection_export) // external_connection.export
|
| 236 |
|
|
);
|
| 237 |
|
|
|
| 238 |
|
|
ulight_fifo_fifo_empty_rx_status fifo_empty_tx_status (
|
| 239 |
|
|
.clk (clk_clk), // clk.clk
|
| 240 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 241 |
|
|
.address (mm_interconnect_0_fifo_empty_tx_status_s1_address), // s1.address
|
| 242 |
|
|
.readdata (mm_interconnect_0_fifo_empty_tx_status_s1_readdata), // .readdata
|
| 243 |
|
|
.in_port (fifo_empty_tx_status_external_connection_export) // external_connection.export
|
| 244 |
|
|
);
|
| 245 |
|
|
|
| 246 |
|
|
ulight_fifo_fifo_empty_rx_status fifo_full_rx_status (
|
| 247 |
|
|
.clk (clk_clk), // clk.clk
|
| 248 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 249 |
|
|
.address (mm_interconnect_0_fifo_full_rx_status_s1_address), // s1.address
|
| 250 |
|
|
.readdata (mm_interconnect_0_fifo_full_rx_status_s1_readdata), // .readdata
|
| 251 |
|
|
.in_port (fifo_full_rx_status_external_connection_export) // external_connection.export
|
| 252 |
|
|
);
|
| 253 |
|
|
|
| 254 |
|
|
ulight_fifo_fifo_empty_rx_status fifo_full_tx_status (
|
| 255 |
|
|
.clk (clk_clk), // clk.clk
|
| 256 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 257 |
|
|
.address (mm_interconnect_0_fifo_full_tx_status_s1_address), // s1.address
|
| 258 |
|
|
.readdata (mm_interconnect_0_fifo_full_tx_status_s1_readdata), // .readdata
|
| 259 |
|
|
.in_port (fifo_full_tx_status_external_connection_export) // external_connection.export
|
| 260 |
|
|
);
|
| 261 |
|
|
|
| 262 |
|
|
ulight_fifo_counter_rx_fifo fsm_info (
|
| 263 |
|
|
.clk (clk_clk), // clk.clk
|
| 264 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 265 |
|
|
.address (mm_interconnect_0_fsm_info_s1_address), // s1.address
|
| 266 |
|
|
.readdata (mm_interconnect_0_fsm_info_s1_readdata), // .readdata
|
| 267 |
|
|
.in_port (fsm_info_external_connection_export) // external_connection.export
|
| 268 |
|
|
);
|
| 269 |
|
|
|
| 270 |
|
|
ulight_fifo_hps_0 #(
|
| 271 |
|
|
.F2S_Width (0),
|
| 272 |
|
|
.S2F_Width (1)
|
| 273 |
|
|
) hps_0 (
|
| 274 |
|
|
.mem_a (memory_mem_a), // memory.mem_a
|
| 275 |
|
|
.mem_ba (memory_mem_ba), // .mem_ba
|
| 276 |
|
|
.mem_ck (memory_mem_ck), // .mem_ck
|
| 277 |
|
|
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
|
| 278 |
|
|
.mem_cke (memory_mem_cke), // .mem_cke
|
| 279 |
|
|
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
|
| 280 |
|
|
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
|
| 281 |
|
|
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
|
| 282 |
|
|
.mem_we_n (memory_mem_we_n), // .mem_we_n
|
| 283 |
|
|
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
|
| 284 |
|
|
.mem_dq (memory_mem_dq), // .mem_dq
|
| 285 |
|
|
.mem_dqs (memory_mem_dqs), // .mem_dqs
|
| 286 |
|
|
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
|
| 287 |
|
|
.mem_odt (memory_mem_odt), // .mem_odt
|
| 288 |
|
|
.mem_dm (memory_mem_dm), // .mem_dm
|
| 289 |
|
|
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
|
| 290 |
|
|
.h2f_rst_n (hps_0_h2f_reset_reset), // h2f_reset.reset_n
|
| 291 |
|
|
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
|
| 292 |
|
|
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
|
| 293 |
|
|
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
|
| 294 |
|
|
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
|
| 295 |
|
|
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
|
| 296 |
|
|
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
|
| 297 |
|
|
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
|
| 298 |
|
|
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
|
| 299 |
|
|
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
|
| 300 |
|
|
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
|
| 301 |
|
|
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
|
| 302 |
|
|
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
|
| 303 |
|
|
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
|
| 304 |
|
|
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
|
| 305 |
|
|
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
|
| 306 |
|
|
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
|
| 307 |
|
|
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
|
| 308 |
|
|
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
|
| 309 |
|
|
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
|
| 310 |
|
|
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
|
| 311 |
|
|
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
|
| 312 |
|
|
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
|
| 313 |
|
|
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
|
| 314 |
|
|
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
|
| 315 |
|
|
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
|
| 316 |
|
|
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
|
| 317 |
|
|
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
|
| 318 |
|
|
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
|
| 319 |
|
|
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
|
| 320 |
|
|
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
|
| 321 |
|
|
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
|
| 322 |
|
|
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
|
| 323 |
|
|
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
|
| 324 |
|
|
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
|
| 325 |
|
|
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
|
| 326 |
|
|
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
|
| 327 |
|
|
.h2f_RREADY (hps_0_h2f_axi_master_rready) // .rready
|
| 328 |
|
|
);
|
| 329 |
|
|
|
| 330 |
|
|
ulight_fifo_led_pio_test led_pio_test (
|
| 331 |
|
|
.clk (clk_clk), // clk.clk
|
| 332 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 333 |
|
|
.address (mm_interconnect_0_led_pio_test_s1_address), // s1.address
|
| 334 |
|
|
.write_n (~mm_interconnect_0_led_pio_test_s1_write), // .write_n
|
| 335 |
|
|
.writedata (mm_interconnect_0_led_pio_test_s1_writedata), // .writedata
|
| 336 |
|
|
.chipselect (mm_interconnect_0_led_pio_test_s1_chipselect), // .chipselect
|
| 337 |
|
|
.readdata (mm_interconnect_0_led_pio_test_s1_readdata), // .readdata
|
| 338 |
|
|
.out_port (led_pio_test_external_connection_export) // external_connection.export
|
| 339 |
|
|
);
|
| 340 |
|
|
|
| 341 |
|
|
ulight_fifo_auto_start link_disable (
|
| 342 |
|
|
.clk (clk_clk), // clk.clk
|
| 343 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 344 |
|
|
.address (mm_interconnect_0_link_disable_s1_address), // s1.address
|
| 345 |
|
|
.write_n (~mm_interconnect_0_link_disable_s1_write), // .write_n
|
| 346 |
|
|
.writedata (mm_interconnect_0_link_disable_s1_writedata), // .writedata
|
| 347 |
|
|
.chipselect (mm_interconnect_0_link_disable_s1_chipselect), // .chipselect
|
| 348 |
|
|
.readdata (mm_interconnect_0_link_disable_s1_readdata), // .readdata
|
| 349 |
|
|
.out_port (link_disable_external_connection_export) // external_connection.export
|
| 350 |
|
|
);
|
| 351 |
|
|
|
| 352 |
|
|
ulight_fifo_auto_start link_start (
|
| 353 |
|
|
.clk (clk_clk), // clk.clk
|
| 354 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 355 |
|
|
.address (mm_interconnect_0_link_start_s1_address), // s1.address
|
| 356 |
|
|
.write_n (~mm_interconnect_0_link_start_s1_write), // .write_n
|
| 357 |
|
|
.writedata (mm_interconnect_0_link_start_s1_writedata), // .writedata
|
| 358 |
|
|
.chipselect (mm_interconnect_0_link_start_s1_chipselect), // .chipselect
|
| 359 |
|
|
.readdata (mm_interconnect_0_link_start_s1_readdata), // .readdata
|
| 360 |
|
|
.out_port (link_start_external_connection_export) // external_connection.export
|
| 361 |
|
|
);
|
| 362 |
|
|
|
| 363 |
|
|
ulight_fifo_pll_0 pll_0 (
|
| 364 |
|
|
.refclk (clk_clk), // refclk.clk
|
| 365 |
|
|
.rst (~reset_reset_n), // reset.reset
|
| 366 |
|
|
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
|
| 367 |
|
|
.locked (pll_0_locked_export), // locked.export
|
| 368 |
|
|
.refclk1 () // refclk1.refclk1
|
| 369 |
|
|
);
|
| 370 |
|
|
|
| 371 |
|
|
ulight_fifo_fifo_empty_rx_status timecode_ready_rx (
|
| 372 |
|
|
.clk (clk_clk), // clk.clk
|
| 373 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 374 |
|
|
.address (mm_interconnect_0_timecode_ready_rx_s1_address), // s1.address
|
| 375 |
|
|
.readdata (mm_interconnect_0_timecode_ready_rx_s1_readdata), // .readdata
|
| 376 |
|
|
.in_port (timecode_ready_rx_external_connection_export) // external_connection.export
|
| 377 |
|
|
);
|
| 378 |
|
|
|
| 379 |
|
|
ulight_fifo_timecode_rx timecode_rx (
|
| 380 |
|
|
.clk (clk_clk), // clk.clk
|
| 381 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 382 |
|
|
.address (mm_interconnect_0_timecode_rx_s1_address), // s1.address
|
| 383 |
|
|
.readdata (mm_interconnect_0_timecode_rx_s1_readdata), // .readdata
|
| 384 |
|
|
.in_port (timecode_rx_external_connection_export) // external_connection.export
|
| 385 |
|
|
);
|
| 386 |
|
|
|
| 387 |
|
|
ulight_fifo_timecode_tx_data timecode_tx_data (
|
| 388 |
|
|
.clk (clk_clk), // clk.clk
|
| 389 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 390 |
|
|
.address (mm_interconnect_0_timecode_tx_data_s1_address), // s1.address
|
| 391 |
|
|
.write_n (~mm_interconnect_0_timecode_tx_data_s1_write), // .write_n
|
| 392 |
|
|
.writedata (mm_interconnect_0_timecode_tx_data_s1_writedata), // .writedata
|
| 393 |
|
|
.chipselect (mm_interconnect_0_timecode_tx_data_s1_chipselect), // .chipselect
|
| 394 |
|
|
.readdata (mm_interconnect_0_timecode_tx_data_s1_readdata), // .readdata
|
| 395 |
|
|
.out_port (timecode_tx_data_external_connection_export) // external_connection.export
|
| 396 |
|
|
);
|
| 397 |
|
|
|
| 398 |
|
|
ulight_fifo_auto_start timecode_tx_enable (
|
| 399 |
|
|
.clk (clk_clk), // clk.clk
|
| 400 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 401 |
|
|
.address (mm_interconnect_0_timecode_tx_enable_s1_address), // s1.address
|
| 402 |
|
|
.write_n (~mm_interconnect_0_timecode_tx_enable_s1_write), // .write_n
|
| 403 |
|
|
.writedata (mm_interconnect_0_timecode_tx_enable_s1_writedata), // .writedata
|
| 404 |
|
|
.chipselect (mm_interconnect_0_timecode_tx_enable_s1_chipselect), // .chipselect
|
| 405 |
|
|
.readdata (mm_interconnect_0_timecode_tx_enable_s1_readdata), // .readdata
|
| 406 |
|
|
.out_port (timecode_tx_enable_external_connection_export) // external_connection.export
|
| 407 |
|
|
);
|
| 408 |
|
|
|
| 409 |
|
|
ulight_fifo_fifo_empty_rx_status timecode_tx_ready (
|
| 410 |
|
|
.clk (clk_clk), // clk.clk
|
| 411 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 412 |
|
|
.address (mm_interconnect_0_timecode_tx_ready_s1_address), // s1.address
|
| 413 |
|
|
.readdata (mm_interconnect_0_timecode_tx_ready_s1_readdata), // .readdata
|
| 414 |
|
|
.in_port (timecode_tx_ready_external_connection_export) // external_connection.export
|
| 415 |
|
|
);
|
| 416 |
|
|
|
| 417 |
|
|
ulight_fifo_write_data_fifo_tx write_data_fifo_tx (
|
| 418 |
|
|
.clk (clk_clk), // clk.clk
|
| 419 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 420 |
|
|
.address (mm_interconnect_0_write_data_fifo_tx_s1_address), // s1.address
|
| 421 |
|
|
.write_n (~mm_interconnect_0_write_data_fifo_tx_s1_write), // .write_n
|
| 422 |
|
|
.writedata (mm_interconnect_0_write_data_fifo_tx_s1_writedata), // .writedata
|
| 423 |
|
|
.chipselect (mm_interconnect_0_write_data_fifo_tx_s1_chipselect), // .chipselect
|
| 424 |
|
|
.readdata (mm_interconnect_0_write_data_fifo_tx_s1_readdata), // .readdata
|
| 425 |
|
|
.out_port (write_data_fifo_tx_external_connection_export) // external_connection.export
|
| 426 |
|
|
);
|
| 427 |
|
|
|
| 428 |
|
|
ulight_fifo_auto_start write_en_tx (
|
| 429 |
|
|
.clk (clk_clk), // clk.clk
|
| 430 |
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
| 431 |
|
|
.address (mm_interconnect_0_write_en_tx_s1_address), // s1.address
|
| 432 |
|
|
.write_n (~mm_interconnect_0_write_en_tx_s1_write), // .write_n
|
| 433 |
|
|
.writedata (mm_interconnect_0_write_en_tx_s1_writedata), // .writedata
|
| 434 |
|
|
.chipselect (mm_interconnect_0_write_en_tx_s1_chipselect), // .chipselect
|
| 435 |
|
|
.readdata (mm_interconnect_0_write_en_tx_s1_readdata), // .readdata
|
| 436 |
|
|
.out_port (write_en_tx_external_connection_export) // external_connection.export
|
| 437 |
|
|
);
|
| 438 |
|
|
|
| 439 |
|
|
ulight_fifo_mm_interconnect_0 mm_interconnect_0 (
|
| 440 |
|
|
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
|
| 441 |
|
|
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
|
| 442 |
|
|
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
|
| 443 |
|
|
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
|
| 444 |
|
|
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
|
| 445 |
|
|
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
|
| 446 |
|
|
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
|
| 447 |
|
|
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
|
| 448 |
|
|
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
|
| 449 |
|
|
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
|
| 450 |
|
|
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
|
| 451 |
|
|
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
|
| 452 |
|
|
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
|
| 453 |
|
|
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
|
| 454 |
|
|
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
|
| 455 |
|
|
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
|
| 456 |
|
|
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
|
| 457 |
|
|
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
|
| 458 |
|
|
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
|
| 459 |
|
|
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
|
| 460 |
|
|
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
|
| 461 |
|
|
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
|
| 462 |
|
|
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
|
| 463 |
|
|
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
|
| 464 |
|
|
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
|
| 465 |
|
|
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
|
| 466 |
|
|
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
|
| 467 |
|
|
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
|
| 468 |
|
|
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
|
| 469 |
|
|
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
|
| 470 |
|
|
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
|
| 471 |
|
|
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
|
| 472 |
|
|
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
|
| 473 |
|
|
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
|
| 474 |
|
|
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
|
| 475 |
|
|
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
|
| 476 |
|
|
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
|
| 477 |
|
|
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
|
| 478 |
|
|
.led_pio_test_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // led_pio_test_reset_reset_bridge_in_reset.reset
|
| 479 |
|
|
.auto_start_s1_address (mm_interconnect_0_auto_start_s1_address), // auto_start_s1.address
|
| 480 |
|
|
.auto_start_s1_write (mm_interconnect_0_auto_start_s1_write), // .write
|
| 481 |
|
|
.auto_start_s1_readdata (mm_interconnect_0_auto_start_s1_readdata), // .readdata
|
| 482 |
|
|
.auto_start_s1_writedata (mm_interconnect_0_auto_start_s1_writedata), // .writedata
|
| 483 |
|
|
.auto_start_s1_chipselect (mm_interconnect_0_auto_start_s1_chipselect), // .chipselect
|
| 484 |
|
|
.clock_sel_s1_address (mm_interconnect_0_clock_sel_s1_address), // clock_sel_s1.address
|
| 485 |
|
|
.clock_sel_s1_write (mm_interconnect_0_clock_sel_s1_write), // .write
|
| 486 |
|
|
.clock_sel_s1_readdata (mm_interconnect_0_clock_sel_s1_readdata), // .readdata
|
| 487 |
|
|
.clock_sel_s1_writedata (mm_interconnect_0_clock_sel_s1_writedata), // .writedata
|
| 488 |
|
|
.clock_sel_s1_chipselect (mm_interconnect_0_clock_sel_s1_chipselect), // .chipselect
|
| 489 |
|
|
.counter_rx_fifo_s1_address (mm_interconnect_0_counter_rx_fifo_s1_address), // counter_rx_fifo_s1.address
|
| 490 |
|
|
.counter_rx_fifo_s1_readdata (mm_interconnect_0_counter_rx_fifo_s1_readdata), // .readdata
|
| 491 |
|
|
.counter_tx_fifo_s1_address (mm_interconnect_0_counter_tx_fifo_s1_address), // counter_tx_fifo_s1.address
|
| 492 |
|
|
.counter_tx_fifo_s1_readdata (mm_interconnect_0_counter_tx_fifo_s1_readdata), // .readdata
|
| 493 |
|
|
.data_flag_rx_s1_address (mm_interconnect_0_data_flag_rx_s1_address), // data_flag_rx_s1.address
|
| 494 |
|
|
.data_flag_rx_s1_readdata (mm_interconnect_0_data_flag_rx_s1_readdata), // .readdata
|
| 495 |
|
|
.data_info_s1_address (mm_interconnect_0_data_info_s1_address), // data_info_s1.address
|
| 496 |
|
|
.data_info_s1_readdata (mm_interconnect_0_data_info_s1_readdata), // .readdata
|
| 497 |
|
|
.data_read_en_rx_s1_address (mm_interconnect_0_data_read_en_rx_s1_address), // data_read_en_rx_s1.address
|
| 498 |
|
|
.data_read_en_rx_s1_write (mm_interconnect_0_data_read_en_rx_s1_write), // .write
|
| 499 |
|
|
.data_read_en_rx_s1_readdata (mm_interconnect_0_data_read_en_rx_s1_readdata), // .readdata
|
| 500 |
|
|
.data_read_en_rx_s1_writedata (mm_interconnect_0_data_read_en_rx_s1_writedata), // .writedata
|
| 501 |
|
|
.data_read_en_rx_s1_chipselect (mm_interconnect_0_data_read_en_rx_s1_chipselect), // .chipselect
|
| 502 |
|
|
.fifo_empty_rx_status_s1_address (mm_interconnect_0_fifo_empty_rx_status_s1_address), // fifo_empty_rx_status_s1.address
|
| 503 |
|
|
.fifo_empty_rx_status_s1_readdata (mm_interconnect_0_fifo_empty_rx_status_s1_readdata), // .readdata
|
| 504 |
|
|
.fifo_empty_tx_status_s1_address (mm_interconnect_0_fifo_empty_tx_status_s1_address), // fifo_empty_tx_status_s1.address
|
| 505 |
|
|
.fifo_empty_tx_status_s1_readdata (mm_interconnect_0_fifo_empty_tx_status_s1_readdata), // .readdata
|
| 506 |
|
|
.fifo_full_rx_status_s1_address (mm_interconnect_0_fifo_full_rx_status_s1_address), // fifo_full_rx_status_s1.address
|
| 507 |
|
|
.fifo_full_rx_status_s1_readdata (mm_interconnect_0_fifo_full_rx_status_s1_readdata), // .readdata
|
| 508 |
|
|
.fifo_full_tx_status_s1_address (mm_interconnect_0_fifo_full_tx_status_s1_address), // fifo_full_tx_status_s1.address
|
| 509 |
|
|
.fifo_full_tx_status_s1_readdata (mm_interconnect_0_fifo_full_tx_status_s1_readdata), // .readdata
|
| 510 |
|
|
.fsm_info_s1_address (mm_interconnect_0_fsm_info_s1_address), // fsm_info_s1.address
|
| 511 |
|
|
.fsm_info_s1_readdata (mm_interconnect_0_fsm_info_s1_readdata), // .readdata
|
| 512 |
|
|
.led_pio_test_s1_address (mm_interconnect_0_led_pio_test_s1_address), // led_pio_test_s1.address
|
| 513 |
|
|
.led_pio_test_s1_write (mm_interconnect_0_led_pio_test_s1_write), // .write
|
| 514 |
|
|
.led_pio_test_s1_readdata (mm_interconnect_0_led_pio_test_s1_readdata), // .readdata
|
| 515 |
|
|
.led_pio_test_s1_writedata (mm_interconnect_0_led_pio_test_s1_writedata), // .writedata
|
| 516 |
|
|
.led_pio_test_s1_chipselect (mm_interconnect_0_led_pio_test_s1_chipselect), // .chipselect
|
| 517 |
|
|
.link_disable_s1_address (mm_interconnect_0_link_disable_s1_address), // link_disable_s1.address
|
| 518 |
|
|
.link_disable_s1_write (mm_interconnect_0_link_disable_s1_write), // .write
|
| 519 |
|
|
.link_disable_s1_readdata (mm_interconnect_0_link_disable_s1_readdata), // .readdata
|
| 520 |
|
|
.link_disable_s1_writedata (mm_interconnect_0_link_disable_s1_writedata), // .writedata
|
| 521 |
|
|
.link_disable_s1_chipselect (mm_interconnect_0_link_disable_s1_chipselect), // .chipselect
|
| 522 |
|
|
.link_start_s1_address (mm_interconnect_0_link_start_s1_address), // link_start_s1.address
|
| 523 |
|
|
.link_start_s1_write (mm_interconnect_0_link_start_s1_write), // .write
|
| 524 |
|
|
.link_start_s1_readdata (mm_interconnect_0_link_start_s1_readdata), // .readdata
|
| 525 |
|
|
.link_start_s1_writedata (mm_interconnect_0_link_start_s1_writedata), // .writedata
|
| 526 |
|
|
.link_start_s1_chipselect (mm_interconnect_0_link_start_s1_chipselect), // .chipselect
|
| 527 |
|
|
.timecode_ready_rx_s1_address (mm_interconnect_0_timecode_ready_rx_s1_address), // timecode_ready_rx_s1.address
|
| 528 |
|
|
.timecode_ready_rx_s1_readdata (mm_interconnect_0_timecode_ready_rx_s1_readdata), // .readdata
|
| 529 |
|
|
.timecode_rx_s1_address (mm_interconnect_0_timecode_rx_s1_address), // timecode_rx_s1.address
|
| 530 |
|
|
.timecode_rx_s1_readdata (mm_interconnect_0_timecode_rx_s1_readdata), // .readdata
|
| 531 |
|
|
.timecode_tx_data_s1_address (mm_interconnect_0_timecode_tx_data_s1_address), // timecode_tx_data_s1.address
|
| 532 |
|
|
.timecode_tx_data_s1_write (mm_interconnect_0_timecode_tx_data_s1_write), // .write
|
| 533 |
|
|
.timecode_tx_data_s1_readdata (mm_interconnect_0_timecode_tx_data_s1_readdata), // .readdata
|
| 534 |
|
|
.timecode_tx_data_s1_writedata (mm_interconnect_0_timecode_tx_data_s1_writedata), // .writedata
|
| 535 |
|
|
.timecode_tx_data_s1_chipselect (mm_interconnect_0_timecode_tx_data_s1_chipselect), // .chipselect
|
| 536 |
|
|
.timecode_tx_enable_s1_address (mm_interconnect_0_timecode_tx_enable_s1_address), // timecode_tx_enable_s1.address
|
| 537 |
|
|
.timecode_tx_enable_s1_write (mm_interconnect_0_timecode_tx_enable_s1_write), // .write
|
| 538 |
|
|
.timecode_tx_enable_s1_readdata (mm_interconnect_0_timecode_tx_enable_s1_readdata), // .readdata
|
| 539 |
|
|
.timecode_tx_enable_s1_writedata (mm_interconnect_0_timecode_tx_enable_s1_writedata), // .writedata
|
| 540 |
|
|
.timecode_tx_enable_s1_chipselect (mm_interconnect_0_timecode_tx_enable_s1_chipselect), // .chipselect
|
| 541 |
|
|
.timecode_tx_ready_s1_address (mm_interconnect_0_timecode_tx_ready_s1_address), // timecode_tx_ready_s1.address
|
| 542 |
|
|
.timecode_tx_ready_s1_readdata (mm_interconnect_0_timecode_tx_ready_s1_readdata), // .readdata
|
| 543 |
|
|
.write_data_fifo_tx_s1_address (mm_interconnect_0_write_data_fifo_tx_s1_address), // write_data_fifo_tx_s1.address
|
| 544 |
|
|
.write_data_fifo_tx_s1_write (mm_interconnect_0_write_data_fifo_tx_s1_write), // .write
|
| 545 |
|
|
.write_data_fifo_tx_s1_readdata (mm_interconnect_0_write_data_fifo_tx_s1_readdata), // .readdata
|
| 546 |
|
|
.write_data_fifo_tx_s1_writedata (mm_interconnect_0_write_data_fifo_tx_s1_writedata), // .writedata
|
| 547 |
|
|
.write_data_fifo_tx_s1_chipselect (mm_interconnect_0_write_data_fifo_tx_s1_chipselect), // .chipselect
|
| 548 |
|
|
.write_en_tx_s1_address (mm_interconnect_0_write_en_tx_s1_address), // write_en_tx_s1.address
|
| 549 |
|
|
.write_en_tx_s1_write (mm_interconnect_0_write_en_tx_s1_write), // .write
|
| 550 |
|
|
.write_en_tx_s1_readdata (mm_interconnect_0_write_en_tx_s1_readdata), // .readdata
|
| 551 |
|
|
.write_en_tx_s1_writedata (mm_interconnect_0_write_en_tx_s1_writedata), // .writedata
|
| 552 |
|
|
.write_en_tx_s1_chipselect (mm_interconnect_0_write_en_tx_s1_chipselect) // .chipselect
|
| 553 |
|
|
);
|
| 554 |
|
|
|
| 555 |
|
|
altera_reset_controller #(
|
| 556 |
|
|
.NUM_RESET_INPUTS (1),
|
| 557 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
| 558 |
|
|
.SYNC_DEPTH (2),
|
| 559 |
|
|
.RESET_REQUEST_PRESENT (0),
|
| 560 |
|
|
.RESET_REQ_WAIT_TIME (1),
|
| 561 |
|
|
.MIN_RST_ASSERTION_TIME (3),
|
| 562 |
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
| 563 |
|
|
.USE_RESET_REQUEST_IN0 (0),
|
| 564 |
|
|
.USE_RESET_REQUEST_IN1 (0),
|
| 565 |
|
|
.USE_RESET_REQUEST_IN2 (0),
|
| 566 |
|
|
.USE_RESET_REQUEST_IN3 (0),
|
| 567 |
|
|
.USE_RESET_REQUEST_IN4 (0),
|
| 568 |
|
|
.USE_RESET_REQUEST_IN5 (0),
|
| 569 |
|
|
.USE_RESET_REQUEST_IN6 (0),
|
| 570 |
|
|
.USE_RESET_REQUEST_IN7 (0),
|
| 571 |
|
|
.USE_RESET_REQUEST_IN8 (0),
|
| 572 |
|
|
.USE_RESET_REQUEST_IN9 (0),
|
| 573 |
|
|
.USE_RESET_REQUEST_IN10 (0),
|
| 574 |
|
|
.USE_RESET_REQUEST_IN11 (0),
|
| 575 |
|
|
.USE_RESET_REQUEST_IN12 (0),
|
| 576 |
|
|
.USE_RESET_REQUEST_IN13 (0),
|
| 577 |
|
|
.USE_RESET_REQUEST_IN14 (0),
|
| 578 |
|
|
.USE_RESET_REQUEST_IN15 (0),
|
| 579 |
|
|
.ADAPT_RESET_REQUEST (0)
|
| 580 |
|
|
) rst_controller (
|
| 581 |
|
|
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
| 582 |
|
|
.clk (clk_clk), // clk.clk
|
| 583 |
|
|
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
| 584 |
|
|
.reset_req (), // (terminated)
|
| 585 |
|
|
.reset_req_in0 (1'b0), // (terminated)
|
| 586 |
|
|
.reset_in1 (1'b0), // (terminated)
|
| 587 |
|
|
.reset_req_in1 (1'b0), // (terminated)
|
| 588 |
|
|
.reset_in2 (1'b0), // (terminated)
|
| 589 |
|
|
.reset_req_in2 (1'b0), // (terminated)
|
| 590 |
|
|
.reset_in3 (1'b0), // (terminated)
|
| 591 |
|
|
.reset_req_in3 (1'b0), // (terminated)
|
| 592 |
|
|
.reset_in4 (1'b0), // (terminated)
|
| 593 |
|
|
.reset_req_in4 (1'b0), // (terminated)
|
| 594 |
|
|
.reset_in5 (1'b0), // (terminated)
|
| 595 |
|
|
.reset_req_in5 (1'b0), // (terminated)
|
| 596 |
|
|
.reset_in6 (1'b0), // (terminated)
|
| 597 |
|
|
.reset_req_in6 (1'b0), // (terminated)
|
| 598 |
|
|
.reset_in7 (1'b0), // (terminated)
|
| 599 |
|
|
.reset_req_in7 (1'b0), // (terminated)
|
| 600 |
|
|
.reset_in8 (1'b0), // (terminated)
|
| 601 |
|
|
.reset_req_in8 (1'b0), // (terminated)
|
| 602 |
|
|
.reset_in9 (1'b0), // (terminated)
|
| 603 |
|
|
.reset_req_in9 (1'b0), // (terminated)
|
| 604 |
|
|
.reset_in10 (1'b0), // (terminated)
|
| 605 |
|
|
.reset_req_in10 (1'b0), // (terminated)
|
| 606 |
|
|
.reset_in11 (1'b0), // (terminated)
|
| 607 |
|
|
.reset_req_in11 (1'b0), // (terminated)
|
| 608 |
|
|
.reset_in12 (1'b0), // (terminated)
|
| 609 |
|
|
.reset_req_in12 (1'b0), // (terminated)
|
| 610 |
|
|
.reset_in13 (1'b0), // (terminated)
|
| 611 |
|
|
.reset_req_in13 (1'b0), // (terminated)
|
| 612 |
|
|
.reset_in14 (1'b0), // (terminated)
|
| 613 |
|
|
.reset_req_in14 (1'b0), // (terminated)
|
| 614 |
|
|
.reset_in15 (1'b0), // (terminated)
|
| 615 |
|
|
.reset_req_in15 (1'b0) // (terminated)
|
| 616 |
|
|
);
|
| 617 |
|
|
|
| 618 |
|
|
altera_reset_controller #(
|
| 619 |
|
|
.NUM_RESET_INPUTS (1),
|
| 620 |
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
| 621 |
|
|
.SYNC_DEPTH (2),
|
| 622 |
|
|
.RESET_REQUEST_PRESENT (0),
|
| 623 |
|
|
.RESET_REQ_WAIT_TIME (1),
|
| 624 |
|
|
.MIN_RST_ASSERTION_TIME (3),
|
| 625 |
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
| 626 |
|
|
.USE_RESET_REQUEST_IN0 (0),
|
| 627 |
|
|
.USE_RESET_REQUEST_IN1 (0),
|
| 628 |
|
|
.USE_RESET_REQUEST_IN2 (0),
|
| 629 |
|
|
.USE_RESET_REQUEST_IN3 (0),
|
| 630 |
|
|
.USE_RESET_REQUEST_IN4 (0),
|
| 631 |
|
|
.USE_RESET_REQUEST_IN5 (0),
|
| 632 |
|
|
.USE_RESET_REQUEST_IN6 (0),
|
| 633 |
|
|
.USE_RESET_REQUEST_IN7 (0),
|
| 634 |
|
|
.USE_RESET_REQUEST_IN8 (0),
|
| 635 |
|
|
.USE_RESET_REQUEST_IN9 (0),
|
| 636 |
|
|
.USE_RESET_REQUEST_IN10 (0),
|
| 637 |
|
|
.USE_RESET_REQUEST_IN11 (0),
|
| 638 |
|
|
.USE_RESET_REQUEST_IN12 (0),
|
| 639 |
|
|
.USE_RESET_REQUEST_IN13 (0),
|
| 640 |
|
|
.USE_RESET_REQUEST_IN14 (0),
|
| 641 |
|
|
.USE_RESET_REQUEST_IN15 (0),
|
| 642 |
|
|
.ADAPT_RESET_REQUEST (0)
|
| 643 |
|
|
) rst_controller_001 (
|
| 644 |
|
|
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
|
| 645 |
|
|
.clk (clk_clk), // clk.clk
|
| 646 |
|
|
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
|
| 647 |
|
|
.reset_req (), // (terminated)
|
| 648 |
|
|
.reset_req_in0 (1'b0), // (terminated)
|
| 649 |
|
|
.reset_in1 (1'b0), // (terminated)
|
| 650 |
|
|
.reset_req_in1 (1'b0), // (terminated)
|
| 651 |
|
|
.reset_in2 (1'b0), // (terminated)
|
| 652 |
|
|
.reset_req_in2 (1'b0), // (terminated)
|
| 653 |
|
|
.reset_in3 (1'b0), // (terminated)
|
| 654 |
|
|
.reset_req_in3 (1'b0), // (terminated)
|
| 655 |
|
|
.reset_in4 (1'b0), // (terminated)
|
| 656 |
|
|
.reset_req_in4 (1'b0), // (terminated)
|
| 657 |
|
|
.reset_in5 (1'b0), // (terminated)
|
| 658 |
|
|
.reset_req_in5 (1'b0), // (terminated)
|
| 659 |
|
|
.reset_in6 (1'b0), // (terminated)
|
| 660 |
|
|
.reset_req_in6 (1'b0), // (terminated)
|
| 661 |
|
|
.reset_in7 (1'b0), // (terminated)
|
| 662 |
|
|
.reset_req_in7 (1'b0), // (terminated)
|
| 663 |
|
|
.reset_in8 (1'b0), // (terminated)
|
| 664 |
|
|
.reset_req_in8 (1'b0), // (terminated)
|
| 665 |
|
|
.reset_in9 (1'b0), // (terminated)
|
| 666 |
|
|
.reset_req_in9 (1'b0), // (terminated)
|
| 667 |
|
|
.reset_in10 (1'b0), // (terminated)
|
| 668 |
|
|
.reset_req_in10 (1'b0), // (terminated)
|
| 669 |
|
|
.reset_in11 (1'b0), // (terminated)
|
| 670 |
|
|
.reset_req_in11 (1'b0), // (terminated)
|
| 671 |
|
|
.reset_in12 (1'b0), // (terminated)
|
| 672 |
|
|
.reset_req_in12 (1'b0), // (terminated)
|
| 673 |
|
|
.reset_in13 (1'b0), // (terminated)
|
| 674 |
|
|
.reset_req_in13 (1'b0), // (terminated)
|
| 675 |
|
|
.reset_in14 (1'b0), // (terminated)
|
| 676 |
|
|
.reset_req_in14 (1'b0), // (terminated)
|
| 677 |
|
|
.reset_in15 (1'b0), // (terminated)
|
| 678 |
|
|
.reset_req_in15 (1'b0) // (terminated)
|
| 679 |
|
|
);
|
| 680 |
|
|
|
| 681 |
|
|
endmodule
|
