1 |
32 |
redbear |
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2 |
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module ulight_fifo (
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3 |
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auto_start_external_connection_export,
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4 |
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clk_clk,
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5 |
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clock_sel_external_connection_export,
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6 |
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counter_rx_fifo_external_connection_export,
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7 |
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counter_tx_fifo_external_connection_export,
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8 |
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data_flag_rx_external_connection_export,
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data_info_external_connection_export,
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10 |
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data_read_en_rx_external_connection_export,
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11 |
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fifo_empty_rx_status_external_connection_export,
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12 |
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fifo_empty_tx_status_external_connection_export,
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fifo_full_rx_status_external_connection_export,
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fifo_full_tx_status_external_connection_export,
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fsm_info_external_connection_export,
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led_pio_test_external_connection_export,
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link_disable_external_connection_export,
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link_start_external_connection_export,
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memory_mem_a,
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memory_mem_ba,
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memory_mem_ck,
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memory_mem_ck_n,
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memory_mem_cke,
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memory_mem_cs_n,
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memory_mem_ras_n,
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memory_mem_cas_n,
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memory_mem_we_n,
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memory_mem_reset_n,
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memory_mem_dq,
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memory_mem_dqs,
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31 |
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memory_mem_dqs_n,
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32 |
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memory_mem_odt,
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33 |
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memory_mem_dm,
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memory_oct_rzqin,
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35 |
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pll_0_locked_export,
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pll_0_outclk0_clk,
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reset_reset_n,
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timecode_ready_rx_external_connection_export,
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timecode_rx_external_connection_export,
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timecode_tx_data_external_connection_export,
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timecode_tx_enable_external_connection_export,
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timecode_tx_ready_external_connection_export,
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write_data_fifo_tx_external_connection_export,
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write_en_tx_external_connection_export);
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46 |
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output auto_start_external_connection_export;
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input clk_clk;
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output [2:0] clock_sel_external_connection_export;
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input [5:0] counter_rx_fifo_external_connection_export;
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input [5:0] counter_tx_fifo_external_connection_export;
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input [8:0] data_flag_rx_external_connection_export;
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input [13:0] data_info_external_connection_export;
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output data_read_en_rx_external_connection_export;
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54 |
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input fifo_empty_rx_status_external_connection_export;
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input fifo_empty_tx_status_external_connection_export;
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input fifo_full_rx_status_external_connection_export;
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input fifo_full_tx_status_external_connection_export;
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input [5:0] fsm_info_external_connection_export;
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output [4:0] led_pio_test_external_connection_export;
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60 |
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output link_disable_external_connection_export;
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61 |
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output link_start_external_connection_export;
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output [12:0] memory_mem_a;
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63 |
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output [2:0] memory_mem_ba;
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output memory_mem_ck;
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output memory_mem_ck_n;
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output memory_mem_cke;
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output memory_mem_cs_n;
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output memory_mem_ras_n;
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output memory_mem_cas_n;
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output memory_mem_we_n;
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output memory_mem_reset_n;
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inout [7:0] memory_mem_dq;
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inout memory_mem_dqs;
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inout memory_mem_dqs_n;
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output memory_mem_odt;
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output memory_mem_dm;
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input memory_oct_rzqin;
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output pll_0_locked_export;
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output pll_0_outclk0_clk;
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80 |
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input reset_reset_n;
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81 |
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input timecode_ready_rx_external_connection_export;
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input [7:0] timecode_rx_external_connection_export;
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output [7:0] timecode_tx_data_external_connection_export;
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84 |
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output timecode_tx_enable_external_connection_export;
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85 |
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input timecode_tx_ready_external_connection_export;
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output [8:0] write_data_fifo_tx_external_connection_export;
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output write_en_tx_external_connection_export;
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88 |
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endmodule
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