| 1 |
32 |
redbear |
Info: Starting: Create block symbol file (.bsf)
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| 2 |
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Info: qsys-generate /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo.qsys --block-symbol-file --output-directory=/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo --family="Cyclone V" --part=5CSEMA4U23C6
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| 3 |
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Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
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| 4 |
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Progress: Reading input file
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| 5 |
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Progress: Adding auto_start [altera_avalon_pio 17.0]
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| 6 |
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Progress: Parameterizing module auto_start
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| 7 |
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Progress: Adding clk_0 [clock_source 17.0]
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| 8 |
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Progress: Parameterizing module clk_0
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| 9 |
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Progress: Adding clock_sel [altera_avalon_pio 17.0]
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| 10 |
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Progress: Parameterizing module clock_sel
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| 11 |
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Progress: Adding counter_rx_fifo [altera_avalon_pio 17.0]
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| 12 |
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Progress: Parameterizing module counter_rx_fifo
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| 13 |
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Progress: Adding counter_tx_fifo [altera_avalon_pio 17.0]
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| 14 |
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Progress: Parameterizing module counter_tx_fifo
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| 15 |
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Progress: Adding data_flag_rx [altera_avalon_pio 17.0]
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| 16 |
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Progress: Parameterizing module data_flag_rx
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| 17 |
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Progress: Adding data_info [altera_avalon_pio 17.0]
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| 18 |
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Progress: Parameterizing module data_info
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| 19 |
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Progress: Adding data_read_en_rx [altera_avalon_pio 17.0]
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| 20 |
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Progress: Parameterizing module data_read_en_rx
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| 21 |
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Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.0]
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| 22 |
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Progress: Parameterizing module fifo_empty_rx_status
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| 23 |
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Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.0]
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| 24 |
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Progress: Parameterizing module fifo_empty_tx_status
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| 25 |
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Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.0]
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| 26 |
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Progress: Parameterizing module fifo_full_rx_status
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| 27 |
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Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.0]
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| 28 |
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Progress: Parameterizing module fifo_full_tx_status
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| 29 |
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Progress: Adding fsm_info [altera_avalon_pio 17.0]
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| 30 |
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Progress: Parameterizing module fsm_info
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| 31 |
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Progress: Adding hps_0 [altera_hps 17.0]
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| 32 |
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Progress: Parameterizing module hps_0
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| 33 |
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Progress: Adding led_pio_test [altera_avalon_pio 17.0]
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| 34 |
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Progress: Parameterizing module led_pio_test
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| 35 |
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Progress: Adding link_disable [altera_avalon_pio 17.0]
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| 36 |
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Progress: Parameterizing module link_disable
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| 37 |
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Progress: Adding link_start [altera_avalon_pio 17.0]
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| 38 |
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Progress: Parameterizing module link_start
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| 39 |
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Progress: Adding pll_0 [altera_pll 17.0]
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| 40 |
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Progress: Parameterizing module pll_0
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| 41 |
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Progress: Adding timecode_ready_rx [altera_avalon_pio 17.0]
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| 42 |
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Progress: Parameterizing module timecode_ready_rx
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| 43 |
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Progress: Adding timecode_rx [altera_avalon_pio 17.0]
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| 44 |
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Progress: Parameterizing module timecode_rx
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| 45 |
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Progress: Adding timecode_tx_data [altera_avalon_pio 17.0]
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| 46 |
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Progress: Parameterizing module timecode_tx_data
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| 47 |
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Progress: Adding timecode_tx_enable [altera_avalon_pio 17.0]
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| 48 |
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Progress: Parameterizing module timecode_tx_enable
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| 49 |
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Progress: Adding timecode_tx_ready [altera_avalon_pio 17.0]
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| 50 |
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Progress: Parameterizing module timecode_tx_ready
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| 51 |
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Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.0]
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| 52 |
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Progress: Parameterizing module write_data_fifo_tx
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| 53 |
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Progress: Adding write_en_tx [altera_avalon_pio 17.0]
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| 54 |
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Progress: Parameterizing module write_en_tx
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| 55 |
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Progress: Building connections
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| 56 |
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Progress: Parameterizing connections
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| 57 |
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Progress: Validating
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| 58 |
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Progress: Done reading input file
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| 59 |
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Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 60 |
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Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 61 |
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Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 62 |
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Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 63 |
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Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 64 |
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 65 |
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Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 66 |
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Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 67 |
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 68 |
40 |
redbear |
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
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| 69 |
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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| 70 |
32 |
redbear |
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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| 71 |
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Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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| 72 |
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Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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| 73 |
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Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
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| 74 |
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Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
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| 75 |
40 |
redbear |
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
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| 76 |
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Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
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| 77 |
32 |
redbear |
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
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| 78 |
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Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
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| 79 |
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Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 80 |
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Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 81 |
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Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 82 |
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Info: qsys-generate succeeded.
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| 83 |
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Info: Finished: Create block symbol file (.bsf)
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| 84 |
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Info:
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| 85 |
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Info: Starting: Create HDL design files for synthesis
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| 86 |
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Info: qsys-generate /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo.qsys --synthesis=VERILOG --output-directory=/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis --family="Cyclone V" --part=5CSEMA4U23C6
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| 87 |
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Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
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| 88 |
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Progress: Reading input file
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| 89 |
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Progress: Adding auto_start [altera_avalon_pio 17.0]
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| 90 |
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Progress: Parameterizing module auto_start
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| 91 |
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Progress: Adding clk_0 [clock_source 17.0]
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| 92 |
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Progress: Parameterizing module clk_0
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| 93 |
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Progress: Adding clock_sel [altera_avalon_pio 17.0]
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| 94 |
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Progress: Parameterizing module clock_sel
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| 95 |
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Progress: Adding counter_rx_fifo [altera_avalon_pio 17.0]
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| 96 |
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Progress: Parameterizing module counter_rx_fifo
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| 97 |
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Progress: Adding counter_tx_fifo [altera_avalon_pio 17.0]
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| 98 |
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Progress: Parameterizing module counter_tx_fifo
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| 99 |
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Progress: Adding data_flag_rx [altera_avalon_pio 17.0]
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| 100 |
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Progress: Parameterizing module data_flag_rx
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| 101 |
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Progress: Adding data_info [altera_avalon_pio 17.0]
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| 102 |
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Progress: Parameterizing module data_info
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| 103 |
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Progress: Adding data_read_en_rx [altera_avalon_pio 17.0]
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| 104 |
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Progress: Parameterizing module data_read_en_rx
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| 105 |
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Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.0]
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| 106 |
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Progress: Parameterizing module fifo_empty_rx_status
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| 107 |
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Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.0]
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| 108 |
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Progress: Parameterizing module fifo_empty_tx_status
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| 109 |
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Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.0]
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| 110 |
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Progress: Parameterizing module fifo_full_rx_status
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| 111 |
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Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.0]
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| 112 |
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Progress: Parameterizing module fifo_full_tx_status
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| 113 |
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Progress: Adding fsm_info [altera_avalon_pio 17.0]
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| 114 |
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Progress: Parameterizing module fsm_info
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| 115 |
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Progress: Adding hps_0 [altera_hps 17.0]
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| 116 |
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Progress: Parameterizing module hps_0
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| 117 |
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Progress: Adding led_pio_test [altera_avalon_pio 17.0]
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| 118 |
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Progress: Parameterizing module led_pio_test
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| 119 |
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Progress: Adding link_disable [altera_avalon_pio 17.0]
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| 120 |
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Progress: Parameterizing module link_disable
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| 121 |
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Progress: Adding link_start [altera_avalon_pio 17.0]
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| 122 |
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Progress: Parameterizing module link_start
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| 123 |
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Progress: Adding pll_0 [altera_pll 17.0]
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| 124 |
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Progress: Parameterizing module pll_0
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| 125 |
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Progress: Adding timecode_ready_rx [altera_avalon_pio 17.0]
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| 126 |
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Progress: Parameterizing module timecode_ready_rx
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| 127 |
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Progress: Adding timecode_rx [altera_avalon_pio 17.0]
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| 128 |
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Progress: Parameterizing module timecode_rx
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| 129 |
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Progress: Adding timecode_tx_data [altera_avalon_pio 17.0]
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| 130 |
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Progress: Parameterizing module timecode_tx_data
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| 131 |
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Progress: Adding timecode_tx_enable [altera_avalon_pio 17.0]
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| 132 |
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Progress: Parameterizing module timecode_tx_enable
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| 133 |
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Progress: Adding timecode_tx_ready [altera_avalon_pio 17.0]
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| 134 |
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Progress: Parameterizing module timecode_tx_ready
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| 135 |
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Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.0]
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| 136 |
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Progress: Parameterizing module write_data_fifo_tx
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| 137 |
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Progress: Adding write_en_tx [altera_avalon_pio 17.0]
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| 138 |
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Progress: Parameterizing module write_en_tx
|
| 139 |
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Progress: Building connections
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| 140 |
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Progress: Parameterizing connections
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| 141 |
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Progress: Validating
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| 142 |
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Progress: Done reading input file
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| 143 |
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Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 144 |
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Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 145 |
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Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 146 |
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Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 147 |
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Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 148 |
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 149 |
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Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 150 |
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Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 151 |
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 152 |
40 |
redbear |
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
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| 153 |
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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| 154 |
32 |
redbear |
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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| 155 |
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Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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| 156 |
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Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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| 157 |
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Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
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| 158 |
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Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
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| 159 |
40 |
redbear |
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
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| 160 |
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Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
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| 161 |
32 |
redbear |
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
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| 162 |
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Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
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| 163 |
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Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 164 |
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Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 165 |
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Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 166 |
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Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for QUARTUS_SYNTH
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| 167 |
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Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
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| 168 |
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Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
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| 169 |
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Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
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| 170 |
40 |
redbear |
Info: auto_start: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7485_7332943204255753946.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]
|
| 171 |
32 |
redbear |
Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
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| 172 |
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Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
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| 173 |
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Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
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| 174 |
40 |
redbear |
Info: clock_sel: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7485_7332943204255753946.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]
|
| 175 |
32 |
redbear |
Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
|
| 176 |
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Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
|
| 177 |
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Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
|
| 178 |
40 |
redbear |
Info: counter_rx_fifo: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7485_7332943204255753946.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]
|
| 179 |
32 |
redbear |
Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
|
| 180 |
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Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
|
| 181 |
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Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
|
| 182 |
40 |
redbear |
Info: data_flag_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7485_7332943204255753946.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]
|
| 183 |
32 |
redbear |
Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
|
| 184 |
|
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Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
|
| 185 |
|
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Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
|
| 186 |
40 |
redbear |
Info: data_info: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7485_7332943204255753946.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]
|
| 187 |
32 |
redbear |
Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
|
| 188 |
|
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Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
|
| 189 |
|
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Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
|
| 190 |
40 |
redbear |
Info: fifo_empty_rx_status: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7485_7332943204255753946.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]
|
| 191 |
32 |
redbear |
Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
|
| 192 |
|
|
Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
|
| 193 |
|
|
Info: hps_0: "Running for module: hps_0"
|
| 194 |
40 |
redbear |
Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36
|
| 195 |
|
|
Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
|
| 196 |
32 |
redbear |
Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
| 197 |
|
|
Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
| 198 |
|
|
Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
| 199 |
|
|
Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
| 200 |
|
|
Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
|
| 201 |
|
|
Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
|
| 202 |
40 |
redbear |
Info: led_pio_test: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7485_7332943204255753946.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]
|
| 203 |
32 |
redbear |
Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
|
| 204 |
|
|
Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
|
| 205 |
|
|
Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
|
| 206 |
|
|
Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
|
| 207 |
40 |
redbear |
Info: timecode_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7485_7332943204255753946.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]
|
| 208 |
32 |
redbear |
Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
|
| 209 |
|
|
Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
|
| 210 |
|
|
Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
|
| 211 |
40 |
redbear |
Info: timecode_tx_data: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7485_7332943204255753946.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]
|
| 212 |
32 |
redbear |
Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
|
| 213 |
|
|
Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
|
| 214 |
|
|
Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
|
| 215 |
40 |
redbear |
Info: write_data_fifo_tx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7485_7332943204255753946.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]
|
| 216 |
32 |
redbear |
Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
|
| 217 |
|
|
Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
|
| 218 |
|
|
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
|
| 219 |
|
|
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
|
| 220 |
|
|
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
|
| 221 |
|
|
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
|
| 222 |
|
|
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
|
| 223 |
|
|
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
|
| 224 |
|
|
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
|
| 225 |
|
|
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
|
| 226 |
|
|
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
|
| 227 |
|
|
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
|
| 228 |
|
|
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
|
| 229 |
|
|
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
|
| 230 |
|
|
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
|
| 231 |
|
|
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
|
| 232 |
|
|
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
|
| 233 |
|
|
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
|
| 234 |
|
|
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
|
| 235 |
|
|
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
|
| 236 |
|
|
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
|
| 237 |
|
|
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
|
| 238 |
|
|
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
|
| 239 |
|
|
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
|
| 240 |
|
|
Info: mm_interconnect_0: "ulight_fifo" instantiated altera_mm_interconnect "mm_interconnect_0"
|
| 241 |
|
|
Info: rst_controller: "ulight_fifo" instantiated altera_reset_controller "rst_controller"
|
| 242 |
|
|
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
|
| 243 |
|
|
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
|
| 244 |
|
|
Info: led_pio_test_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "led_pio_test_s1_translator"
|
| 245 |
|
|
Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
|
| 246 |
|
|
Info: led_pio_test_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "led_pio_test_s1_agent"
|
| 247 |
|
|
Info: led_pio_test_s1_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "led_pio_test_s1_agent_rsp_fifo"
|
| 248 |
|
|
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
|
| 249 |
|
|
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
|
| 250 |
|
|
Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
|
| 251 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v
|
| 252 |
|
|
Info: led_pio_test_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "led_pio_test_s1_burst_adapter"
|
| 253 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv
|
| 254 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v
|
| 255 |
|
|
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
|
| 256 |
|
|
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
|
| 257 |
|
|
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
|
| 258 |
|
|
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
|
| 259 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv
|
| 260 |
|
|
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
|
| 261 |
|
|
Info: border: "hps_io" instantiated altera_interface_generator "border"
|
| 262 |
|
|
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
|
| 263 |
|
|
Info: ulight_fifo: Done "ulight_fifo" with 32 modules, 89 files
|
| 264 |
|
|
Info: qsys-generate succeeded.
|
| 265 |
|
|
Info: Finished: Create HDL design files for synthesis
|
