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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [clock_reduce.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module clock_reduce(
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                        input clk,
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                        input reset_n,
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                        input [2:0] clock_sel,
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                        output  clk_reduced,
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                        output  clk_100_reduced
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                   );
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reg [10:0] counter;
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reg [10:0] counter_100;
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assign clk_reduced     = clk_reduced_p | clk_reduced_n;
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assign clk_100_reduced = clk_100_reduced_p | clk_100_reduced_n;
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reg clk_reduced_i;
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reg clk_100_reduced_i;
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reg clk_reduced_p;
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reg clk_100_reduced_p;
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reg clk_reduced_n;
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reg clk_100_reduced_n;
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always@(*)
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begin
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        clk_reduced_p = 1'b0;
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        if(clk_reduced_i)
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        begin
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                clk_reduced_p = 1'b1;
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        end
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end
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always@(*)
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begin
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        clk_reduced_n = 1'b1;
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        if(!clk_reduced_i)
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        begin
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                clk_reduced_n = 1'b0;
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        end
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end
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always@(*)
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begin
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        clk_100_reduced_p = 1'b0;
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        if(clk_100_reduced_i)
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        begin
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                clk_100_reduced_p = 1'b1;
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        end
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end
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always@(*)
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begin
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        clk_100_reduced_n = 1'b1;
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        if(!clk_100_reduced_i)
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        begin
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                clk_100_reduced_n = 1'b0;
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        end
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end
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always@(posedge clk)
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begin
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        if(!reset_n)
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        begin
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                counter <= 11'd0;
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                counter_100 <= 11'd0;
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                clk_reduced_i <= 1'b0;
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                clk_100_reduced_i <= 1'b0;
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        end
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        else
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        begin
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                case(clock_sel)
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                3'd0://2mhz - 500 ns
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                begin
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                        if(counter >=11'd0 && counter <=11'd99 )
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter >=11'd100 && counter <=11'd199 )
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
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                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd1://5mhz
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                begin
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                        if(counter >=11'd0 && counter <=11'd39 )
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter >=11'd40 && counter <=11'd79 )
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
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                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd2://10mhz
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                begin
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                        if(counter >=11'd0 && counter <=11'd19 )
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter >=11'd20 && counter <=11'd39 )
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
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                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd3://50mhz
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                begin
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                        if(counter >=11'd0 && counter <=11'd3 )
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter >=11'd4 && counter <=11'd7)
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
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                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd4://100mhz
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                begin
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                        if(counter >=11'd0 && counter <=11'd1 )
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter >=11'd2 && counter <=11'd4)
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                        begin
210
                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
212
                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd5://150mhz
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                begin
221
                        if(counter >=11'd0 && counter <=11'd1 )
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                        begin
223
                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
225
                        end
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                        else if(counter >=11'd2 && counter <=11'd3)
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
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                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
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                end
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                3'd6://200mhz
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                begin
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                        if(counter >=11'd0 && counter <=11'd1 )
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                        begin
241
                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter == 11'd2)
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
248
                        end
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                        else
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                        begin
251
                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
253
                        end
254
                end
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                3'd7://300mhz
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                begin
257
                        if(counter ==11'd0 )
258
                        begin
259
                                clk_reduced_i <= 1'b1;
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                                counter <= counter + 11'd1;
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                        end
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                        else if(counter ==11'd1)
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                        begin
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                                clk_reduced_i <= 1'b0;
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                                counter <= counter + 11'd1;
266
                        end
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                        else
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                        begin
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                                clk_reduced_i <= 1'b1;
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                                counter <= 11'd0;
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                        end
272
                end
273
                endcase
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275
                if(counter_100 >=11'd0 && counter_100 <=11'd1 )
276
                begin
277
                        clk_100_reduced_i <= 1'b1;
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                        counter_100 <= counter_100 + 11'd1;
279
                end
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                else if(counter_100 >=11'd2 && counter_100 <=11'd4)
281
                begin
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                        clk_100_reduced_i <= 1'b0;
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                        counter_100 <= counter_100 + 11'd1;
284
                end
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                else
286
                begin
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                        clk_100_reduced_i <= 1'b1;
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                        counter_100 <= 11'd0;
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                end
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        end
292
 
293
end
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endmodule

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