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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Blame information for rev 40

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1 33 redbear
//+FHDR------------------------------------------------------------------------
2
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3
//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module fifo_rx
34
#(
35
        parameter integer DWIDTH = 9,
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        parameter integer AWIDTH = 6
37
)
38
 
39
(
40
        input clock, reset, wr_en, rd_en,
41
        input [DWIDTH-1:0] data_in,
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        output reg f_full,f_empty,
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        output reg open_slot_fct,
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        output reg overflow_credit_error,
45 40 redbear
        output [DWIDTH-1:0] data_out,
46 33 redbear
        output reg [AWIDTH-1:0] counter
47
);
48
 
49
        reg [AWIDTH-1:0] wr_ptr;
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        reg [AWIDTH-1:0] rd_ptr;
51
 
52
        reg [AWIDTH-1:0] credit_counter;
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54 37 redbear
        reg  [1:0] state_data_write;
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        reg  [1:0] next_state_data_write;
56
 
57
        reg  [1:0] state_data_read;
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        reg  [1:0] next_state_data_read;
59
 
60 40 redbear
        reg  [1:0] state_open_slot;
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        reg  [1:0] next_state_open_slot;
62 37 redbear
 
63 40 redbear
        reg [10:0] counter_wait;
64
 
65 37 redbear
/****************************************/
66
 
67
always@(*)
68
begin
69 40 redbear
        next_state_open_slot = state_open_slot;
70
 
71
        case(state_open_slot)
72
        2'd0:
73
        begin
74
                if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
75
                begin
76
                        next_state_open_slot = 2'd1;
77
                end
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                else
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                begin
80
                        next_state_open_slot = 2'd0;
81
                end
82
        end
83
        2'd1:
84
        begin
85
                if(counter_wait != 11'd300)
86
                        next_state_open_slot = 2'd1;
87
                else
88
                        next_state_open_slot = 2'd2;
89
        end
90
        2'd2:
91
        begin
92
                if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
93
                begin
94
                        next_state_open_slot = 2'd2;
95
                end
96
                else
97
                begin
98
                        next_state_open_slot = 2'd0;
99
                end
100
 
101
        end
102
        default:
103
        begin
104
                next_state_open_slot = 2'd0;
105
        end
106
        endcase
107
end
108
 
109
/****************************************/
110
 
111
always@(*)
112
begin
113 37 redbear
        next_state_data_write = state_data_write;
114
 
115
        case(state_data_write)
116
        2'd0:
117
        begin
118
                if(wr_en && !f_full)
119
                begin
120
                        next_state_data_write = 2'd1;
121
                end
122
                else
123
                begin
124
                        next_state_data_write = 2'd0;
125
                end
126
        end
127
        2'd1:
128
        begin
129
                if(wr_en)
130
                begin
131
                        next_state_data_write = 2'd1;
132
                end
133
                else
134
                begin
135
                        next_state_data_write = 2'd2;
136
                end
137
        end
138
        2'd2:
139
        begin
140
                next_state_data_write = 2'd0;
141
        end
142
        default:
143
        begin
144
                next_state_data_write = 2'd0;
145
        end
146
        endcase
147
end
148
 
149
/****************************************/
150
 
151
always@(*)
152
begin
153
        next_state_data_read = state_data_read;
154
 
155
        case(state_data_read)
156
        2'd0:
157
        begin
158
                if(rd_en && !f_empty)
159
                begin
160
                        next_state_data_read = 2'd1;
161
                end
162
                else
163
                begin
164
                        next_state_data_read = 2'd0;
165
                end
166
        end
167
        2'd1:
168
        begin
169
                if(rd_en)
170
                begin
171
                        next_state_data_read = 2'd1;
172
                end
173
                else
174
                begin
175
                        next_state_data_read = 2'd2;
176
                end
177
        end
178
        2'd2:
179
        begin
180
                next_state_data_read = 2'd0;
181
        end
182
        default:
183
        begin
184
                next_state_data_read = 2'd0;
185
        end
186
        endcase
187
end
188
 
189 40 redbear
always@(posedge clock or negedge reset)
190
begin
191
        if (!reset)
192
        begin
193
                state_open_slot <= 2'd0;
194
                open_slot_fct<= 1'b0;
195
                counter_wait <= 11'd0;
196
        end
197
        else
198
        begin
199
                state_open_slot <= next_state_open_slot;
200 37 redbear
 
201 40 redbear
                case(state_open_slot)
202
                2'd0:
203
                begin
204
                        if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
205
                        begin
206
                                open_slot_fct<= 1'b1;
207
                                counter_wait <= counter_wait + 11'd1;
208
                        end
209
                        else
210
                        begin
211
                                open_slot_fct<= 1'b0;
212
                        end
213
                end
214
                2'd1:
215
                begin
216
                        if(counter_wait != 11'd300)
217
                                counter_wait <= counter_wait + 11'd1;
218
                        else
219
                                counter_wait <= counter_wait;
220
 
221
                        open_slot_fct<= 1'b1;
222
                end
223
                2'd2:
224
                begin
225
                        counter_wait <= 11'd0;
226
                        open_slot_fct<= 1'b0;
227
                end
228
                default:
229
                begin
230
                        open_slot_fct<= open_slot_fct;
231
                end
232
                endcase
233
 
234
        end
235
end
236 33 redbear
//Write pointer
237
        always@(posedge clock or negedge reset)
238
        begin
239
                if (!reset)
240
                begin
241 40 redbear
                        state_data_write <= 2'd0;
242 33 redbear
                        wr_ptr <= {(AWIDTH){1'b0}};
243
                end
244
                else
245
                begin
246 37 redbear
 
247
                        state_data_write <= next_state_data_write;
248
 
249
                        case(state_data_write)
250
                        2'd0:
251 33 redbear
                        begin
252 40 redbear
                                wr_ptr <= wr_ptr;
253 33 redbear
                        end
254 37 redbear
                        2'd1:
255 33 redbear
                        begin
256 40 redbear
                                wr_ptr <= wr_ptr;
257 33 redbear
                        end
258 37 redbear
                        2'd2:
259
                        begin
260
                                wr_ptr <= wr_ptr + 6'd1;
261
                        end
262
                        default:
263
                        begin
264
                                wr_ptr <= wr_ptr;
265
                        end
266
                        endcase
267 38 redbear
 
268 33 redbear
                end
269
        end
270
 
271
//FULL - EMPTY COUNTER
272
 
273 40 redbear
always@(posedge clock or negedge reset)
274
begin
275
 
276
        if (!reset)
277 33 redbear
        begin
278 40 redbear
                f_full  <= 1'b0;
279
                f_empty <= 1'b0;
280
                overflow_credit_error<=1'b0;
281
                counter <= {(AWIDTH){1'b0}};
282
        end
283
        else
284
        begin
285
                if(state_data_write == 2'd2)
286 33 redbear
                begin
287 40 redbear
                        counter <= counter + 6'd1;
288 33 redbear
                end
289
                else
290
                begin
291 40 redbear
                        if(counter > 6'd0 && state_data_read == 2'd2)
292
                                counter <= counter - 6'd1;
293 34 redbear
                        else
294
                                counter <= counter;
295 39 redbear
                end
296 33 redbear
 
297 40 redbear
                if(counter > 6'd56)
298
                begin
299
                        overflow_credit_error <= 1'b1;
300
                end
301
                else
302
                        overflow_credit_error <= 1'b0;
303 33 redbear
 
304 40 redbear
                if(counter == 6'd56)
305
                begin
306
                        f_full  <= 1'b1;
307
                end
308
                else
309
                begin
310
                        f_full  <= 1'b0;
311
                end
312 39 redbear
 
313 40 redbear
                if(counter == 6'd0)
314
                begin
315
                        f_empty <= 1'b1;
316
                end
317
                else
318
                begin
319
                        f_empty <= 1'b0;
320
                end
321 33 redbear
        end
322 40 redbear
end
323 33 redbear
 
324 39 redbear
 
325 33 redbear
//Read pointer
326
        always@(posedge clock or negedge reset)
327
        begin
328
                if (!reset)
329
                begin
330
                        rd_ptr <= {(AWIDTH){1'b0}};
331 37 redbear
                        state_data_read <= 2'd0;
332 33 redbear
                end
333
                else
334
                begin
335 40 redbear
 
336 37 redbear
                        state_data_read <= next_state_data_read;
337 33 redbear
 
338 37 redbear
                        case(state_data_read)
339
                        2'd0:
340 33 redbear
                        begin
341 37 redbear
                                if(rd_en)
342
                                begin
343
                                        rd_ptr     <= rd_ptr+ 6'd1;
344
                                end
345
                                else
346
                                begin
347 40 redbear
                                        rd_ptr     <= rd_ptr;
348 37 redbear
                                end
349 33 redbear
                        end
350 37 redbear
                        2'd1:
351 33 redbear
                        begin
352 40 redbear
                                rd_ptr     <= rd_ptr;
353 37 redbear
                        end
354
                        2'd2:
355 33 redbear
                        begin
356 40 redbear
                                rd_ptr     <= rd_ptr;
357 33 redbear
                        end
358 37 redbear
                        default:
359
                        begin
360
                                rd_ptr     <= rd_ptr;
361 40 redbear
 
362 37 redbear
                        end
363
                        endcase
364 34 redbear
 
365 37 redbear
 
366 33 redbear
                end
367
        end
368
 
369 40 redbear
 
370
mem_data mem_dta_fifo_rx(
371
 
372
                .clock(clock),
373
                .reset(reset),
374
 
375
                .data_in(data_in),
376
                .wr_ptr(wr_ptr),
377
                .rd_ptr(rd_ptr),
378
                .data_out(data_out)
379
);
380 33 redbear
endmodule

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