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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 12

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output rx_got_bit,
                        output rx_got_null,
                        output rx_got_nchar,
                        output rx_got_time_code,
                        output rx_got_fct,
 
                        output [8:0] rx_data_flag,
                        output rx_buffer_write,
 
                        output [7:0] rx_time_out,
                        output rx_tick_out
                 );
 
        wire [4:0] counter;
 
        reg  [4:0] counter_pos;
        reg  [4:0] counter_neg;
 
        wire posedge_clk;
        wire negedge_clk;
 
        wire [3:0] control;
        wire [9:0] data;
        wire [9:0] timecode;
 
        reg [3:0] control_l_a;
        reg [9:0] data_l_a;
        reg [9:0] timecode_l_a;
 
        reg [2:0] control_l_r;
        reg [9:0] data_l_r;
        reg [9:0] timecode_l_r;
 
        reg parity_error;
 
        reg control_found;
        reg data_found;
        reg time_code_found;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_time_code;
 
        wire data_control_up;
 
        assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1:
                                 (counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:
                                 (counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0;
 
        assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
        assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
 
        assign  counter = counter_pos + counter_neg;
 
        assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9];
        assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8];
        assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0];
        assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1];
        assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2];
        assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3];
        assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4];
        assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5];
        assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6];
        assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7];
 
        assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0];
        assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1];
        assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2];
        assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3];
        assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4];
        assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5];
        assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6];
        assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7];
        assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];
        assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];
 
        assign control[0:0]  = (counter == 5'd3)?rx_din:control[0:0];
        assign control[1:1]  = (counter == 5'd2)?rx_din:control[1:1];
        assign control[2:2]  = (counter == 5'd1)?rx_din:control[2:2];
        assign control[3:3]  = (counter == 5'd0)?rx_din:control[3:3];
 
        assign rx_got_fct       = (counter == 5'd3   & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
        assign rx_got_nchar     = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
        assign rx_got_time_code = (counter == 5'd9   & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
        assign rx_got_null      = (counter == 5'd3   & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
 
        assign rx_error         = (parity_error)?1'b1:
                                  ((counter == 5'd9 | counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0;
 
        assign rx_data_flag     = (rx_got_nchar)?data[8:0]:data_l_a[8:0];
        assign rx_buffer_write  = (rx_got_nchar & data_control_up)?1'b1:1'b0;
 
        assign rx_time_out      = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0];
        assign rx_tick_out      = (rx_got_time_code & data_control_up)?1'b1:1'b0;
 
 
always@(posedge posedge_clk or negedge rx_resetn  or posedge last_was_control)
begin
        if(!rx_resetn | last_was_control)
        begin
                counter_pos <= 5'd0;
        end
        else
        begin
                if(counter == 5'd4 & control[2:2])
                begin
                        counter_pos <= 5'd0;
                end
                else if(counter == 5'd9)
                begin
                        counter_pos <= 5'd0;
                end
                else
                begin
                        counter_pos <= counter_pos + 5'd1;
                end
        end
end
 
//
always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control)
begin
        if(!rx_resetn | last_was_control )
        begin
                counter_neg <= 5'd0;
        end
        else
        begin
                if(counter == 5'd4 & control[2:2])
                begin
                        counter_neg <= 5'd0;
                end
                else if(counter == 5'd9)
                begin
                        counter_neg <= 5'd0;
                end
                else
                begin
                        counter_neg <= counter_neg + 5'd1;
                end
        end
end
 
//parity error
always@(*)
begin
 
        parity_error = 1'b0;
 
        if(control_found && last_was_control)
        begin
                if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(control_found && last_was_data)
        begin
                if(!(data_l_a[8]^control_l_r[0]^control_l_r[1])  != data_l_a[9])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(control_found && last_was_time_code)
        begin
                if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(data_found && last_was_control)
        begin
                if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(data_found && last_was_data)
        begin
                if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(data_found && last_was_time_code)
        begin
                if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7])  != data_l_r[9])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(time_code_found && last_was_data)
        begin
                if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9])
                begin
                        parity_error = 1'b1;
                end
        end
        else if(time_code_found && last_was_control)
        begin
                if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7])  != control_l_a[3])
                begin
                        parity_error = 1'b1;
                end
        end
end
 
//
always@(*)
begin
 
        last_was_control  = 1'b0;
        last_was_data     = 1'b0;
        last_was_time_code= 1'b0;
 
        if(counter == 5'd4 & control[2:2])
        begin
                last_was_control  = 1'b1;
        end
        else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7)
        begin
                last_was_data     = 1'b1;
        end
        else if(counter == 5'd9 && control_l_a[2:0] == 3'd7)
        begin
                last_was_time_code= 1'b1;
        end
 
end
 
//
always@(posedge data_control_up or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                control_found   <= 1'b0;
                data_found      <= 1'b0;
                time_code_found <= 1'b0;
        end
        else
        begin
                control_found   <= last_was_control;
                data_found      <= last_was_data;
                time_code_found <= last_was_time_code;
        end
 
end
 
//
always@(posedge last_was_control or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                control_l_a <= 4'd4;
                control_l_r <= 3'd4;
        end
        else
        begin
                control_l_a <= control;
                control_l_r <= control_l_a[2:0];
        end
end
 
always@(posedge last_was_data or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                data_l_a <= 10'd0;
                data_l_r <= 10'd0;
        end
        else
        begin
                data_l_a <= data;
                data_l_r <= data_l_a;
        end
end
 
always@(posedge last_was_time_code or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                timecode_l_a <= 10'd0;
                timecode_l_r <= 10'd0;
        end
        else
        begin
                timecode_l_a <= timecode;
                timecode_l_r <= timecode_l_a;
        end
end
 
 
endmodule

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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42			`output rx_error,`
43
44			`output rx_got_bit,`
45			`output rx_got_null,`
46			`output rx_got_nchar,`
47			`output rx_got_time_code,`
48			`output rx_got_fct,`
49
50			`output [8:0] rx_data_flag,`
51			`output rx_buffer_write,`
52
53			`output [7:0] rx_time_out,`
54			`output rx_tick_out`
55			`);`
56
57			`wire [4:0] counter;`
58
59			`reg [4:0] counter_pos;`
60			`reg [4:0] counter_neg;`
61
62			`wire posedge_clk;`
63			`wire negedge_clk;`
64
65			`wire [3:0] control;`
66			`wire [9:0] data;`
67			`wire [9:0] timecode;`
68
69			`reg [3:0] control_l_a;`
70			`reg [9:0] data_l_a;`
71			`reg [9:0] timecode_l_a;`
72
73			`reg [2:0] control_l_r;`
74			`reg [9:0] data_l_r;`
75			`reg [9:0] timecode_l_r;`
76
77			`reg parity_error;`
78
79			`reg control_found;`
80			`reg data_found;`
81			`reg time_code_found;`
82
83			`reg last_was_control;`
84			`reg last_was_data;`
85			`reg last_was_time_code;`
86
87			`wire data_control_up;`
88
89			`assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1:`
90			`(counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:`
91			`(counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0;`
92
93			`assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;`
94			`assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;`
95
96			`assign counter = counter_pos + counter_neg;`
97
98			`assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9];`
99			`assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8];`
100			`assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0];`
101			`assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1];`
102			`assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2];`
103			`assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3];`
104			`assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4];`
105			`assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5];`
106			`assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6];`
107			`assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7];`
108
109			`assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0];`
110			`assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1];`
111			`assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2];`
112			`assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3];`
113			`assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4];`
114			`assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5];`
115			`assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6];`
116			`assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7];`
117			`assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];`
118			`assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];`
119
120	12	redbear	`assign control[0:0] = (counter == 5'd3)?rx_din:control[0:0];`
121			`assign control[1:1] = (counter == 5'd2)?rx_din:control[1:1];`
122			`assign control[2:2] = (counter == 5'd1)?rx_din:control[2:2];`
123			`assign control[3:3] = (counter == 5'd0)?rx_din:control[3:3];`
124	5	redbear
125	12	redbear	`assign rx_got_fct = (counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;`
126			`assign rx_got_nchar = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;`
127			`assign rx_got_time_code = (counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;`
128			`assign rx_got_null = (counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;`
129	5	redbear	`assign rx_got_bit = (posedge_clk)?1'b1:1'b0;`
130
131			`assign rx_error = (parity_error)?1'b1:`
132			`((counter == 5'd9 \| counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0;`
133
134			`assign rx_data_flag = (rx_got_nchar)?data[8:0]:data_l_a[8:0];`
135			`assign rx_buffer_write = (rx_got_nchar & data_control_up)?1'b1:1'b0;`
136
137			`assign rx_time_out = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0];`
138			`assign rx_tick_out = (rx_got_time_code & data_control_up)?1'b1:1'b0;`
139
140
141			`always@(posedge posedge_clk or negedge rx_resetn or posedge last_was_control)`
142			`begin`
143			`if(!rx_resetn \| last_was_control)`
144			`begin`
145			`counter_pos <= 5'd0;`
146			`end`
147			`else`
148			`begin`
149			`if(counter == 5'd4 & control[2:2])`
150			`begin`
151			`counter_pos <= 5'd0;`
152			`end`
153			`else if(counter == 5'd9)`
154			`begin`
155			`counter_pos <= 5'd0;`
156			`end`
157			`else`
158			`begin`
159			`counter_pos <= counter_pos + 5'd1;`
160			`end`
161			`end`
162			`end`
163
164			`//`
165			`always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control)`
166			`begin`
167			`if(!rx_resetn \| last_was_control )`
168			`begin`
169			`counter_neg <= 5'd0;`
170			`end`
171			`else`
172			`begin`
173			`if(counter == 5'd4 & control[2:2])`
174			`begin`
175			`counter_neg <= 5'd0;`
176			`end`
177			`else if(counter == 5'd9)`
178			`begin`
179			`counter_neg <= 5'd0;`
180			`end`
181			`else`
182			`begin`
183			`counter_neg <= counter_neg + 5'd1;`
184			`end`
185			`end`
186			`end`
187
188			`//parity error`
189			`always@(*)`
190			`begin`
191
192			`parity_error = 1'b0;`
193
194			`if(control_found && last_was_control)`
195			`begin`
196			`if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3])`
197			`begin`
198			`parity_error = 1'b1;`
199			`end`
200			`end`
201			`else if(control_found && last_was_data)`
202			`begin`
203			`if(!(data_l_a[8]^control_l_r[0]^control_l_r[1]) != data_l_a[9])`
204			`begin`
205			`parity_error = 1'b1;`
206			`end`
207			`end`
208			`else if(control_found && last_was_time_code)`
209			`begin`
210			`if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9])`
211			`begin`
212			`parity_error = 1'b1;`
213			`end`
214			`end`
215			`else if(data_found && last_was_control)`
216			`begin`
217			`if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3])`
218			`begin`
219			`parity_error = 1'b1;`
220			`end`
221			`end`
222			`else if(data_found && last_was_data)`
223			`begin`
224			`if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9])`
225			`begin`
226			`parity_error = 1'b1;`
227			`end`
228			`end`
229			`else if(data_found && last_was_time_code)`
230			`begin`
231			`if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7]) != data_l_r[9])`
232			`begin`
233			`parity_error = 1'b1;`
234			`end`
235			`end`
236			`else if(time_code_found && last_was_data)`
237			`begin`
238			`if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9])`
239			`begin`
240			`parity_error = 1'b1;`
241			`end`
242			`end`
243			`else if(time_code_found && last_was_control)`
244			`begin`
245			`if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7]) != control_l_a[3])`
246			`begin`
247			`parity_error = 1'b1;`
248			`end`
249			`end`
250			`end`
251
252			`//`
253			`always@(*)`
254			`begin`
255
256			`last_was_control = 1'b0;`
257			`last_was_data = 1'b0;`
258			`last_was_time_code= 1'b0;`
259
260			`if(counter == 5'd4 & control[2:2])`
261			`begin`
262			`last_was_control = 1'b1;`
263			`end`
264			`else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7)`
265			`begin`
266			`last_was_data = 1'b1;`
267			`end`
268			`else if(counter == 5'd9 && control_l_a[2:0] == 3'd7)`
269			`begin`
270			`last_was_time_code= 1'b1;`
271			`end`
272
273			`end`
274
275			`//`
276			`always@(posedge data_control_up or negedge rx_resetn)`
277			`begin`
278
279			`if(!rx_resetn)`
280			`begin`
281			`control_found <= 1'b0;`
282			`data_found <= 1'b0;`
283			`time_code_found <= 1'b0;`
284			`end`
285			`else`
286			`begin`
287			`control_found <= last_was_control;`
288			`data_found <= last_was_data;`
289			`time_code_found <= last_was_time_code;`
290			`end`
291
292			`end`
293
294			`//`
295			`always@(posedge last_was_control or negedge rx_resetn)`
296			`begin`
297			`if(!rx_resetn)`
298			`begin`
299			`control_l_a <= 4'd4;`
300			`control_l_r <= 3'd4;`
301			`end`
302			`else`
303			`begin`
304			`control_l_a <= control;`
305			`control_l_r <= control_l_a[2:0];`
306			`end`
307			`end`
308
309			`always@(posedge last_was_data or negedge rx_resetn)`
310			`begin`
311			`if(!rx_resetn)`
312			`begin`
313			`data_l_a <= 10'd0;`
314			`data_l_r <= 10'd0;`
315			`end`
316			`else`
317			`begin`
318			`data_l_a <= data;`
319			`data_l_r <= data_l_a;`
320			`end`
321			`end`
322
323			`always@(posedge last_was_time_code or negedge rx_resetn)`
324			`begin`
325			`if(!rx_resetn)`
326			`begin`
327			`timecode_l_a <= 10'd0;`
328			`timecode_l_r <= 10'd0;`
329			`end`
330			`else`
331			`begin`
332			`timecode_l_a <= timecode;`
333			`timecode_l_r <= timecode_l_a;`
334			`end`
335			`end`
336
337
338			`endmodule`