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redbear |
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy :
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//Clock Domains :
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//Critical Timing :
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//Test Features :
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//Asynchronous I/F :
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//Scan Methodology :
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//Instantiations :
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//Synthesizable (y/n) :
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//Other :
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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module RX_SPW (
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input rx_din,
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input rx_sin,
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input rx_resetn,
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output rx_error,
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output rx_got_bit,
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output rx_got_null,
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output rx_got_nchar,
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output rx_got_time_code,
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output rx_got_fct,
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output [8:0] rx_data_flag,
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output rx_buffer_write,
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output [7:0] rx_time_out,
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output rx_tick_out
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);
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wire [4:0] counter;
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reg [4:0] counter_pos;
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reg [4:0] counter_neg;
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wire posedge_clk;
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wire negedge_clk;
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wire [3:0] control;
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wire [9:0] data;
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wire [9:0] timecode;
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reg [3:0] control_l_a;
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reg [9:0] data_l_a;
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reg [9:0] timecode_l_a;
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reg [2:0] control_l_r;
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reg [9:0] data_l_r;
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reg [9:0] timecode_l_r;
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reg parity_error;
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reg control_found;
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reg data_found;
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reg time_code_found;
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reg last_was_control;
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reg last_was_data;
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reg last_was_time_code;
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wire data_control_up;
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assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1:
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(counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:
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(counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign counter = counter_pos + counter_neg;
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assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9];
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assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8];
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assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0];
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assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1];
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assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2];
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assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3];
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assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4];
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assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5];
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assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6];
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assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7];
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assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0];
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assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1];
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assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2];
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assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3];
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assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4];
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assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5];
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assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6];
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assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7];
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assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];
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assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];
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assign control[0:0] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:control[0:0];
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assign control[1:1] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:control[1:1];
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assign control[2:2] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:control[2:2];
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assign control[3:3] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:control[3:3];
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assign rx_got_fct = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_nchar = (!rx_resetn)?1'b0:(!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
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assign rx_got_time_code = (!rx_resetn)?1'b0:(counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
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assign rx_got_null = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_error = (parity_error)?1'b1:
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((counter == 5'd9 | counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0;
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assign rx_data_flag = (rx_got_nchar)?data[8:0]:data_l_a[8:0];
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assign rx_buffer_write = (rx_got_nchar & data_control_up)?1'b1:1'b0;
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assign rx_time_out = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0];
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assign rx_tick_out = (rx_got_time_code & data_control_up)?1'b1:1'b0;
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always@(posedge posedge_clk or negedge rx_resetn or posedge last_was_control)
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begin
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if(!rx_resetn | last_was_control)
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begin
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counter_pos <= 5'd0;
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end
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else
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begin
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if(counter == 5'd4 & control[2:2])
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begin
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counter_pos <= 5'd0;
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end
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else if(counter == 5'd9)
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begin
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counter_pos <= 5'd0;
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end
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else
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begin
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counter_pos <= counter_pos + 5'd1;
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end
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end
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end
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//
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always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control)
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begin
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if(!rx_resetn | last_was_control )
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begin
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counter_neg <= 5'd0;
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end
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else
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begin
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if(counter == 5'd4 & control[2:2])
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begin
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counter_neg <= 5'd0;
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end
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else if(counter == 5'd9)
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begin
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counter_neg <= 5'd0;
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end
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else
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begin
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counter_neg <= counter_neg + 5'd1;
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end
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end
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end
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//parity error
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always@(*)
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begin
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parity_error = 1'b0;
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if(control_found && last_was_control)
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begin
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if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3])
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begin
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parity_error = 1'b1;
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end
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end
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else if(control_found && last_was_data)
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begin
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if(!(data_l_a[8]^control_l_r[0]^control_l_r[1]) != data_l_a[9])
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begin
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parity_error = 1'b1;
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end
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end
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else if(control_found && last_was_time_code)
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begin
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if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9])
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begin
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parity_error = 1'b1;
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end
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end
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else if(data_found && last_was_control)
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begin
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if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3])
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begin
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parity_error = 1'b1;
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end
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end
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else if(data_found && last_was_data)
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begin
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if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9])
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begin
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parity_error = 1'b1;
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end
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end
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else if(data_found && last_was_time_code)
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begin
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if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7]) != data_l_r[9])
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begin
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parity_error = 1'b1;
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end
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end
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else if(time_code_found && last_was_data)
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begin
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if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9])
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begin
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parity_error = 1'b1;
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end
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end
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else if(time_code_found && last_was_control)
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begin
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if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7]) != control_l_a[3])
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begin
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parity_error = 1'b1;
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end
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end
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end
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//
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always@(*)
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begin
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last_was_control = 1'b0;
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last_was_data = 1'b0;
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last_was_time_code= 1'b0;
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if(counter == 5'd4 & control[2:2])
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begin
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last_was_control = 1'b1;
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end
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else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7)
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begin
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last_was_data = 1'b1;
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end
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else if(counter == 5'd9 && control_l_a[2:0] == 3'd7)
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begin
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last_was_time_code= 1'b1;
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end
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end
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//
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always@(posedge data_control_up or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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control_found <= 1'b0;
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data_found <= 1'b0;
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time_code_found <= 1'b0;
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end
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else
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begin
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control_found <= last_was_control;
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data_found <= last_was_data;
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time_code_found <= last_was_time_code;
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end
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end
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//
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always@(posedge last_was_control or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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control_l_a <= 4'd4;
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control_l_r <= 3'd4;
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end
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else
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begin
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control_l_a <= control;
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control_l_r <= control_l_a[2:0];
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end
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end
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always@(posedge last_was_data or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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data_l_a <= 10'd0;
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data_l_r <= 10'd0;
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end
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else
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begin
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data_l_a <= data;
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data_l_r <= data_l_a;
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end
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end
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322 |
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|
|
323 |
|
|
always@(posedge last_was_time_code or negedge rx_resetn)
|
324 |
|
|
begin
|
325 |
|
|
if(!rx_resetn)
|
326 |
|
|
begin
|
327 |
|
|
timecode_l_a <= 10'd0;
|
328 |
|
|
timecode_l_r <= 10'd0;
|
329 |
|
|
end
|
330 |
|
|
else
|
331 |
|
|
begin
|
332 |
|
|
timecode_l_a <= timecode;
|
333 |
|
|
timecode_l_r <= timecode_l_a;
|
334 |
|
|
end
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
endmodule
|