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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [systemC/] [main.cc] - Blame information for rev 40

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1 29 redbear
#include <systemc.h>
2
#include <stdio.h>
3
#include <vector>
4
#include <string>
5
#include <stdlib.h> 
6
#include <gtkmm.h>
7
#include <random>
8
#include <boost/thread.hpp>
9
 
10
using namespace std;
11
using namespace Gtk;
12
using namespace boost;
13
 
14
#include "../gladicapi/data_recorder.h"
15
#include "../gladicapi/data_check.h"
16
 
17
bool EEP_EOP;
18
 
19
unsigned int finish = 0;
20
bool link_start = false;
21
bool link_disable = false;
22
bool auto_start = false;
23
 
24
//systemc and verilog
25
bool global_reset = false;
26
 
27
//verilog variables
28
bool verilog_link_start = false;
29
bool verilog_link_disable = false;
30
bool verilog_auto_start = false;
31
int frquency_nano_second = 500;
32
 
33
vector<string> data_col_store;
34
data_recorder *REC_TX_SPW;
35
data_check    *COMPARE_SPW;
36
 
37
vector<string> data_col_store0;
38
data_recorder *REC_TX_SPWSC;
39
data_check    *COMPARE_SPW_RX;
40
 
41
unsigned long int a = 0;
42
int clock_systemc   = 2;
43
 
44
//send data systemC
45
 
46
bool start_send_data_verilog  = false;
47
bool enable_time_code_verilog = false;
48
 
49
bool start_send_data = false;
50
bool start_tick_data = false;
51
 
52
vector<sc_uint<9> > data_generated_sc;
53
sc_uint<9> intermediate_systemc;
54
sc_uint<9> intermediate_sc;
55
unsigned int data_iteration_sc_aux = 0;
56
unsigned int data_iteration_sc = 0;
57
 
58
vector<sc_uint<9> > data_generated_verilog;
59
sc_uint<9> intermediate;
60
sc_uint<9> intermediate_verilog;
61
 
62
unsigned int data_iteration = 0;
63
unsigned int data_iteration_vlog = 0;
64
sc_uint<9> intermediate_data;
65
 
66 40 redbear
 
67
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys);
68
 
69 29 redbear
#include "top_spw.h"
70
 
71
//Data generation
72 40 redbear
unsigned long int max_data = 255;
73 29 redbear
 
74
std::random_device rd;
75
std::uniform_int_distribution<unsigned long int> data_in(0,255);
76 40 redbear
std::uniform_int_distribution<unsigned long int> nchar(1,max_data);//eop-eep
77 29 redbear
 
78
class sc_TOP_SPW;
79
 
80
SC_MODULE(sc_TOP_SPW)
81
{
82
 
83
        sc_clock CLOCK;
84
        sc_signal<bool>  RESET;
85
        sc_signal<bool> LINK_START;
86
        sc_signal<bool> LINK_DISABLE;
87
        sc_signal<bool> AUTO_START;
88
        sc_signal<sc_uint<4> > FSM_SPW_OUT;
89
        sc_signal<sc_uint<4> > FSM_TX;
90
 
91
        sc_signal<sc_uint<10> > CLOCK_GEN;
92
        sc_signal<bool> E_SEND_DATA;
93
 
94
 
95
        sc_signal<bool> BUFFER_READY;
96
        sc_signal<sc_uint<9> > DATARX_FLAG;
97
        sc_signal<bool> BUFFER_WRITE;
98
 
99
        sc_signal<sc_uint<8> > TIME_OUT;
100
        sc_signal<bool> TICK_OUT;
101
        sc_signal<bool> CONTROL_FLAG_OUT;
102
 
103
        sc_signal<uint> DOUT;
104
        sc_signal<uint> SOUT;
105
        sc_signal<uint>  DIN;
106
        sc_signal<uint>  SIN;
107
 
108
        sc_TOP DUT;
109
 
110
        SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
111
                           RESET("RESET"),
112
                           LINK_DISABLE("LINK_DISABLE"),
113
                           LINK_START("LINK_START"),
114
                           AUTO_START("AUTO_START"),
115
                           FSM_SPW_OUT("FSM_SPW_OUT"),
116
                           CLOCK_GEN("CLOCK_GEN"),
117
                           E_SEND_DATA("E_SEND_DATA"),
118
                           DOUT("DOUT"),
119
                           SOUT("SOUT"),
120
 
121
                           FSM_TX("FSM_TX"),
122
                           DIN("DIN"),
123
                           SIN("SIN"),
124
                           BUFFER_READY("BUFFER_READY"),
125
                           DATARX_FLAG("DATARX_FLAG"),
126
                           BUFFER_WRITE("BUFFER_WRITE"),
127
                           TIME_OUT("TIME_OUT"),
128
                           TICK_OUT("TICK_OUT"),
129
                           CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
130
 
131
 
132
        DUT("DUT") {
133
        DUT.CLOCK(CLOCK);
134
        DUT.RESET(RESET);
135
        DUT.LINK_DISABLE(LINK_DISABLE);
136
        DUT.AUTO_START(AUTO_START);
137
        DUT.LINK_START(LINK_START);
138
        DUT.FSM_SPW_OUT(FSM_SPW_OUT);
139
        DUT.CLOCK_GEN(CLOCK_GEN);
140
        DUT.E_SEND_DATA(E_SEND_DATA);
141
        DUT.FSM_TX(FSM_TX);
142
        DUT.DOUT(DOUT);
143
        DUT.SOUT(SOUT);
144
 
145
        DUT.DIN(DIN);
146
        DUT.SIN(SIN);
147
        DUT.BUFFER_READY(BUFFER_READY);
148
        DUT.DATARX_FLAG(DATARX_FLAG);
149
        DUT.BUFFER_WRITE(BUFFER_WRITE);
150
        DUT.TIME_OUT(TIME_OUT);
151
        DUT.TICK_OUT(TICK_OUT);
152
        DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
153
 
154
        cout << "SC_CTOR(sc_TOP_SPW)" << endl;
155
        }
156
 
157
};
158
 
159
Glib::RefPtr<Gtk::Builder> builder;
160
 
161
Gtk::Window *window;
162
 
163
Gtk::Button *BtnFinsihSimulation;
164
Gtk::Button *BtnLinkEnable;
165
Gtk::Button *BtnLinkDisable;
166
Gtk::Button *BtnAutoStart;
167
Gtk::Button *BtnReset;
168
 
169
Gtk::Button *BtnSpaceWireVerilog;
170
Gtk::CheckButton *CheckbtnLinkEnable;
171
Gtk::CheckButton *CheckbtnAutoStart;
172
Gtk::CheckButton *CheckbtnLinkDisable;
173
 
174
//Execute test
175
Gtk::Button *BtnSimpleTest;
176
Gtk::CheckButton *CheckBtnEop;
177
Gtk::CheckButton *CheckBtnEep;
178
Gtk::CheckButton *CheckBtnTimeCode;
179
 
180
//Generate data
181
Gtk::Button *BtnGenerationDataVerilog;
182
Gtk::CheckButton *CheckBtnEopGenVerilog;
183
Gtk::CheckButton *CheckBtnEepGenVerilog;
184
Gtk::CheckButton *CheckBtnTimeCodeGenVerilog;
185
 
186
Gtk::Button *BtnTxFrequency;
187
Gtk::Entry  *EntryFrequency;
188
 
189
Gtk::Button *BtnChangeFrequencyVerilog;
190
Gtk::Entry  *EntryFrequencyVerilog;
191
 
192
Gtk::Button *BtnSendDataScTx;
193
Gtk::Button *BtnTimeCodeScTx;
194
Gtk::Button *BtnGenerateDataSc;
195
 
196
Gtk::CheckButton *CheckBtnEepGenSystemC;
197
Gtk::CheckButton *CheckBtnEopGenSystemC;
198
 
199
 
200
Gtk::Label *lblStatus;
201
 
202
 
203
sc_TOP_SPW *sn_top;
204
 
205
extern "C" Control_SC* create_object()
206
{
207
  return new Control_SC;
208
}
209
 
210
extern "C" void destroy_object( Control_SC* object )
211
{
212
  delete object;
213
}
214
 
215
/*GTKMM CONTROL*/
216
void on_BtnFinsihSimulation_clicked()
217
{
218
        cout<< "End Simulation" <<endl;
219
        Gtk::Main::quit();
220
        finish = 1;
221
        REC_TX_SPW->endsimulation();
222
        REC_TX_SPWSC->endsimulation();
223
}
224
 
225
void on_BtnLinkEnable_clicked()
226
{
227
        link_start = !link_start;
228
}
229
 
230
void on_BtnLinkDisable_clicked()
231
{
232
        link_disable = !link_disable;
233
}
234
 
235
void on_BtnAutoStart_clicked()
236
{
237
        auto_start = !auto_start;
238
}
239
 
240
void on_BtnReset_clicked()
241
{
242
        global_reset = !global_reset;
243
}
244
 
245
 
246
void on_BtnSpaceWireVerilog_clicked()
247
{
248
 
249
 
250
        if(!CheckbtnLinkEnable->get_active())
251
        {
252
                verilog_link_start = false;
253
                lblStatus->set_text("LINKENABLE VERILOG IS OFF");
254
        }
255
 
256
        if(!CheckbtnAutoStart->get_active())
257
        {
258
                verilog_auto_start = false;
259
                lblStatus->set_text("AUTOSTART VERILOG IS OFF");
260
        }
261
 
262
        if(!CheckbtnLinkDisable->get_active())
263
        {
264
                verilog_link_disable = false;
265
                lblStatus->set_text("AUTOSTART VERILOG IS OFF");
266
        }
267
 
268
        if(CheckbtnLinkEnable->get_active())
269
        {
270
                verilog_link_start = true;
271
                lblStatus->set_text("LINKENABLE VERILOG IS ON");
272
        }
273
 
274
        if(CheckbtnAutoStart->get_active())
275
        {
276
                verilog_auto_start = true;
277
                lblStatus->set_text("AUTOSTART VERILOG IS ON");
278
        }
279
 
280
        if(CheckbtnLinkDisable->get_active())
281
        {
282
                verilog_link_disable = true;
283
                lblStatus->set_text("LINKDISABLE VERILOG IS ON");
284
        }
285
 
286
}
287
 
288
 
289
void on_BtnSimpleTest_clicked()
290
{
291
 
292
        if(CheckBtnEopGenVerilog->get_active())
293
        {
294
                start_send_data_verilog = true;
295
        }
296
        else
297
        {
298
                start_send_data_verilog = false;
299
        }
300
 
301
        if(CheckBtnTimeCodeGenVerilog->get_active())
302
        {
303
                enable_time_code_verilog = true;
304
        }
305
        else
306
        {
307
                enable_time_code_verilog = false;
308
        }
309
 
310
}
311
 
312
void on_BtnGenerationDataVerilog_clicked()
313
{
314
        data_generated_verilog.clear();
315
        data_iteration=0;
316
        data_iteration_vlog=0;
317
        if(CheckBtnEopGenVerilog->get_active())
318
        {
319 40 redbear
                for(int cnt_max_data = 0; cnt_max_data < max_data;cnt_max_data++)
320 29 redbear
                {
321 40 redbear
                        if(cnt_max_data >= 0 && cnt_max_data < max_data)
322 29 redbear
                        {
323
                                intermediate_verilog(7,0) = data_in(rd);
324
                                intermediate_verilog(8,8) = 0;
325 40 redbear
 
326
                                data_generated_verilog.push_back(intermediate_verilog);
327 29 redbear
                        }
328 40 redbear
                        intermediate_verilog=0;
329
 
330 29 redbear
                }
331 40 redbear
 
332
                intermediate_verilog(8,8) = 1;
333
                intermediate_verilog(7,0) = 0;
334
 
335
                data_generated_verilog.push_back(intermediate_verilog);
336
                intermediate_verilog=0;
337 29 redbear
        }else if(CheckBtnEepGenVerilog->get_active())
338
        {
339
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
340
                {
341
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
342
                        {
343
                                intermediate_verilog(8,8) = 1;
344
                                intermediate_verilog(7,0) = 1;
345
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
346
                        {
347
                                intermediate_verilog(7,0) = data_in(rd);
348
                                intermediate_verilog(8,8) = 0;
349
                        }
350 40 redbear
                        else
351
                        {
352
                                intermediate_verilog(7,0) = data_in(rd);
353
                                intermediate_verilog(8,8) = 0;
354
                        }
355 29 redbear
                        data_generated_verilog.push_back(intermediate_verilog);
356 40 redbear
                        intermediate_verilog=0;
357 29 redbear
                }
358
                intermediate_verilog(7,0) = 1;
359
                intermediate_verilog(8,8) = 1;
360
                data_generated_verilog[nchar(rd)] = intermediate_verilog;
361
        }
362
}
363
 
364
void on_BtnTxFrequency_clicked()
365
{
366
 
367
        string aux = EntryFrequency->get_text();
368
        switch(atoi(aux.c_str()))
369
        {
370
                case 2:
371
                        sn_top->CLOCK_GEN = 1;
372
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 2MHz");
373
                break;
374
                case 10:
375
                        sn_top->CLOCK_GEN = 2;
376
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 10MHz");
377
                break;
378
                case 20:
379
                        sn_top->CLOCK_GEN = 4;
380
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 20MHz");
381
                break;
382
                case 50:
383
                        sn_top->CLOCK_GEN = 8;
384
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 50MHz");
385
                break;
386
                case 100:
387
                        sn_top->CLOCK_GEN = 16;
388
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 100MHz");
389
                break;
390
                case 150:
391
                        sn_top->CLOCK_GEN = 32;
392
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 150MHz");
393
                break;
394
                case 200:
395
                        sn_top->CLOCK_GEN = 64;
396
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 200MHz");
397
                break;
398
                case 201:
399
                        sn_top->CLOCK_GEN = 128;
400
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 201MHz");
401
                break;
402
                case 250:
403
                        sn_top->CLOCK_GEN = 256;
404
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 250MHz");
405
                break;
406
                case 280:
407
                        sn_top->CLOCK_GEN = 512;
408
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 280MHz");
409
                break;
410
        }
411
 
412
}
413
 
414
void on_BtnTimeCodeScTx_clicked()
415
{
416
        start_tick_data = !start_tick_data;
417
        if(start_tick_data)
418
        {lblStatus->set_text("TIME CODE ENABLED ON TX SYSTEMC");}
419
        else
420
        {lblStatus->set_text("TIME CODE DISABLED ON TX SYSTEMC");}
421
}
422
 
423
void on_BtnSendDataScTx_clicked()
424
{
425
        start_send_data = !start_send_data;
426
        if(start_send_data)
427
        {lblStatus->set_text("SEND DATA ENABLED TX SYSTEMC");}
428
        else
429
        {lblStatus->set_text("SEND DATA DISABLED TX SYSTEMC");}
430
}
431
 
432
void on_BtnGenerateDataSc_clicked()
433
{
434
        data_generated_sc.clear();
435
        data_iteration_sc_aux=0;
436
        data_iteration_sc=0;
437
        if(CheckBtnEopGenSystemC->get_active())
438
        {
439 40 redbear
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
440 29 redbear
                {
441 40 redbear
                        if(cnt_max_data > 0 && cnt_max_data < max_data)
442 29 redbear
                        {
443
                                intermediate_sc(7,0) = data_in(rd);
444
                                intermediate_sc(8,8) = 0;
445
                        }
446
                        data_generated_sc.push_back(intermediate_sc);
447
                }
448 40 redbear
 
449
                intermediate_sc(8,8) = 1;
450
                intermediate_sc(7,0) = 0;
451
 
452
                data_generated_sc.push_back(intermediate_verilog);
453
                intermediate_sc=0;
454
 
455 29 redbear
        }else if(CheckBtnEepGenSystemC->get_active())
456
        {
457
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
458
                {
459
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
460
                        {
461
                                intermediate_sc(8,8) = 1;
462
                                intermediate_sc(7,0) = 1;
463
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
464
                        {
465
                                intermediate_sc(7,0) = data_in(rd);
466
                                intermediate_sc(8,8) = 0;
467
                        }
468
                        data_generated_sc.push_back(intermediate_sc);
469
                }
470
                intermediate_sc(7,0) = 1;
471
                intermediate_sc(8,8) = 1;
472
                data_generated_sc[nchar(rd)] = intermediate_sc;
473
        }
474
}
475
 
476
 
477
void on_BtnChangeFrequencyVerilog_clicked()
478
{
479
        string aux = EntryFrequencyVerilog->get_text();
480
 
481
        switch(atoi(aux.c_str()))
482
        {
483
                case 2:
484
                        frquency_nano_second = 500;
485
                break;
486
                case 10:
487
                        frquency_nano_second = 100;
488
                break;
489
                case 20:
490
                        frquency_nano_second = 50;
491
                break;
492
                case 50:
493
                        frquency_nano_second = 20;
494
                break;
495
                case 100:
496
                        frquency_nano_second = 10;
497
                break;
498
                case 150:
499
                        frquency_nano_second = 7;
500
                break;
501
                case 200:
502
                        frquency_nano_second = 5;
503
                break;
504
                case 201:
505
                        frquency_nano_second = 4;
506
                break;
507
                case 250:
508
                        frquency_nano_second = 4;
509
                break;
510
                case 280:
511
                        frquency_nano_second = 3;
512
                break;
513
                default:
514
                        frquency_nano_second = 500;
515
                break;
516
        }
517
 
518
}
519
 
520
void thread_gtkmm_run()
521
{
522
        //GRAPHICAL INTERFACE
523
        Main Application(true);
524
        builder = Gtk::Builder::create_from_file("SpaceWrireTestSuit.glade");
525
 
526
        builder->get_widget("SpaceWireTestStress", window);
527
        builder->get_widget("BtnFinsihSimulation", BtnFinsihSimulation);
528
        builder->get_widget("BtnLinkEnable", BtnLinkEnable);
529
        builder->get_widget("BtnLinkDisable", BtnLinkDisable);
530
        builder->get_widget("BtnAutoStart", BtnAutoStart);
531
        builder->get_widget("BtnReset", BtnReset);
532
 
533
        builder->get_widget("BtnSpaceWireVerilog", BtnSpaceWireVerilog);
534
        builder->get_widget("CheckbtnLinkDisable", CheckbtnLinkDisable);
535
        builder->get_widget("CheckbtnAutoStart", CheckbtnAutoStart);
536
        builder->get_widget("CheckbtnLinkEnable", CheckbtnLinkEnable);
537
 
538
        builder->get_widget("BtnGenerationDataVerilog", BtnGenerationDataVerilog);
539
        builder->get_widget("BtnSimpleTest", BtnSimpleTest);
540
        builder->get_widget("CheckBtnEopGenVerilog", CheckBtnEopGenVerilog);
541
        builder->get_widget("CheckBtnEepGenVerilog", CheckBtnEepGenVerilog);
542
        builder->get_widget("CheckBtnTimeCodeGenVerilog", CheckBtnTimeCodeGenVerilog);
543
 
544
        builder->get_widget("BtnChangeFrequencyVerilog", BtnChangeFrequencyVerilog);
545
        builder->get_widget("EntryFrequencyVerilog", EntryFrequencyVerilog);
546
 
547
        builder->get_widget("BtnTxFrequency", BtnTxFrequency);
548
        builder->get_widget("EntryFrequency", EntryFrequency);
549
 
550
        builder->get_widget("BtnSendDataScTx", BtnSendDataScTx);
551
        builder->get_widget("BtnTimeCodeScTx", BtnTimeCodeScTx);
552
        builder->get_widget("BtnGenerateDataSc", BtnGenerateDataSc);
553
        builder->get_widget("CheckBtnEepGenSystemC", CheckBtnEepGenSystemC);
554
        builder->get_widget("CheckBtnEopGenSystemC", CheckBtnEopGenSystemC);
555
 
556
        builder->get_widget("lblStatus",lblStatus);
557
 
558
        BtnFinsihSimulation->signal_clicked().connect(sigc::ptr_fun(&on_BtnFinsihSimulation_clicked));
559
        BtnLinkEnable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkEnable_clicked));
560
        BtnLinkDisable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkDisable_clicked));
561
        BtnAutoStart->signal_clicked().connect(sigc::ptr_fun(&on_BtnAutoStart_clicked));
562
        BtnReset->signal_clicked().connect(sigc::ptr_fun(&on_BtnReset_clicked));
563
 
564
        BtnSpaceWireVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnSpaceWireVerilog_clicked));
565
 
566
        BtnSimpleTest->signal_clicked().connect(sigc::ptr_fun(&on_BtnSimpleTest_clicked));
567
 
568
        BtnChangeFrequencyVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnChangeFrequencyVerilog_clicked));
569
 
570
        BtnGenerationDataVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerationDataVerilog_clicked));
571
 
572
        BtnTxFrequency->signal_clicked().connect(sigc::ptr_fun(&on_BtnTxFrequency_clicked));
573
 
574
        BtnSendDataScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnSendDataScTx_clicked));
575
        BtnTimeCodeScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnTimeCodeScTx_clicked));
576
        BtnGenerateDataSc->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerateDataSc_clicked));
577
 
578
        window->set_title("GLADIC SPACEWIRE TEST TOOL");
579
 
580
        Application.run(*window);
581
}
582
 
583
Control_SC::Control_SC()
584
{
585
        clock_systemc  = 2;
586
        sn_top = new sc_TOP_SPW("sc_TOP_SPW");
587
        boost::thread workerThreadGTKMM(thread_gtkmm_run);
588
 
589
        data_col_store.push_back("CONTROL TYPE");
590
        data_col_store.push_back("NUMBER GENERATED");
591
        data_col_store.push_back("NUMBER RECEIVED");
592
        data_col_store.push_back("COMPARE");
593
        data_col_store.push_back("TIME STAMP");
594
        REC_TX_SPW = new data_recorder("test_suit_vlog_sc.html",data_col_store,"test_suit_vlog_sc.html","TX VERILOG 2 RX SYSTEMC");
595
        REC_TX_SPW->initialize();
596
        COMPARE_SPW = new data_check();
597
        data_col_store.clear();
598
 
599
        data_col_store0.push_back("CONTROL TYPE");
600
        data_col_store0.push_back("NUMBER GENERATED");
601
        data_col_store0.push_back("NUMBER RECEIVED");
602
        data_col_store0.push_back("COMPARE");
603
        data_col_store0.push_back("TIME STAMP");
604
        REC_TX_SPWSC = new data_recorder("test_suit_sc_vlog.html",data_col_store0,"test_suit_sc_vlog.html","TX SYSTEMC 2 RX VERILOG");
605
        COMPARE_SPW_RX = new data_check();
606
        REC_TX_SPWSC->initialize();
607
        data_col_store0.clear();
608
}
609
 
610
void Control_SC::init()
611
{
612
 
613
        sn_top->RESET     = true;
614
 
615
        sn_top->LINK_DISABLE  = false;
616
        sn_top->LINK_START    = false;
617
        sn_top->AUTO_START = false;
618
 
619
        sn_top->E_SEND_DATA = false;
620
 
621
        sn_top->CLOCK_GEN = 1;
622
        frquency_nano_second = 500;
623
}
624
 
625
void autostart()
626
{
627
        if(auto_start)
628
        {
629
                sn_top->AUTO_START = true;
630
                //lblStatus->set_text("AUTOSTART ENABLED ON TX SYSTEMC");
631
        }
632
        else
633
        {
634
                sn_top->AUTO_START = false;
635
                //lblStatus->set_text("AUTOSTART DISABLED ON TX SYSTEMC");
636
        }
637
}
638
 
639
void linkstart()
640
{
641
        if(link_start)
642
        {
643
                sn_top->LINK_START = true;
644
                //lblStatus->set_text("LINKSTART ENABLED ON TX SYSTEMC");
645
        }
646
        else
647
        {
648
                sn_top->LINK_START = false;
649
                //lblStatus->set_text("LINKSTART DISABLED ON TX SYSTEMC");
650
        }
651
}
652
 
653
void linkdisable()
654
{
655
        if(link_disable)
656
        {
657
                sn_top->LINK_DISABLE = true;
658
                //lblStatus->set_text("LINKDISABLE ENABLED ON TX SYSTEMC");
659
        }
660
        else
661
        {
662
                sn_top->LINK_DISABLE = false;
663
                //lblStatus->set_text("LINKDISABLE DISABLED ON TX SYSTEMC");
664
        }
665
}
666
 
667
void send_data_tx_sc()
668
{
669
        if(start_send_data)
670
        {
671
                sn_top->E_SEND_DATA = true;
672
        }
673
        else
674
        {
675
                sn_top->E_SEND_DATA = false;
676
        }
677
 
678
}
679
 
680
void Control_SC::run_sim()
681
{
682
 
683
        autostart();
684
        linkstart();
685
        linkdisable();
686
        send_data_tx_sc();
687
 
688
        sc_start(clock_systemc,SC_NS);
689
 
690
}
691
 
692
/*        END OF SIMULATION      */
693
void Control_SC::stop_sim()
694
{
695
        sc_stop();
696
}
697
 
698
/*         RESET HIGH           */
699
bool Control_SC::reset_set()
700
{
701
 
702
        if(global_reset)
703
        {
704
                sn_top->RESET = false;
705
        }else
706
        {
707
                sn_top->RESET = true;
708
        }
709
 
710
        return sn_top->RESET;
711
}
712
 
713
unsigned int Control_SC::get_value_dout()
714
{
715
        return sn_top->DOUT.read();
716
}
717
 
718
unsigned int Control_SC::get_value_sout()
719
{
720
        return sn_top->SOUT.read();
721
}
722
 
723
void Control_SC::set_rx_sin(unsigned int strobe)
724
{
725
        sn_top->SIN = strobe;
726
}
727
 
728
void Control_SC::set_rx_din(unsigned int data)
729
{
730
        sn_top->DIN = data;
731
}
732
 
733
unsigned int Control_SC::get_spw_fsm()
734
{
735
        return sn_top->FSM_SPW_OUT.read();
736
}
737
 
738
unsigned int  Control_SC::finish_simulation()
739
{
740
        return finish;
741
}
742
 
743
//verilog variables
744
bool Control_SC::verilog_linkenable()
745
{
746
        return verilog_link_start;
747
}
748
 
749
bool Control_SC::verilog_autostart()
750
{
751
        return verilog_auto_start;
752
}
753
 
754
bool Control_SC::verilog_linkdisable()
755
{
756
        return verilog_link_disable;
757
}
758
 
759
float Control_SC::verilog_frequency()
760
{
761
        return frquency_nano_second;
762
}
763
 
764
//Test verilog
765
bool Control_SC::start_tx_test()
766
{
767
        return start_send_data_verilog;
768
}
769
 
770
bool Control_SC::enable_time_code_tx_test()
771
{
772
        return enable_time_code_verilog;
773
}
774
 
775
void Control_SC::end_tx_test()
776
{
777
        start_send_data_verilog = enable_time_code_verilog = false;
778
}
779
 
780 40 redbear
int Control_SC::size_data_test_vlog()
781 29 redbear
{
782 40 redbear
        return data_generated_verilog.size();
783 29 redbear
}
784
 
785 40 redbear
int Control_SC::size_data_test_sc()
786
{
787
        return data_generated_sc.size();
788
}
789
 
790 29 redbear
unsigned int Control_SC::take_data(unsigned int a)
791
{
792
        intermediate = data_generated_verilog[a];
793
        return intermediate(8,0);
794
}
795
 
796
void Control_SC::data_o(unsigned int data, unsigned int pos)
797
{
798
                sc_uint<9> intermediate = data;
799
 
800
                data_col_store0.clear();
801
                if(data_iteration_sc <= data_generated_sc.size()-1)
802
                {
803
                        data_col_store0.push_back("DATA");
804
 
805
                        intermediate_sc=data_generated_sc[pos];
806
                        data_col_store0.push_back(intermediate_sc.to_string(SC_HEX));
807
 
808
                        data_col_store0.push_back(intermediate.to_string(SC_HEX));
809
 
810
                        data_col_store0.push_back(" ");
811
                        COMPARE_SPW_RX->compare_test(&data_col_store0);
812
 
813
                        data_col_store0.push_back(sc_time_stamp().to_string());
814
                        REC_TX_SPWSC->storedata(data_col_store0);
815
                        data_iteration_sc++;
816
                }else
817
                {
818
                        data_iteration_sc = 0;
819
                }
820
}
821
 
822 40 redbear
 
823
void  Control_SC::data_rx_vlog_loopback_o(unsigned int data, unsigned int pos)
824
{
825
 
826
        sc_uint<9> intermediate;
827
 
828
        data_col_store.clear();
829
 
830
        data_col_store.push_back("DATA");
831
        intermediate = data_generated_verilog[pos];
832
        data_col_store.push_back(intermediate.to_string(SC_HEX));
833
 
834
        intermediate = data;
835
        data_col_store.push_back(intermediate(8,0).to_string(SC_HEX));
836
        data_col_store.push_back(" ");
837
        COMPARE_SPW->compare_test(&data_col_store);
838
 
839
        data_col_store.push_back(sc_time_stamp().to_string());
840
        REC_TX_SPW->storedata(data_col_store);
841
}
842
 
843
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys)
844
{
845
        data_col_store.clear();
846
 
847
        switch(type_char)
848
        {
849
                case 0:
850
                        data_col_store.push_back("NULL");
851
                        data_col_store.push_back(" - ");
852
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
853
                        data_col_store.push_back(" - ");
854
                        data_col_store.push_back(sc_time_stamp().to_string());
855
                        REC_TX_SPW->storedata(data_col_store);
856
                break;
857
                case 1:
858
                        data_col_store.push_back("FCT");
859
                        data_col_store.push_back(" - ");
860
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
861
                        data_col_store.push_back(" - ");
862
                        data_col_store.push_back(sc_time_stamp().to_string());
863
                        REC_TX_SPW->storedata(data_col_store);
864
                break;
865
                case 2:
866
                        data_col_store.push_back("EOP");
867
                        intermediate_data = data_generated_verilog[data_iteration];
868
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
869
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
870
                        data_col_store.push_back(" ");
871
                        COMPARE_SPW->compare_test(&data_col_store);
872
                        data_iteration++;
873
                        data_col_store.push_back(sc_time_stamp().to_string());
874
                        REC_TX_SPW->storedata(data_col_store);
875
                break;
876
                case 3:
877
                        data_col_store.push_back("EEP");
878
                        intermediate_data = data_generated_verilog[data_iteration];
879
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
880
 
881
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
882
                        data_col_store.push_back(" ");
883
                        COMPARE_SPW->compare_test(&data_col_store);
884
                        data_iteration++;
885
 
886
                        data_col_store.push_back(sc_time_stamp().to_string());
887
                        REC_TX_SPW->storedata(data_col_store);
888
                break;
889
                case 4:
890
                        data_col_store.push_back("INVALID CONNECTION");
891
                        data_col_store.push_back(" - ");
892
                        data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
893
                        data_col_store.push_back(" - ");
894
                        data_col_store.push_back(sc_time_stamp().to_string());
895
                        REC_TX_SPW->storedata(data_col_store);
896
                break;
897
                case 5:
898
                        data_col_store.push_back("DATA");
899
                        intermediate_data = data_generated_verilog[data_iteration];
900
                        data_col_store.push_back(intermediate_data.to_string(SC_HEX));
901
 
902
                        data_col_store.push_back(data(8,0).to_string(SC_HEX));
903
                        data_col_store.push_back(" ");
904
                        COMPARE_SPW->compare_test(&data_col_store);
905
 
906
                        data_col_store.push_back(sc_time_stamp().to_string());
907
                        REC_TX_SPW->storedata(data_col_store);
908
                        data_iteration++;
909
                break;
910
                case 6:
911
                        data_col_store.push_back("TIMECODE");
912
                        data_col_store.push_back(" - ");
913
                        data_col_store.push_back(timecode_sys(7,0).to_string());
914
                        data_col_store.push_back(" - ");
915
                        data_col_store.push_back(sc_time_stamp().to_string());
916
                        REC_TX_SPW->storedata(data_col_store);
917
                break;
918
        }
919
 
920
}
921
 
922 29 redbear
unsigned int Control_SC::clock_tx()
923
{
924
        return sn_top->DUT.CLOCK_TX_OUT.read();
925
}
926
 

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