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[/] [spidac/] [trunk/] [testbench/] [dac_tb.vhd] - Blame information for rev 6

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-- Engineer: Armandas JaruĊĦauskas (jarusauskas@gmail.com www.armandas.lt)
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-- 
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-- Create date: 2010-08-03
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-- Design name: Testbench for LTC2624 Quad 12 Bit DAC Controller 
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-----------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity dac_tb is
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end dac_tb;
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architecture behaviour of dac_tb is
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    constant T: time := 20 ns;
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    signal clk, reset: std_logic;
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    signal mosi, sck, cs, ready: std_logic;
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    signal data, old_data: std_logic_vector(31 downto 0);
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begin
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    -- clock generator
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    process
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    begin
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        clk <= '1';
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        wait for T / 2;
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        clk <= '0';
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        wait for T / 2;
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    end process;
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    -- initial reset
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    reset <= '1', '0' after T / 2;
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    testbench:
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    process
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        variable value: std_logic_vector(11 downto 0);
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        variable addr: std_logic_vector(3 downto 0);
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        variable command: std_logic_vector(3 downto 0);
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    begin
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        value := "010000000000";
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        addr := "0010";
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        command := "0011";
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        data <= "00000000" & command & addr & value & "0000";
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        old_data <= "00000000" & command & addr & value & "0000";
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        -- testing bit order in the 32-bit word
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        for i in 31 downto 0 loop
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            wait until rising_edge(sck);
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            assert mosi = data(i)
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                report "Bit mismatch! (Order)"
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                severity error;
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        end loop;
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        -- testing data latching
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        for i in 31 downto 0 loop
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            wait until rising_edge(sck);
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            if i = 24 then
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                data <= "10010101110101101010101110100110"; --(others => '1');
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            end if;
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            assert mosi = old_data(i)
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                report "Bit mismatch! (Latching)"
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                severity error;
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        end loop;
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        -- what's happening after that?
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        for i in 63 downto 0 loop
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            wait until rising_edge(sck);
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        end loop;
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        -- end of simulation
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        assert false
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            report "Simulation completed."
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            severity failure;
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    end process;
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    uut: entity work.dac_control
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    port map(
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        clk => clk,
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        rst => reset,
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        dac_mosi => mosi,
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        dac_sck => sck,
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        dac_cs => cs,
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        rdy => ready,
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        dac_data => data
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    );
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end behaviour;

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