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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Blame information for rev 153

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1 131 creep
alu_chk.e
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<'
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import alu_components;
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unit alu_chk_u {
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        reg_a : byte;
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        reg_x : byte;
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        reg_y : byte;
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        reg_status : byte;
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        reg_result : byte;
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        inst : alu_input_s;
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        next_inst : alu_input_s;
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        count_cycles : int;
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        first_cycle : bool;
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        keep first_cycle == TRUE;
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        keep count_cycles == 0;
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        store(input : alu_input_s) is {
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                count_cycles = count_cycles + 1;
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                //out ("CYCLE ", count_cycles, " STORE:");
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                //print input;
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                if (first_cycle) {
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                        inst = input;
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                        next_inst = input;
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                }
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                else {
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                        inst = next_inst;
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                        next_inst = input;
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                };
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        };
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        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
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                if (first_cycle) {
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                        first_cycle = FALSE;
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                        reg_x = 0;
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                        reg_y = 0;
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                        reg_status = 8'b00100010;
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                        reg_a = 0; // TODO: check this
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                        reg_result = 0;
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                }
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                else {
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                        //out ("CYCLE ", count_cycles, " COMPARE:");
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                        //print inst;
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                        case inst.input_kind {
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                                ENABLED_VALID: {
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                                        //out("CYCLE ", count_cycles, ": executing and comparing");
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                                        execute();
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                                };
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                                DISABLED_VALID: {
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                                        //out("CYCLE ", count_cycles, ": just comparing");
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                                };
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                                RESET: {
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                                        reg_x = 0;
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                                        reg_y = 0;
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                                        reg_status = 8'b00100010;
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                                        reg_a = 0; // TODO: check this
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                                        reg_result = 0;
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                                        return;
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                                };
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                                default: {
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                                        dut_error("error at e code");
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                                };
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                        };
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                        // here i have already calculated. must compare!
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                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
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                                out("#########################################################");
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                                print me;
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                                out("#########################################################");
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                                print alu_result;
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                                print alu_status;
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                                print alu_x;
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                                print alu_y;
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                                dut_error("WRONG!");
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                        };
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                };
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        };
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        execute() is {
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                case inst.alu_opcode {
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                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
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                        ADC_ZPG: { exec_sum(); };
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                        ADC_ZPX: { exec_sum(); };
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                        ADC_ABS: { exec_sum(); };
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                        ADC_ABX: { exec_sum(); };
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                        ADC_ABY: { exec_sum(); };
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                        ADC_IDX: { exec_sum(); };
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                        ADC_IDY: { exec_sum(); };
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                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
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                        AND_ZPG: { exec_and(); };
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                        AND_ZPX: { exec_and(); };
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                        AND_ABS: { exec_and(); };
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                        AND_ABX: { exec_and(); };
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                        AND_ABY: { exec_and(); };
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                        AND_IDX: { exec_and(); };
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                        AND_IDY: { exec_and(); };
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                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
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                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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                        ASL_ZPX: { exec_asl_mem(); };
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                        ASL_ABS: { exec_asl_mem(); };
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                        ASL_ABX: { exec_asl_mem(); };
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                        BCC_REL: {};
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                        BCS_REL: {};
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                        BEQ_REL: {};
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                        default: {
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                                //dut_error("unknown opcode");
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                        }
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                };
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        };
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        exec_asl_acc() is {
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                reg_status[0:0] = reg_a[7:7];
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                reg_a = reg_a * 2;
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                update_z(reg_a);
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                update_n(reg_a);
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                reg_result = reg_a;
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        };
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        exec_asl_mem() is {
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                reg_status[0:0] = inst.alu_a[7:7];
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                reg_result = inst.alu_a * 2;
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                update_z(reg_result);
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                update_n(reg_result);
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        };
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        exec_and() is {
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                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
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                update_z(reg_a);
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                update_n(reg_a);
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                reg_result = reg_a;
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        };
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        exec_sum() is {
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                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
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                reg_result = reg_a + inst.alu_a + reg_status[0:0];
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                update_c(reg_a, inst.alu_a, reg_status[0:0]);
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                update_v(reg_a, inst.alu_a, reg_result);
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                update_z(reg_result);
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                update_n(reg_result);
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                reg_a = reg_result;
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                //print me;
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                //dut_error();
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        };
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        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
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                if (arg1 + arg2 + arg3 > 255) {
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                        reg_status[0:0] = 1;
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                }
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                else {
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                        reg_status[0:0] = 0;
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                }
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        };
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        update_v(op1 : byte, op2 : byte, res : byte) is {
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                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
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                        reg_status[6:6] = 1;
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                }
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                else {
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                        reg_status[6:6] = 0;
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                };
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        };
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        update_z(arg : byte) is {
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                if (arg == 0) {
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                        reg_status[1:1] = 1;
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                }
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                else {
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                        reg_status[1:1] = 0;
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                }
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        };
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        update_n(arg : byte) is {
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                if (arg[7:7] == 1) {
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                        reg_status[7:7] = 1;
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                }
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                else {
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                        reg_status[7:7] = 0;
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                }
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        };
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};
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'>

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