OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Blame information for rev 234

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 creep
alu_chk.e
2
<'
3
import alu_components;
4
 
5
unit alu_chk_u {
6
        reg_a : byte;
7
        reg_x : byte;
8
        reg_y : byte;
9
        reg_status : byte;
10 135 creep
        reg_result : byte;
11 131 creep
 
12 159 creep
        !inst : alu_input_s;
13
        !next_inst : alu_input_s;
14 132 creep
 
15 131 creep
        count_cycles : int;
16
        first_cycle : bool;
17 159 creep
        last_a : byte;
18
        last_status : byte;
19
        last_result : byte;
20 182 creep
        rst_counter : byte;
21 131 creep
 
22
        keep first_cycle == TRUE;
23
        keep count_cycles == 0;
24 182 creep
        keep rst_counter == 0;
25 131 creep
 
26 182 creep
        event T3_cover_event;
27
        cover T3_cover_event is {
28
                item rst_counter; // using num_of_buckets=100;
29
        };
30
 
31
 
32 131 creep
        store(input : alu_input_s) is {
33 134 creep
                count_cycles = count_cycles + 1;
34
 
35 153 creep
                //out ("CYCLE ", count_cycles, " STORE:");
36
                //print input;
37 132 creep
 
38 159 creep
                last_a = reg_a;
39
                last_status = reg_status;
40
                last_result = reg_result;
41
 
42 132 creep
                if (first_cycle) {
43
                        inst = input;
44
                        next_inst = input;
45
                }
46
                else {
47
                        inst = next_inst;
48
                        next_inst = input;
49
                };
50
 
51 131 creep
        };
52
 
53
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
54
                if (first_cycle) {
55
                        first_cycle = FALSE;
56 143 creep
                        reg_x = 0;
57
                        reg_y = 0;
58
                        reg_status = 8'b00100010;
59 185 creep
                        reg_a = 0;
60 135 creep
                        reg_result = 0;
61 131 creep
                }
62 132 creep
                else {
63 185 creep
                        //out ("CYCLE ", count_cycles, " COMPARE:");
64
                        //print inst;
65 134 creep
 
66 159 creep
                        if (count_cycles == 99999) {
67
                                out("ENOUGH!");
68
                                stop_run();
69
                        };
70
 
71 182 creep
                        if (inst.input_kind == RESET) {
72
                                rst_counter = rst_counter + 1;
73
                        }
74
                        else {
75
                                emit T3_cover_event;
76
                                rst_counter = 0;
77
                        };
78
 
79 132 creep
                        case inst.input_kind {
80
                                ENABLED_VALID: {
81 153 creep
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
82 185 creep
                                        execute(inst.alu_opcode);
83
 
84
                                        if (reg_status[3:3] == 1) {
85
                                                case inst.alu_opcode {
86
                                                        SBC_IMM: {
87
                                                                reg_a = alu_result;
88
                                                                reg_result = alu_result;
89
                                                                reg_status = alu_status;
90
                                                        };
91
                                                        SBC_ZPG: {
92
                                                                reg_a = alu_result;
93
                                                                reg_result = alu_result;
94
                                                                reg_status = alu_status;
95
                                                        };
96
                                                        SBC_ZPX: {
97
                                                                reg_a = alu_result;
98
                                                                reg_result = alu_result;
99
                                                                reg_status = alu_status;
100
                                                        };
101
                                                        SBC_ABS: {
102
                                                                reg_a = alu_result;
103
                                                                reg_result = alu_result;
104
                                                                reg_status = alu_status;
105
                                                        };
106
                                                        SBC_ABX: {
107
                                                                reg_a = alu_result;
108
                                                                reg_result = alu_result;
109
                                                                reg_status = alu_status;
110
                                                        };
111
                                                        SBC_ABY: {
112
                                                                reg_a = alu_result;
113
                                                                reg_result = alu_result;
114
                                                                reg_status = alu_status;
115
                                                        };
116
                                                        SBC_IDX: {
117
                                                                reg_a = alu_result;
118
                                                                reg_result = alu_result;
119
                                                                reg_status = alu_status;
120
                                                        };
121
                                                        SBC_IDY: {
122
                                                                reg_a = alu_result;
123
                                                                reg_result = alu_result;
124
                                                                reg_status = alu_status;
125
                                                        };
126
                                                };
127
                                        };
128 132 creep
                                };
129 143 creep
                                RESET: {
130 146 creep
                                        reg_x = 0;
131
                                        reg_y = 0;
132
                                        reg_status = 8'b00100010;
133
                                        reg_a = 0; // TODO: check this
134
                                        reg_result = 0;
135
 
136 143 creep
                                        return;
137
                                };
138 182 creep
                                ENABLED_RAND: {
139 185 creep
                                        execute(inst.rand_op.as_a(valid_opcodes));
140
 
141
                                        if (reg_status[3:3] == 1) {
142
                                                case inst.rand_op.as_a(valid_opcodes) {
143
                                                        SBC_IMM: {
144
                                                                reg_a = alu_result;
145
                                                                reg_result = alu_result;
146
                                                                reg_status = alu_status;
147
                                                        };
148
                                                        SBC_ZPG: {
149
                                                                reg_a = alu_result;
150
                                                                reg_result = alu_result;
151
                                                                reg_status = alu_status;
152
                                                        };
153
                                                        SBC_ZPX: {
154
                                                                reg_a = alu_result;
155
                                                                reg_result = alu_result;
156
                                                                reg_status = alu_status;
157
                                                        };
158
                                                        SBC_ABS: {
159
                                                                reg_a = alu_result;
160
                                                                reg_result = alu_result;
161
                                                                reg_status = alu_status;
162
                                                        };
163
                                                        SBC_ABX: {
164
                                                                reg_a = alu_result;
165
                                                                reg_result = alu_result;
166
                                                                reg_status = alu_status;
167
                                                        };
168
                                                        SBC_ABY: {
169
                                                                reg_a = alu_result;
170
                                                                reg_result = alu_result;
171
                                                                reg_status = alu_status;
172
                                                        };
173
                                                        SBC_IDX: {
174
                                                                reg_a = alu_result;
175
                                                                reg_result = alu_result;
176
                                                                reg_status = alu_status;
177
                                                        };
178
                                                        SBC_IDY: {
179
                                                                reg_a = alu_result;
180
                                                                reg_result = alu_result;
181
                                                                reg_status = alu_status;
182
                                                        };
183
                                                };
184
                                        };
185
 
186 182 creep
                                };
187 132 creep
                                default: {
188
                                };
189
                        };
190
 
191 133 creep
                        // here i have already calculated. must compare!
192 143 creep
 
193 146 creep
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
194 153 creep
                                out("#########################################################");
195 135 creep
                                print me;
196 155 creep
                                print me.inst;
197 153 creep
                                out("#########################################################");
198 134 creep
                                print alu_result;
199 135 creep
                                print alu_status;
200
                                print alu_x;
201
                                print alu_y;
202
 
203 133 creep
                                dut_error("WRONG!");
204
                        };
205 146 creep
                };
206 131 creep
        };
207 132 creep
 
208 185 creep
        execute(opcode : valid_opcodes) is {
209
                case opcode {
210 132 creep
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
211
                        ADC_ZPG: { exec_sum(); };
212
                        ADC_ZPX: { exec_sum(); };
213
                        ADC_ABS: { exec_sum(); };
214
                        ADC_ABX: { exec_sum(); };
215
                        ADC_ABY: { exec_sum(); };
216
                        ADC_IDX: { exec_sum(); };
217
                        ADC_IDY: { exec_sum(); };
218
 
219 133 creep
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
220 132 creep
                        AND_ZPG: { exec_and(); };
221
                        AND_ZPX: { exec_and(); };
222
                        AND_ABS: { exec_and(); };
223
                        AND_ABX: { exec_and(); };
224
                        AND_ABY: { exec_and(); };
225
                        AND_IDX: { exec_and(); };
226
                        AND_IDY: { exec_and(); };
227
 
228 135 creep
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
229 132 creep
 
230 135 creep
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
231
                        ASL_ZPX: { exec_asl_mem(); };
232
                        ASL_ABS: { exec_asl_mem(); };
233
                        ASL_ABX: { exec_asl_mem(); };
234
 
235 155 creep
                        BCC_REL: {}; // nothing is done. these are all branches.
236 153 creep
                        BCS_REL: {};
237
                        BEQ_REL: {};
238 155 creep
                        BMI_REL: {};
239
                        BNE_REL: {};
240
                        BPL_REL: {};
241
                        BVC_REL: {};
242
                        BVS_REL: {};
243 153 creep
 
244 155 creep
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
245
                        BIT_ABS: { exec_bit(); };
246
 
247
                        BRK_IMP: { reg_status[4:4] = 1; };
248
 
249
                        CLC_IMP: { reg_status[0:0] = 0; };
250
                        CLD_IMP: { reg_status[3:3] = 0; };
251
                        CLI_IMP: { reg_status[2:2] = 0; };
252
                        CLV_IMP: { reg_status[6:6] = 0; };
253
 
254 159 creep
                        CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
255
                        CMP_ZPG: { exec_cmp(reg_a); };
256
                        CMP_ZPX: { exec_cmp(reg_a); };
257
                        CMP_ABS: { exec_cmp(reg_a); };
258
                        CMP_ABX: { exec_cmp(reg_a); };
259
                        CMP_ABY: { exec_cmp(reg_a); };
260
                        CMP_IDX: { exec_cmp(reg_a); };
261
                        CMP_IDY: { exec_cmp(reg_a); };
262
 
263
                        CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
264
                        CPX_ZPG: { exec_cmp(reg_x); };
265
                        CPX_ABS: { exec_cmp(reg_x); };
266
 
267
                        CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
268
                        CPY_ZPG: { exec_cmp(reg_y); };
269
                        CPY_ABS: { exec_cmp(reg_y); };
270
 
271
                        DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
272
                        DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
273
                        DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
274
                        DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
275
 
276
                        DEX_IMP: { exec_dec(reg_x, FALSE); };  // X,Z,N = X-1
277
                        DEY_IMP: { exec_dec(reg_y, FALSE); };  // Y,Z,N = Y-1
278
 
279
                        EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
280
                        EOR_ZPG: { exec_eor(); };
281
                        EOR_ZPX: { exec_eor(); };
282
                        EOR_ABS: { exec_eor(); };
283
                        EOR_ABX: { exec_eor(); };
284
                        EOR_ABY: { exec_eor(); };
285
                        EOR_IDX: { exec_eor(); };
286
                        EOR_IDY: { exec_eor(); };
287
 
288
                        INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
289
                        INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
290
                        INC_ABS: { exec_inc(inst.alu_a, TRUE); };
291
                        INC_ABX: { exec_inc(inst.alu_a, TRUE); };
292
 
293
                        INX_IMP: { exec_inc(reg_x, FALSE); };
294
                        INY_IMP: { exec_inc(reg_y, FALSE); };
295
 
296
                        JMP_ABS: {};
297
                        JMP_IND: {};
298
                        JSR_ABS: {};
299
 
300
                        LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
301
                        LDA_ZPG: { exec_load(reg_a, TRUE); };
302
                        LDA_ZPX: { exec_load(reg_a, TRUE); };
303
                        LDA_ABS: { exec_load(reg_a, TRUE); };
304
                        LDA_ABX: { exec_load(reg_a, TRUE); };
305
                        LDA_ABY: { exec_load(reg_a, TRUE); };
306
                        LDA_IDX: { exec_load(reg_a, TRUE); };
307
                        LDA_IDY: { exec_load(reg_a, TRUE); };
308
 
309
                        LDX_IMM: { exec_load(reg_x, FALSE); };
310
                        LDX_ZPG: { exec_load(reg_x, FALSE); };
311
                        LDX_ZPY: { exec_load(reg_x, FALSE); };
312
                        LDX_ABS: { exec_load(reg_x, FALSE); };
313
                        LDX_ABY: { exec_load(reg_x, FALSE); };
314
 
315
                        LDY_IMM: { exec_load(reg_y, FALSE); };
316
                        LDY_ZPG: { exec_load(reg_y, FALSE); };
317
                        LDY_ZPX: { exec_load(reg_y, FALSE); };
318
                        LDY_ABS: { exec_load(reg_y, FALSE); };
319
                        LDY_ABX: { exec_load(reg_y, FALSE); };
320
 
321
                        LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
322
                        LSR_ZPG: { exec_lsr(inst.alu_a); };
323
                        LSR_ZPX: { exec_lsr(inst.alu_a); };
324
                        LSR_ABS: { exec_lsr(inst.alu_a); };
325
                        LSR_ABX: { exec_lsr(inst.alu_a); };
326
 
327
                        NOP_IMP: {};
328
 
329
                        ORA_IMM: { exec_or(); }; // A,Z,N = A|M
330
                        ORA_ZPG: { exec_or(); };
331
                        ORA_ZPX: { exec_or(); };
332
                        ORA_ABS: { exec_or(); };
333
                        ORA_ABX: { exec_or(); };
334
                        ORA_ABY: { exec_or(); };
335
                        ORA_IDX: { exec_or(); };
336
                        ORA_IDY: { exec_or(); };
337
 
338
                        PHA_IMP: { reg_result = reg_a; };
339
                        PHP_IMP: {}; // P is always connected and the result is not updated
340
                        PLA_IMP: {
341
                                reg_a = inst.alu_a;
342
                                reg_result = inst.alu_a;
343
                                update_z(reg_a);
344
                                update_n(reg_a);
345
                        };
346
                        PLP_IMP: {
347
                                reg_status = inst.alu_a;
348
                                reg_status[5:5] = 1; // this is always one
349
                        };
350
 
351 185 creep
                        ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
352 177 creep
                        ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
353
                        ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
354
                        ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
355
                        ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
356 185 creep
                        ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
357 177 creep
                        ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
358
                        ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
359
                        ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
360
                        ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
361 160 creep
 
362 177 creep
                        RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
363
                        RTS_IMP: { };
364
 
365
                        SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
366
                        SBC_ZPG: { exec_sub(); };
367
                        SBC_ZPX: { exec_sub(); };
368
                        SBC_ABS: { exec_sub(); };
369
                        SBC_ABX: { exec_sub(); };
370
                        SBC_ABY: { exec_sub(); };
371
                        SBC_IDX: { exec_sub(); };
372
                        SBC_IDY: { exec_sub(); };
373
 
374
                        SEC_IMP: { reg_status[0:0] = 1; };
375
                        SED_IMP: { reg_status[3:3] = 1; };
376
                        SEI_IMP: { reg_status[2:2] = 1; };
377
 
378
                        STA_ZPG: { reg_result = reg_a; };
379
                        STA_ZPX: { reg_result = reg_a; };
380
                        STA_ABS: { reg_result = reg_a; };
381
                        STA_ABX: { reg_result = reg_a; };
382
                        STA_ABY: { reg_result = reg_a; };
383
                        STA_IDX: { reg_result = reg_a; };
384
                        STA_IDY: { reg_result = reg_a; };
385 182 creep
                        STX_ZPG: { };
386
                        STX_ZPY: { };
387
                        STX_ABS: { };
388
                        STY_ZPG: { };
389
                        STY_ZPX: { };
390
                        STY_ABS: { };
391 177 creep
 
392 182 creep
                        TAX_IMP: { exec_transfer(reg_a, reg_x); };
393
                        TAY_IMP: { exec_transfer(reg_a, reg_y); };
394
                        TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
395
                        TXA_IMP: { exec_transfer(reg_x, reg_a); };
396
                        TXS_IMP: { };
397 185 creep
                        TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
398 177 creep
 
399 185 creep
                        // note: tya and txa do not update the result register
400
 
401 132 creep
                        default: {
402 182 creep
                                // all the random generated opcodes will fall here
403 132 creep
                        }
404
                };
405
        };
406
 
407 177 creep
        exec_transfer(source : byte, dest : *byte) is {
408
                dest = source;
409
                update_z(dest);
410
                update_n(dest);
411
        };
412
 
413
        exec_sub() is {
414 233 creep
                if (reg_status[3:3] == 1) { // decimal
415 177 creep
                        var op1 : int;
416
                        var op2 : int;
417
 
418 185 creep
                        warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
419
 
420 177 creep
                        //out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
421
 
422
                        op1 = inst.alu_a[3:0];
423
                        op2 = inst.alu_a[7:4];
424
 
425
                        op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
426
                        op2 = reg_a[7:4] - op2;
427
 
428
                        if (op1 >= 10) {
429
                                op2 = op2  + op1/10;
430
                                op1 = op1 % 10;
431
                        } else if (op1 < 0) {
432
                                op2 = op2 - op1/10;
433
                                op1 = -(op1 % 10);
434
                        };
435
 
436 182 creep
                        reg_status[0:0] = 1;
437
 
438 177 creep
                        if (op2 >= 10) {
439
                                op2 = op2 % 10;
440
                        }
441
                        else if (op2 < 0) {
442
                                op2 = op2 + 10;
443
                                reg_status[0:0] = 0;
444
                        };
445
 
446
                        reg_result[3:0] = op1;
447 185 creep
                        reg_result[7:4] = op2;
448 233 creep
 
449
                        update_n(reg_result);
450
                        update_z(reg_result);
451
                        update_v(reg_a, inst.alu_a, reg_result);
452
                        reg_a = reg_result;
453 177 creep
                }
454
                else {
455 233 creep
                        var temp: int;
456
 
457
                        temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
458
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
459
 
460
                        reg_status[7:7] = temp[7:7]; // N
461 234 creep
                        //print  (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
462 233 creep
                        reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
463
 
464
                        if (reg_result == 0) {
465
                                reg_status[1:1] = 1; // Z
466
                        } else {
467
                                reg_status[1:1] = 0; // Z
468
                        };
469
 
470
                        reg_a = temp.as_a(byte);
471
 
472 234 creep
                        //print  (temp & 0xff00);
473
                        //print (temp & 0xff00) != 0x0000;
474 233 creep
 
475
                        if ( (temp & 0xff00) != 0x0000 ) {
476 177 creep
                                reg_status[0:0] = 0;
477 233 creep
                        } else {
478
                                reg_status[0:0] = 1;
479 177 creep
                        }
480 233 creep
 
481 177 creep
                };
482
        };
483
 
484 185 creep
        exec_rot(left : bool, arg1 : byte) is {
485 160 creep
                var oldcarry : bit;
486
 
487 177 creep
                if (left) {
488
                        oldcarry = reg_status[0:0];
489
                        reg_status[0:0] = arg1[7:7];
490 185 creep
                        reg_result = arg1 << 1;
491
                        reg_result[0:0] = oldcarry;
492 177 creep
                }
493
                else {
494
                        oldcarry = reg_status[0:0];
495
                        reg_status[0:0] = arg1[0:0];
496 185 creep
                        reg_result = arg1 >> 1;
497
                        reg_result[7:7] = oldcarry;
498 177 creep
                };
499 160 creep
 
500 185 creep
                update_z(reg_result);
501
                update_n(reg_result);
502 160 creep
        };
503
 
504 159 creep
        exec_or() is {
505
                reg_a = reg_a | inst.alu_a;
506
                reg_result = reg_a;
507
                update_z(reg_a);
508
                update_n(reg_a);
509
        };
510
 
511
        exec_lsr(arg1 : *byte) is {
512
                reg_status[0:0] = arg1[0:0];
513
                arg1 = arg1 >> 1;
514
                update_z(arg1);
515
                update_n(arg1);
516
                reg_result = arg1;
517
        };
518
 
519
        exec_load(arg1 : *byte, update_result : bool) is {
520
                arg1 = inst.alu_a;
521
 
522
                if (update_result) { //
523
                        reg_result = inst.alu_a; // no need for this but...
524
                };
525
                update_z(arg1);
526
                update_n(arg1);
527
        };
528
 
529
        exec_inc(arg1 : *byte, update_result : bool) is {
530
                arg1 = arg1 + 1;
531
                update_z(arg1);
532
                update_n(arg1);
533
 
534
                if (update_result) { //
535
                        reg_result = arg1;
536
                };
537
        };
538
 
539
        exec_eor() is {
540
                reg_a = reg_a ^ inst.alu_a;
541
                reg_result = reg_a;
542
                update_z(reg_a);
543
                update_n(reg_a);
544
        };
545
 
546
        exec_dec(arg1 : *byte, update_result : bool) is {
547
                arg1 = arg1 - 1;
548
                update_z(arg1);
549
                update_n(arg1);
550
 
551
                if (update_result) { // DEX and DEY do not output the result
552
                        reg_result = arg1;
553
                };
554
        };
555
 
556
        exec_cmp(arg1 : byte) is {
557
                update_z(arg1 - inst.alu_a);
558
                update_n(arg1 - inst.alu_a);
559
 
560
                if (arg1 >= inst.alu_a) {
561
                        reg_status[0:0] = 1;
562
                }
563
                else {
564
                        reg_status[0:0] = 0;
565
                };
566
        };
567
 
568 155 creep
        exec_bit() is {
569
                update_z(reg_a & inst.alu_a);
570
                reg_status[7:7] = inst.alu_a[7:7];
571
                reg_status[6:6] = inst.alu_a[6:6];
572
        };
573
 
574 135 creep
        exec_asl_acc() is {
575
                reg_status[0:0] = reg_a[7:7];
576
                reg_a = reg_a * 2;
577
                update_z(reg_a);
578
                update_n(reg_a);
579
                reg_result = reg_a;
580
        };
581
 
582
        exec_asl_mem() is {
583
                reg_status[0:0] = inst.alu_a[7:7];
584
                reg_result = inst.alu_a * 2;
585
                update_z(reg_result);
586
                update_n(reg_result);
587
        };
588
 
589 132 creep
        exec_and() is {
590 133 creep
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
591
                update_z(reg_a);
592
                update_n(reg_a);
593 135 creep
                reg_result = reg_a;
594 132 creep
        };
595
 
596
        exec_sum() is {
597 153 creep
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
598 160 creep
                if (reg_status[3:3] == 1) {
599
                        var op1 : byte;
600
                        var op2 : byte;
601 234 creep
                        var aux : byte;
602 160 creep
 
603 177 creep
                        //out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
604 170 creep
 
605 234 creep
                        op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
606
                        print op1;
607
                        //Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
608 160 creep
 
609 234 creep
                        op2 = reg_a[7:4] + inst.alu_a[7:4];
610
                        //carry_aux = reg_a[7:4] + inst.alu_a[7:4];
611
                        print op2;
612
                        //Int32 hi = (A & 0xf0) + (operand & 0xf0);
613
 
614
                        aux = op1 + op2;
615
 
616
                        if (aux[7:0] == 0) {
617
                                reg_status[1:1] = 1;
618 160 creep
                        }
619
                        else {
620 234 creep
                                reg_status[1:1] = 0;
621 160 creep
                        };
622 234 creep
                        //notZ = (lo+hi) & 0xff;
623
 
624
                        if (op1 > 0x09) {
625
                                op2 += 0x01;
626
                                op1 += 0x06;
627
                        };
628
 
629
                        reg_status[7:7] = op2[3:3];
630
                        //N = hi & 0x80;
631
 
632
                        reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
633
                        //V = ~(A ^ operand) & (A ^ hi) & 0x80;
634
                        print op2;
635
                        if (op2 > 0x09) {
636
                                op2 += 0x06;
637
                                print op2;
638
                        };
639
                        //if (hi > 0x90) hi += 0x60;
640
 
641
                        reg_status[0:0] = (op2 > 15) ? 1 : 0;
642
                        //C = hi & 0xff00;
643
 
644
                        reg_a[3:0] = op1[3:0];
645
                        reg_a[7:4] = op2[3:0];
646
                        //reg_a = (lo & 0x0f) + (hi & 0xf0);
647 160 creep
 
648 234 creep
                        reg_result = reg_a;
649 160 creep
                }
650 233 creep
                else { // stella checked
651 160 creep
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
652 233 creep
                        update_n(reg_result);
653 160 creep
                        update_v(reg_a, inst.alu_a, reg_result);
654
                        update_z(reg_result);
655 233 creep
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
656
 
657 160 creep
                        reg_a = reg_result;
658
                };
659 132 creep
        };
660
 
661 143 creep
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
662 153 creep
                if (arg1 + arg2 + arg3 > 255) {
663 132 creep
                        reg_status[0:0] = 1;
664
                }
665
                else {
666
                        reg_status[0:0] = 0;
667
                }
668
        };
669
 
670 146 creep
        update_v(op1 : byte, op2 : byte, res : byte) is {
671
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
672
                        reg_status[6:6] = 1;
673
                }
674
                else {
675
                        reg_status[6:6] = 0;
676
                };
677
        };
678
 
679
        update_z(arg : byte) is {
680
                if (arg == 0) {
681
                        reg_status[1:1] = 1;
682
                }
683
                else {
684
                        reg_status[1:1] = 0;
685
                }
686
        };
687
 
688
 
689 132 creep
        update_n(arg : byte) is {
690
                if (arg[7:7] == 1) {
691
                        reg_status[7:7] = 1;
692
                }
693
                else {
694
                        reg_status[7:7] = 0;
695
                }
696
        };
697 131 creep
};
698
'>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.