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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [stubs.v] - Blame information for rev 255

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1 252 creep
////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// T6507LP IP Core                                                    ////
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////                                                                    ////
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//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
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////                                                                    ////
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//// Description                                                        ////
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//// 6507 stubs for the pad cells                                       ////
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////                                                                    ////
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//// TODO:                                                              ////
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//// - Nothing                                                          ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
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////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
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//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
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//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
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//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module ICP (PAD, PI, GND5O, GND5R, VDD5O, VDD5R, CLAMPC, PO, Y);
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        input PAD;
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        input PI;
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        input GND5O;
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        input GND5R;
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        input VDD5O;
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        input VDD5R;
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        input CLAMPC;
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        output PO;
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        output Y;
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endmodule
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module BT4P (A, EN, GND5O, GND5R, VDD5O, VDD5R, CLAMPC, PAD);
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        input A;
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        input EN;
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        input GND5O;
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        input GND5R;
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        input VDD5O;
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        input VDD5R;
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        input CLAMPC;
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        output PAD;
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endmodule
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module CORNERCLMP (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
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        input CLAMPC;
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        input VDD5O;
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        input VDD5R;
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        input GND5O;
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        input GND5R;
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endmodule
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module GND5ALLPADP (VDD5O, VDD5R, CLAMPC, GND);
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        input CLAMPC;
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        input VDD5O;
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        input VDD5R;
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        input GND;
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endmodule
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module VDD5ALLPADP (GND5O, GND5R, CLAMPC, VDD);
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        input CLAMPC;
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        input GND5O;
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        input GND5R;
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        input VDD;
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endmodule
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module FILLERP_110 (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
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        input CLAMPC;
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        input VDD5O;
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        input VDD5R;
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        input GND5O;
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        input GND5R;
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endmodule

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