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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t2600_kb_tb.v] - Blame information for rev 230
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// T2600LP IP Core ////
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//// ////
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//// This file is part of the T2600LP project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// Description ////
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//// t2600 keyboard controller ////
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//// ////
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//// TODO: ////
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//// ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module t2600_kb_tb();
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// all inputs are regs
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reg clk;
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reg reset_n;
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reg kd;
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reg kc;
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// all outputs are wires
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wire [15:0] io_lines;
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always #10 clk <= ~clk;
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initial begin
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clk = 1'b0;
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reset_n = 1'b1;
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kd = 1'b0;
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kc = 1'b0;
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#10;
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reset_n = 1'b0;
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#40000;
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$finish;
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end
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always @(clk) begin
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kc = $random;
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kd = $random;
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end
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T2600_KB T2600_KB (
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.CLK (clk),
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.RST (reset_n),
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.io_lines (io_lines),
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.KC (kc),
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.KD (kd)
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);
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endmodule
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