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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 174

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1 141 creep
////////////////////////////////////////////////////////////////////////////
2 152 gabrielosh
////                                                                    ////
3
//// T6507LP IP Core                                                    ////
4
////                                                                    ////
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//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
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////                                                                    ////
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//// Description                                                        ////
9
//// 6507 ALU                                                           ////
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////                                                                    ////
11
//// To Do:                                                             ////
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//// - Search for TODO                                                  ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
18 141 creep
////////////////////////////////////////////////////////////////////////////
19 152 gabrielosh
////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
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////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
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//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
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//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
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//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
43 141 creep
////////////////////////////////////////////////////////////////////////////
44
 
45
`include "timescale.v"
46
 
47
// TODO: verify code identation
48
 
49
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
50
 
51
input wire       clk;
52
input wire       reset_n;
53
input wire       alu_enable;
54
input wire [7:0] alu_opcode;
55
input wire [7:0] alu_a;
56
output reg [7:0] alu_result;
57
output reg [7:0] alu_status;
58
output reg [7:0] alu_x;
59
output reg [7:0] alu_y;
60
 
61
reg [7:0] A;
62
reg [7:0] X;
63
reg [7:0] Y;
64
 
65
reg [7:0] STATUS;
66
reg [7:0] result;
67 152 gabrielosh
reg [7:0] op1;
68
reg [7:0] op2;
69 161 gabrielosh
reg [7:0] bcdl;
70
reg [7:0] bcdh;
71 164 gabrielosh
reg [7:0] bcdh2;
72
reg [7:0] AL;
73
reg [7:0] AH;
74 173 gabrielosh
reg C_aux;
75
reg sign;
76 141 creep
 
77
`include "t6507lp_package.v"
78
 
79
always @ (posedge clk or negedge reset_n)
80
begin
81
        if (reset_n == 0) begin
82
                alu_result <= 0;
83
                alu_status[C] <= 0;
84
                alu_status[N] <= 0;
85
                alu_status[V] <= 0;
86 148 gabrielosh
                alu_status[5] <= 1;
87 141 creep
                alu_status[Z] <= 1;
88
                alu_status[I] <= 0;
89
                alu_status[B] <= 0;
90
                alu_status[D] <= 0;
91
                A <= 0;
92
                X <= 0;
93
                Y <= 0;
94
                alu_x <= 0;
95
                alu_y <= 0;
96
        end
97
        else if ( alu_enable == 1 ) begin
98
                case (alu_opcode)
99
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
100
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
101
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
102
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
103
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
104
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
105
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
106
                        begin
107
                                A          <= result;
108
                                alu_result <= result;
109
                                alu_status <= STATUS;
110
                        end
111
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
112
                        begin
113
                                X          <= result;
114
                                alu_x      <= result;
115
                                alu_status <= STATUS;
116
                        end
117
                        TXS_IMP :
118
                        begin
119 148 gabrielosh
                                X          <= result;
120
                                alu_x      <= result;
121 141 creep
                        end
122
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
123
                        begin
124
                                Y          <= result;
125
                                alu_y      <= result;
126
                                alu_status <= STATUS;
127
                        end
128 148 gabrielosh
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
129 165 gabrielosh
                        CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
130 141 creep
                        begin
131
                                alu_status <= STATUS;
132
                        end
133 158 gabrielosh
                        PHA_IMP :
134
                        begin
135
                                alu_result <= result;
136
                        end
137 141 creep
                        SEC_IMP :
138
                        begin
139
                                alu_status[C] <= 1;
140
                        end
141
                        SED_IMP :
142
                        begin
143
                                alu_status[D] <= 1;
144
                        end
145
                        SEI_IMP :
146
                        begin
147
                                alu_status[I] <= 1;
148
                        end
149
                        CLC_IMP :
150
                        begin
151
                                alu_status[C] <= 0;
152
                        end
153
                        CLD_IMP :
154
                        begin
155
                                alu_status[D] <= 0;
156
                        end
157
                        CLI_IMP :
158
                        begin
159
                                alu_status[I] <= 0;
160
                        end
161
                        CLV_IMP :
162
                        begin
163
                                alu_status[V] <= 0;
164
                        end
165
                        BRK_IMP :
166
                        begin
167 154 gabrielosh
                                alu_status[B] <= 1;
168 141 creep
                        end
169 171 creep
                        PLP_IMP, RTI_IMP :
170 141 creep
                        begin
171 172 gabrielosh
                                alu_status[C] <= STATUS[C];
172
                                alu_status[Z] <= STATUS[Z];
173
                                alu_status[I] <= STATUS[I];
174
                                alu_status[D] <= STATUS[D];
175
                                alu_status[B] <= STATUS[B];
176
                                alu_status[V] <= STATUS[V];
177
                                alu_status[N] <= STATUS[N];
178 173 gabrielosh
                                alu_status[5] <= 1;
179 141 creep
                        end
180
                        BIT_ZPG, BIT_ABS :
181
                        begin
182
                                alu_status[Z] <= STATUS[Z];
183
                                alu_status[V] <= alu_a[6];
184
                                alu_status[N] <= alu_a[7];
185
                        end
186 148 gabrielosh
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
187
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
188
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
189 141 creep
                        begin
190
                                alu_result <= result;
191
                                alu_status <= STATUS;
192
                        end
193 173 gabrielosh
                        //PHP_IMP : begin
194
                        //end
195 141 creep
                        default : begin
196
                                //$display("ERROR");
197
                        end
198
                endcase
199
        end
200
end
201
 
202
always @ (*) begin
203 152 gabrielosh
        op1      = A;
204
        op2      = alu_a;
205 150 gabrielosh
        result    = alu_result;
206
        STATUS[N] = alu_status[N];
207
        STATUS[C] = alu_status[C];
208
        STATUS[V] = alu_status[V];
209
        STATUS[B] = alu_status[B];
210
        STATUS[I] = alu_status[I];
211
        STATUS[D] = alu_status[D];
212
        STATUS[Z] = alu_status[Z];
213
        STATUS[N] = alu_status[N];
214 151 gabrielosh
        STATUS[5] = 1;
215 141 creep
 
216 171 creep
        bcdl = 0;
217
        bcdh = 0;
218
        bcdh2 = 0;
219
        AL = 0;
220
        AH = 0;
221 173 gabrielosh
        sign = op2[7];
222 171 creep
 
223 141 creep
        case (alu_opcode)
224
                // BIT - Bit Test
225
                BIT_ZPG, BIT_ABS: begin
226
                        result = A & alu_a;
227
                end
228
 
229
                // BRK - Force Interrupt
230
                BRK_IMP: begin
231
                        STATUS[B] = 1'b1;
232
                end
233
 
234
                // CLC - Clear Carry Flag
235
                CLC_IMP: begin
236
                        STATUS[C] = 1'b0;
237
                end
238
 
239
                // CLD - Clear Decimal Flag
240
                CLD_IMP: begin
241
                        STATUS[D] = 1'b0;
242
                end
243
 
244
                // CLI - Clear Interrupt Disable
245
                CLI_IMP: begin
246
                        STATUS[I] = 1'b0;
247
                end
248
 
249
                // CLV - Clear Overflow Flag
250
                CLV_IMP: begin
251
                        STATUS[V] = 1'b0;
252
                end
253
 
254
                // NOP - No Operation
255
                //NOP_IMP: begin
256
                        // Do nothing :-D
257
                //end
258
 
259
                // PLP - Pull Processor Status Register
260 171 creep
                PLP_IMP, RTI_IMP: begin
261 141 creep
                        STATUS = alu_a;
262
                end
263 157 gabrielosh
 
264
                PLA_IMP : begin
265
                        result = alu_a;
266
                end
267 141 creep
 
268
                // STA - Store Accumulator
269
                // PHA - Push A
270
                // TAX - Transfer Accumulator to X
271
                // TAY - Transfer Accumulator to Y
272
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
273
                        result = A;
274
                end
275
 
276
                // STX - Store X Register
277
                // TXA - Transfer X to Accumulator
278
                // TXS - Transfer X to Stack pointer
279
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
280
                        result = X;
281
                end
282
 
283
                // STY - Store Y Register
284
                // TYA - Transfer Y to Accumulator
285
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
286
                        result = Y;
287
                end
288
 
289
                // SEC - Set Carry Flag
290
                SEC_IMP: begin
291
                        STATUS[C] = 1'b1;
292
                end
293
 
294
                // SED - Set Decimal Flag
295
                SED_IMP: begin
296
                        STATUS[D] = 1'b1;
297
                end
298
 
299
                // SEI - Set Interrupt Disable
300
                SEI_IMP: begin
301
                        STATUS[I] = 1'b1;
302
                end
303
 
304
                // INC - Increment memory
305
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
306
                        result = alu_a + 1;
307
                end
308
 
309
                // INX - Increment X Register
310
                INX_IMP: begin
311
                        result = X + 1;
312
                end
313
 
314
                // INY - Increment Y Register
315
                INY_IMP : begin
316
                        result = Y + 1;
317
                end
318
 
319
                // DEC - Decrement memory
320
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
321
                        result = alu_a - 1;
322
                end
323
 
324
                // DEX - Decrement X register
325
                DEX_IMP: begin
326
                        result = X - 1;
327
                end
328
 
329
                // DEY - Decrement Y Register
330
                DEY_IMP: begin
331
                        result = Y - 1;
332
                end
333
 
334
                // ADC - Add with carry
335 162 gabrielosh
                // TODO: verify synthesis for % operand
336 141 creep
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
337
                        if (alu_status[D] == 1) begin
338 171 creep
                                //$display("MODO DECIMAL");
339 164 gabrielosh
                                AL = A[3:0] + alu_a[3:0] + alu_status[C];
340
                                AH = A[7:4] + alu_a[7:4];
341 171 creep
                                //$display("AL = %d", AL);
342
                                //$display("AH = %d", AH);
343 164 gabrielosh
                                if (AL > 9) begin
344
                                        bcdh = AH + (AL / 10);
345
                                        bcdl = AL % 10;
346 141 creep
                                end
347 171 creep
                                else begin
348
                                        bcdh = AH;
349
                                        bcdl = AL;
350
                                end
351
 
352
                                // ok
353
 
354
                                if (bcdh > 9) begin
355 161 gabrielosh
                                        STATUS[C] = 1;
356 164 gabrielosh
                                        bcdh2 = bcdh % 10;
357 161 gabrielosh
                                end
358 171 creep
                                else begin
359
                                        STATUS[C] = 0;
360
                                        bcdh2 = bcdh;
361
                                end
362
                                //$display("bcdh2 = %d", bcdh2);
363
                                //$display("bcdl = %d", bcdl);
364 164 gabrielosh
                                result = {bcdh2[3:0],bcdl[3:0]};
365 141 creep
                        end
366 165 gabrielosh
                        else begin
367 171 creep
                                //$display("MODO NORMAL");
368 161 gabrielosh
                                {STATUS[C],result} = op1 + op2 + alu_status[C];
369 165 gabrielosh
                        end
370 162 gabrielosh
 
371 152 gabrielosh
                        if ((op1[7] == op2[7]) && (op1[7] != result[7]))
372 141 creep
                                STATUS[V] = 1;
373
                        else
374
                                STATUS[V] = 0;
375
                end
376
 
377
                // AND - Logical AND
378
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
379
                        result = A & alu_a;
380
                end
381
 
382
                // CMP - Compare
383
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
384
                        result = A - alu_a;
385
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
386
                end
387
 
388
                // EOR - Exclusive OR
389
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
390 156 gabrielosh
                        result = A ^ alu_a;
391 158 gabrielosh
                        //$display("op1 ^ op2 = result");
392
                        //$display("%d  ^ %d  = %d", op1, op2, result);
393 141 creep
                end
394
 
395
                // LDA - Load Accumulator
396
                // LDX - Load X Register
397
                // LDY - Load Y Register
398
                // TSX - Transfer Stack Pointer to X
399
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
400
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
401
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
402
                TSX_IMP : begin
403
                        result = alu_a;
404
                end
405
 
406
                // ORA - Logical OR
407
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
408
                        result = A | alu_a;
409
                end
410
 
411
                // SBC - Subtract with Carry
412
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
413 174 gabrielosh
                        op2 = ~alu_a;
414
                        if (alu_status[D] == 1) begin
415 162 gabrielosh
 
416 174 gabrielosh
                                bcdl = op1[3:0] + op2[3:0] + alu_status[C];
417
                                bcdh = op1[7:4] + op2[7:4];
418 162 gabrielosh
                                if (bcdl > 9) begin
419
                                        bcdh = bcdh + bcdl[5:4];
420
                                        bcdl = bcdl % 10;
421
                                end
422
                                if (bcdh > 9) begin
423
                                        STATUS[C] = 1;
424
                                        bcdh = bcdh % 10;
425
                                end
426 163 gabrielosh
                                result = {bcdh[3:0],bcdl[3:0]};
427 162 gabrielosh
                        end
428 173 gabrielosh
                        else begin
429
                                {C_aux,result} = op1 + op2 + alu_status[C];
430 174 gabrielosh
                                STATUS[C] = ~result[7];
431 173 gabrielosh
                        end
432
 
433 162 gabrielosh
 
434 173 gabrielosh
                        if ((op1[7] == sign) && (op1[7] != result[7]))
435 162 gabrielosh
                                STATUS[V] = 1;
436
                        else
437
                                STATUS[V] = 0;
438
 
439 141 creep
                end
440
 
441
                // ASL - Arithmetic Shift Left
442
                ASL_ACC : begin
443 145 gabrielosh
                        //{STATUS[C],result} = A << 1;
444
                        {STATUS[C],result} = {A,1'b0};
445 141 creep
                end
446
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
447 145 gabrielosh
                        //{STATUS[C],result} = alu_a << 1;
448
                        {STATUS[C],result} = {alu_a,1'b0};
449 141 creep
                end
450
 
451
                // LSR - Logical Shift Right
452
                LSR_ACC: begin
453 145 gabrielosh
                        //{result, STATUS[C]} = A >> 1;
454
                        {result,STATUS[C]} = {1'b0,A};
455 141 creep
                end
456
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
457 145 gabrielosh
                        //{result, STATUS[C]} = alu_a >> 1;
458
                        {result,STATUS[C]} = {1'b0,alu_a};
459 141 creep
                end
460
 
461
                // ROL - Rotate Left
462
                ROL_ACC : begin
463 152 gabrielosh
                        {STATUS[C],result} = {A,alu_status[C]};
464 141 creep
                end
465
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
466
                        {STATUS[C],result} = {alu_a,alu_status[C]};
467
                end
468
 
469 152 gabrielosh
                // ROR - Rotate Right
470 141 creep
                ROR_ACC : begin
471
                        {result,STATUS[C]} = {alu_status[C],A};
472
                end
473
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
474
                        {result, STATUS[C]} = {alu_status[C], alu_a};
475
                end
476
 
477
                // CPX - Compare X Register
478
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
479
                        result = X - alu_a;
480
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
481
                end
482
 
483
                // CPY - Compare Y Register
484
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
485
                        result = Y - alu_a;
486
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
487
                end
488
 
489
                default: begin // NON-DEFAULT OPCODES FALL HERE
490 142 gabrielosh
                end
491 141 creep
        endcase
492 142 gabrielosh
        STATUS[Z] = (result == 0) ? 1 : 0;
493
        STATUS[N] = result[7];
494 141 creep
end
495
 
496
endmodule
497
 

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