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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 239

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1 141 creep
////////////////////////////////////////////////////////////////////////////
2 152 gabrielosh
////                                                                    ////
3
//// T6507LP IP Core                                                    ////
4
////                                                                    ////
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//// This file is part of the T6507LP project                           ////
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//// http://www.opencores.org/cores/t6507lp/                            ////
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////                                                                    ////
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//// Description                                                        ////
9
//// 6507 ALU                                                           ////
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////                                                                    ////
11
//// To Do:                                                             ////
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//// - Search for TODO                                                  ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
18 141 creep
////////////////////////////////////////////////////////////////////////////
19 152 gabrielosh
////                                                                    ////
20
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
21
////                                                                    ////
22
//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
24
//// removed from the file and that any derivative work contains        ////
25
//// the original copyright notice and the associated disclaimer.       ////
26
////                                                                    ////
27
//// This source file is free software; you can redistribute it         ////
28
//// and/or modify it under the terms of the GNU Lesser General         ////
29
//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
37
//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
40
//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
43 141 creep
////////////////////////////////////////////////////////////////////////////
44
 
45
`include "timescale.v"
46
 
47 238 creep
module t6507lp_alu(clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y);
48 141 creep
 
49 238 creep
`include "t6507lp_package.v"
50
 
51
localparam DATA_SIZE = 8;
52
localparam [3:0] BCD_HIGH_LIMIT = 4'd9;
53
localparam [3:0] BCD_FIX = 8'd6;
54
 
55 141 creep
input wire       clk;
56
input wire       reset_n;
57
input wire       alu_enable;
58 238 creep
input wire [DATA_SIZE - 1:0] alu_opcode;
59
input wire [DATA_SIZE - 1:0] alu_a;
60
output reg [DATA_SIZE - 1:0] alu_result;
61
output reg [DATA_SIZE - 1:0] alu_status;
62
output reg [DATA_SIZE - 1:0] alu_x;
63
output reg [DATA_SIZE - 1:0] alu_y;
64 141 creep
 
65 238 creep
reg [DATA_SIZE - 1:0] A;
66
reg [DATA_SIZE - 1:0] STATUS;
67
reg [DATA_SIZE + 1:0] result;
68
reg [DATA_SIZE - 1:0] op1;
69
reg [DATA_SIZE - 1:0] op2;
70
reg [DATA_SIZE - 1:0] bcdl;
71
reg [DATA_SIZE - 1:0] bcdh;
72
reg [DATA_SIZE - 1:0] bcdh2;
73
reg [DATA_SIZE - 1:0] AL;
74
reg [DATA_SIZE - 1:0] AH;
75 141 creep
 
76
always @ (posedge clk or negedge reset_n)
77
begin
78 238 creep
        if (reset_n == 1'b0) begin
79
                alu_result <= 10'd0;
80
                alu_status[C] <= 1'b0;
81
                alu_status[N] <= 1'b0;
82
                alu_status[V] <= 1'b0;
83
                alu_status[5] <= 1'b1;
84
                alu_status[Z] <= 1'b1;
85
                alu_status[I] <= 1'b0;
86
                alu_status[B] <= 1'b0;
87
                alu_status[D] <= 1'b0;
88
                A <= 8'd0;
89
                alu_x <= 8'd0;
90
                alu_y <= 8'd0;
91 141 creep
        end
92 238 creep
        else if ( alu_enable == 1'b1 ) begin
93 141 creep
                case (alu_opcode)
94 224 creep
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
95
                        ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
96
                        AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM,
97
                        EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
98
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS,
99
                        ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC,
100
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY,
101
                        SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
102
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP : begin
103 233 creep
                                A          <= result[7:0];
104
                                alu_result <= result[7:0];
105 141 creep
                                alu_status <= STATUS;
106
                        end
107 224 creep
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP,
108
                        TSX_IMP, INX_IMP, DEX_IMP : begin
109 233 creep
                                alu_x      <= result[7:0];
110 141 creep
                                alu_status <= STATUS;
111
                        end
112 224 creep
                        TXS_IMP : begin
113 233 creep
                                alu_x      <= result[7:0];
114 141 creep
                        end
115 224 creep
                        TXA_IMP, TYA_IMP : begin
116 233 creep
                                A          <= result[7:0];
117 184 gabrielosh
                                alu_status <= STATUS;
118
                        end
119 224 creep
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP,
120
                        INY_IMP, DEY_IMP : begin
121 233 creep
                                alu_y      <= result[7:0];
122 141 creep
                                alu_status <= STATUS;
123
                        end
124 224 creep
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY,
125
                        CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
126
                        CPY_ZPG, CPY_ABS : begin
127 141 creep
                                alu_status <= STATUS;
128
                        end
129 224 creep
                        PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY,
130
                        STA_IDX, STA_IDY : begin
131 233 creep
                                alu_result <= result[7:0];
132 158 gabrielosh
                        end
133 178 gabrielosh
                        STX_ZPG, STX_ZPY, STX_ABS : begin
134 233 creep
                                alu_x <= result[7:0];
135 178 gabrielosh
                        end
136
                        STY_ZPG, STY_ZPX, STY_ABS : begin
137 233 creep
                                alu_y <= result[7:0];
138 178 gabrielosh
                        end
139 224 creep
                        SEC_IMP : begin
140 238 creep
                                alu_status[C] <= 1'b1;
141 141 creep
                        end
142 224 creep
                        SED_IMP : begin
143 238 creep
                                alu_status[D] <= 1'b1;
144 141 creep
                        end
145 224 creep
                        SEI_IMP : begin
146 238 creep
                                alu_status[I] <= 1'b1;
147 141 creep
                        end
148 224 creep
                        CLC_IMP : begin
149 238 creep
                                alu_status[C] <= 1'b0;
150 141 creep
                        end
151 224 creep
                        CLD_IMP : begin
152 238 creep
                                alu_status[D] <= 1'b0;
153 141 creep
                        end
154 224 creep
                        CLI_IMP : begin
155 238 creep
                                alu_status[I] <= 1'b0;
156 141 creep
                        end
157 224 creep
                        CLV_IMP : begin
158 238 creep
                                alu_status[V] <= 1'b0;
159 141 creep
                        end
160 224 creep
                        BRK_IMP : begin
161 238 creep
                                alu_status[B] <= 1'b1;
162 141 creep
                        end
163 224 creep
                        PLP_IMP, RTI_IMP : begin
164 175 gabrielosh
                                alu_status[C] <= alu_a[C];
165
                                alu_status[Z] <= alu_a[Z];
166
                                alu_status[I] <= alu_a[I];
167
                                alu_status[D] <= alu_a[D];
168
                                alu_status[B] <= alu_a[B];
169
                                alu_status[V] <= alu_a[V];
170
                                alu_status[N] <= alu_a[N];
171 238 creep
                                alu_status[5] <= 1'b1;
172 141 creep
                        end
173 224 creep
                        BIT_ZPG, BIT_ABS : begin
174 141 creep
                                alu_status[Z] <= STATUS[Z];
175
                                alu_status[V] <= alu_a[6];
176
                                alu_status[N] <= alu_a[7];
177
                        end
178 224 creep
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX,
179
                        DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX,
180
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX,
181
                        ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
182 141 creep
                        begin
183 233 creep
                                alu_result <= result[7:0];
184 141 creep
                                alu_status <= STATUS;
185
                        end
186
                        default : begin
187 238 creep
                                alu_result <= 8'hFF;
188
                                alu_status <= 8'hFF;
189
                                A <= 8'hFF;
190
                                alu_x <= 8'hFF;
191
                                alu_y <= 8'hFF;
192 141 creep
                        end
193
                endcase
194
        end
195
end
196
 
197
always @ (*) begin
198 238 creep
        op1       = A;
199
        op2       = alu_a;
200
        result    = {2'd0, A[7:0]};
201
        result[9:8] = 2'b00;
202
        STATUS[N] = alu_status[N];
203
        STATUS[C] = alu_status[C];
204
        STATUS[V] = alu_status[V];
205
        STATUS[B] = alu_status[B];
206
        STATUS[I] = alu_status[I];
207
        STATUS[D] = alu_status[D];
208
        STATUS[Z] = alu_status[Z];
209
        STATUS[5] = 1'b1;
210
 
211
        bcdl = 8'd0;
212
        bcdh = 8'd0;
213
        bcdh2 = 8'd0;
214
        AL = 8'd0;
215
        AH = 8'd0;
216
 
217
        if (alu_enable == 1'b1) begin
218 224 creep
                case (alu_opcode)
219
                        // BIT - Bit Test
220
                        BIT_ZPG, BIT_ABS: begin
221 233 creep
                                result[7:0] = A & alu_a;
222 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
223 224 creep
                                STATUS[N] = result[7];
224 141 creep
                        end
225 224 creep
 
226
                        // PLA - Pull Accumulator
227
                        PLA_IMP : begin
228 233 creep
                                result[7:0] = alu_a;
229 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
230 224 creep
                                STATUS[N] = result[7];
231 165 gabrielosh
                        end
232 224 creep
 
233
                        // TAX - Transfer Accumulator to X
234
                        // TAY - Transfer Accumulator to Y
235
                        // PHA - Push Accumulator
236
                        // STA - Store Accumulator
237
                        TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
238
                        STA_ABY, STA_IDX, STA_IDY : begin
239 233 creep
                                result[7:0] = A;
240 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
241 224 creep
                                STATUS[N] = result[7];
242
                        end
243
 
244
                        // STX - Store X Register
245
                        // TXA - Transfer X to Accumulator
246
                        // TXS - Transfer X to Stack pointer
247
                        STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
248 233 creep
                                result[7:0] = alu_x;
249 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
250 224 creep
                                STATUS[N] = result[7];
251
                        end
252
 
253
                        // STY - Store Y Register
254
                        // TYA - Transfer Y to Accumulator
255
                        STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
256 233 creep
                                result[7:0] = alu_y;
257 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
258 224 creep
                                STATUS[N] = result[7];
259
                        end
260
 
261
                        // INC - Increment memory
262
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
263 238 creep
                                result[7:0] = alu_a + 8'd1;
264 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
265 224 creep
                                STATUS[N] = result[7];
266
                        end
267
 
268
                        // INX - Increment X Register
269
                        INX_IMP: begin
270 238 creep
                                result[7:0] = alu_x + 8'd1;
271 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
272 224 creep
                                STATUS[N] = result[7];
273
                        end
274
 
275
                        // INY - Increment Y Register
276
                        INY_IMP : begin
277 238 creep
                                result[7:0] = alu_y + 8'd1;
278 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
279 224 creep
                                STATUS[N] = result[7];
280
                        end
281
 
282
                        // DEC - Decrement memory
283
                        DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
284 238 creep
                                result[7:0] = alu_a - 8'd1;
285 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
286 224 creep
                                STATUS[N] = result[7];
287
                        end
288
 
289
                        // DEX - Decrement X register
290
                        DEX_IMP: begin
291 238 creep
                                result[7:0] = alu_x - 8'd1;
292 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
293 224 creep
                                STATUS[N] = result[7];
294
                        end
295
 
296
                        // DEY - Decrement Y Register
297
                        DEY_IMP: begin
298 238 creep
                                result[7:0] = alu_y - 8'd1;
299 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
300 224 creep
                                STATUS[N] = result[7];
301
                        end
302
 
303
                        // ADC - Add with carry
304
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
305
                        ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
306
                                if (!alu_status[D]) begin
307 238 creep
                                        result = op1 + op2 + {7'd0, alu_status[C]}; // this looks so ugly but the operands are all 8 bits now
308 224 creep
                                        STATUS[N] = result[7];
309 239 gabrielosh
                                        STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
310 238 creep
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1'b1 : 1'b0;
311 233 creep
                                        STATUS[C] = result[8];
312 179 gabrielosh
                                end
313
                                else begin
314 238 creep
                                        AL = op1[3:0] + op2[3:0] + {7'd0, alu_status[C]};
315 224 creep
                                        AH = op1[7:4] + op2[7:4];
316 238 creep
                                        STATUS[Z] = (AL == 0 && AH == 0) ? 1'b1 : 1'b0;
317
                                        if (AL > {4'd0,BCD_HIGH_LIMIT}) begin
318
                                                bcdl = AL + {4'd0, BCD_FIX};
319
                                                bcdh = AH + 8'd1;
320 224 creep
                                        end
321
                                        else begin
322
                                                bcdl = AL;
323
                                                bcdh = AH;
324
                                        end
325
                                        STATUS[N] = bcdh[3];
326 238 creep
                                        STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1'b1 : 1'b0;
327
                                        if (bcdh > {4'd0, BCD_HIGH_LIMIT}) begin
328
                                                bcdh2 = bcdh + {4'd0, BCD_FIX};
329 224 creep
                                        end
330
                                        else begin
331
                                                bcdh2 = bcdh;
332
                                        end
333
                                        STATUS[C] = bcdh2[4] || bcdh2[5];
334 238 creep
                                        result[7:0] = {bcdh2[3:0], bcdl[3:0]};
335 179 gabrielosh
                                end
336
                        end
337 224 creep
 
338
                        // AND - Logical AND
339
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
340
                        AND_IDY : begin
341 233 creep
                                result[7:0] = A & alu_a;
342 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
343 224 creep
                                STATUS[N] = result[7];
344 179 gabrielosh
                        end
345 224 creep
 
346
                        // CMP - Compare
347
                        CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
348
                        CMP_IDY : begin
349 233 creep
                                result[7:0] = A - alu_a;
350 238 creep
                                STATUS[C] = (A >= alu_a) ? 1'b1 : 1'b0;
351 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
352 224 creep
                                STATUS[N] = result[7];
353 162 gabrielosh
                        end
354 224 creep
 
355
                        // EOR - Exclusive OR
356
                        EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
357
                        EOR_IDX, EOR_IDY : begin
358 233 creep
                                result[7:0] = A ^ alu_a;
359 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
360 224 creep
                                STATUS[N] = result[7];
361
                        end
362
 
363
                        // LDA - Load Accumulator
364
                        // LDX - Load X Register
365
                        // LDY - Load Y Register
366
                        // TSX - Transfer Stack Pointer to X
367
                        LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
368
                        LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
369
                        LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
370 233 creep
                                result[7:0] = alu_a;
371 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
372 224 creep
                                STATUS[N] = result[7];
373
                        end
374
 
375
                        // ORA - Logical OR
376
                        ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
377
                        ORA_IDY : begin
378 233 creep
                                result[7:0] = A | alu_a;
379 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
380 224 creep
                                STATUS[N] = result[7];
381
                        end
382
 
383
                        // SBC - Subtract with Carry
384
                        SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
385
                        SBC_IDY : begin
386 238 creep
                                result = op1 - op2 - (1'b1 - alu_status[C]);
387 224 creep
                                STATUS[N] = result[7];
388 238 creep
                                STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1'b1 : 1'b0;
389 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
390 233 creep
                                STATUS[C] = ~(result[8] || result[9]);
391 224 creep
                                if (alu_status[D]) begin
392 238 creep
                                        AL = op1[3:0] - op2[3:0] - (1'b1 - alu_status[C]);
393 224 creep
                                        AH = op1[7:4] - op2[7:4];
394
                                        if (AL[4]) begin
395 238 creep
                                                bcdl = AL - {4'd0, BCD_FIX};
396
                                                bcdh = AH - 8'd1;
397 224 creep
                                        end
398
                                        else begin
399
                                                bcdl = AL;
400
                                                bcdh = AH;
401
                                        end
402
                                        if (bcdh[4]) begin
403 238 creep
                                                bcdh2 = bcdh - {4'd0, BCD_FIX};
404 224 creep
                                        end
405
                                        else begin
406
                                                bcdh2 = bcdh;
407
                                        end
408 233 creep
                                        result[7:0] = {bcdh2[3:0],bcdl[3:0]};
409 224 creep
                                end
410 173 gabrielosh
                        end
411 224 creep
 
412
                        // ASL - Arithmetic Shift Left
413
                        ASL_ACC : begin
414 238 creep
                                {STATUS[C],result[7:0]} = {A, 1'b0};
415 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
416 224 creep
                                STATUS[N] = result[7];
417
                        end
418
                        ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
419 238 creep
                                {STATUS[C],result[7:0]} = {alu_a, 1'b0};
420 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
421 224 creep
                                STATUS[N] = result[7];
422
                        end
423
 
424
                        // LSR - Logical Shift Right
425
                        LSR_ACC: begin
426 233 creep
                                {result[7:0],STATUS[C]} = {1'b0,A};
427 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
428 224 creep
                                STATUS[N] = result[7];
429
                        end
430
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
431 233 creep
                                {result[7:0],STATUS[C]} = {1'b0,alu_a};
432 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
433 224 creep
                                STATUS[N] = result[7];
434
                        end
435
 
436
                        // ROL - Rotate Left
437
                        ROL_ACC : begin
438 233 creep
                                {STATUS[C],result[7:0]} = {A,alu_status[C]};
439 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
440 224 creep
                                STATUS[N] = result[7];
441
                        end
442
                        ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
443 233 creep
                                {STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
444 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
445 224 creep
                                STATUS[N] = result[7];
446
                        end
447
 
448
                        // ROR - Rotate Right
449
                        ROR_ACC : begin
450 233 creep
                                {result[7:0],STATUS[C]} = {alu_status[C],A};
451 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
452 224 creep
                                STATUS[N] = result[7];
453
                        end
454
                        ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
455 233 creep
                                {result[7:0], STATUS[C]} = {alu_status[C], alu_a};
456 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
457 224 creep
                                STATUS[N] = result[7];
458
                        end
459
 
460
                        // CPX - Compare X Register
461
                        CPX_IMM, CPX_ZPG, CPX_ABS : begin
462 233 creep
                                result[7:0] = alu_x - alu_a;
463 238 creep
                                STATUS[C] = (alu_x >= alu_a) ? 1'b1 : 1'b0;
464 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
465 224 creep
                                STATUS[N] = result[7];
466
                        end
467
 
468
                        // CPY - Compare Y Register
469
                        CPY_IMM, CPY_ZPG, CPY_ABS : begin
470 233 creep
                                result[7:0] = alu_y - alu_a;
471 238 creep
                                STATUS[C] = (alu_y >= alu_a) ? 1'b1 : 1'b0;
472 239 gabrielosh
                                STATUS[Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
473 224 creep
                                STATUS[N] = result[7];
474
                        end
475
 
476
                        default: begin
477 238 creep
                                result = 10'h3FF;
478
                                STATUS = 8'hFF;
479 224 creep
                        end
480
                endcase
481
        end
482 141 creep
end
483
endmodule

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