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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 FSM                                                           ////
////                                                                    ////
//// TODO:                                                              ////
//// - Fix absolute indexed mode                                        ////
//// - Code the relative mode                                           ////
//// - Code the indexed indirect mode                                   ////
//// - Code the indirect indexed mode                                   ////
//// - Code the absolute indirect mode                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
        parameter DATA_SIZE = 8;
        parameter ADDR_SIZE = 13;
 
        localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        input reset_n;
        input [DATA_SIZE_:0] alu_result;
        input [DATA_SIZE_:0] alu_status;
        input [DATA_SIZE_:0] data_in;
        output reg [ADDR_SIZE_:0] address;
        output reg control; // one bit is enough? read = 0, write = 1
        output reg [DATA_SIZE_:0] data_out;
        output reg [DATA_SIZE_:0] alu_opcode;
        output reg [DATA_SIZE_:0] alu_a;
        output reg alu_enable;
 
        input [DATA_SIZE_:0] alu_x;
        input [DATA_SIZE_:0] alu_y;
 
        // FSM states
        localparam FETCH_OP = 4'b0000;
        localparam FETCH_OP_CALC = 4'b0001;
        localparam FETCH_LOW = 4'b0010;
        localparam FETCH_HIGH = 4'b0011;
        localparam READ_MEM = 4'b0100;
        localparam DUMMY_WRT_CALC = 4'b0101;
        localparam WRITE_MEM = 4'b0110;
        localparam FETCH_OP_CALC_PARAM = 4'b0111;
        localparam READ_MEM_CALC_INDEX = 4'b1000;
        localparam FETCH_HIGH_CALC_INDEX = 4'b1001;
        localparam READ_MEM_FIX_ADDR = 4'b1010;
        localparam RESET = 4'b1111;
 
        // OPCODES TODO: verify how this get synthesised
        `include "../T6507LP_Package.v"
 
        // control signals
        localparam MEM_READ = 1'b0;
        localparam MEM_WRITE = 1'b1;
 
        reg [ADDR_SIZE_:0] pc;           // program counter
        reg [DATA_SIZE_:0] sp;           // stack pointer
        reg [DATA_SIZE_:0] ir;           // instruction register
        reg [ADDR_SIZE_:0] temp_addr;    // temporary address
        reg [DATA_SIZE_:0] temp_data;    // temporary data
 
        reg [3:0] state, next_state; // current and next state registers
        // TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
        // wiring that simplifies the FSM logic
        reg absolute;
        reg absolute_indexed;
        reg accumulator;
        reg immediate;
        reg implied;
        reg indirect;
        reg relative;
        reg zero_page;
        reg zero_page_indexed;
        reg [DATA_SIZE_:0] index; // will be assigned with either X or Y
 
        // regs that store the type of operation. again, this simplifies the FSM a lot.
        reg read;
        reg read_modify_write;
        reg write;
        reg jump;
 
        wire [ADDR_SIZE_:0] next_pc;
        assign next_pc = pc + 13'b0000000000001;
 
        reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.
        reg page_crossed;                       // so the simple assign was changed into a combinational always block
 
        always @(*) begin
                address_plus_index = 0;
                page_crossed = 0;
 
                if (state == READ_MEM_CALC_INDEX || state == READ_MEM_FIX_ADDR || state == FETCH_HIGH_CALC_INDEX) begin
                        {page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
                        address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
 
                end
        end
 
        always @ (posedge clk or negedge reset_n) begin // sequencial always block
                if (reset_n == 1'b0) begin
                        // all registers must assume default values
                        pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
                        sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
                        ir <= 8'h00;
                        temp_addr <= 0;
                        temp_data <= 8'h00;
                        state <= RESET;
                        // registered outputs also receive default values
                        address <= 0;
                        control <= MEM_READ;
                        data_out <= 8'h00;
                end
                else begin
                        state <= next_state;
 
                        case (state)
                                RESET: begin
                                        // The processor was reset
                                        $write("under reset");
                                end
                                FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
                                                // the last cycle was a memory write.
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
                                        pc <= next_pc;
                                        address <= next_pc;
                                        control <= MEM_READ;
                                        ir <= data_in;
                                end
                                FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
                                        if (accumulator || implied) begin
                                                pc <= pc; // is this better?
                                                address <= pc;
                                                control <= MEM_READ;
                                        end
                                        else if (immediate) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_data <= data_in; // the follow-up byte is saved in temp_data 
                                        end
                                        else if (absolute || absolute_indexed) begin
                                                pc <= next_pc;
                                                address <= next_pc;
                                                control <= MEM_READ;
                                                temp_addr <= {{5{1'b0}},data_in};
                                        end
                                        else if (zero_page) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        else if (zero_page_indexed) begin
                                                pc <= next_pc;
                                                address <= {{5{1'b0}},data_in};
                                                temp_addr <= {{5{1'b0}},data_in};
                                                control <= MEM_READ;
                                        end
                                end
                                FETCH_HIGH_CALC_INDEX: begin
                                        pc <= next_pc;
                                        temp_addr[12:8] <= data_in[4:0];
                                        address <= {data_in[4:0], address_plus_index[7:0]};
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                FETCH_HIGH: begin
                                        if (jump) begin
                                                pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
                                                address <= {data_in[4:0], temp_addr[7:0]};
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                        else begin
                                                if (write) begin
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin // read_modify_write or just read
                                                        pc <= next_pc;
                                                        temp_addr[12:8] <= data_in[4:0];
                                                        address <= {data_in[4:0],temp_addr[7:0]};
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
                                        end
                                        //else begin
                                        //      $write("FETCHHIGH PROBLEM"); 
                                        //      $finish(0); 
                                        //end
                                end
                                READ_MEM: begin
                                        if (read_modify_write) begin
                                                pc <= pc;
                                                address <= temp_addr;
                                                control <= MEM_WRITE;
                                                temp_data <= data_in;
                                                data_out <= data_in; // writeback the same value
                                        end
                                        else begin
                                                pc <= pc;
                                                address <= pc;
                                                temp_data <= data_in;
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                        end
                                end
                                READ_MEM_CALC_INDEX: begin
                                                //pc <= next_pc; // pc was  already updated in the previous cycle
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                                if (write) begin
                                                        control <= MEM_WRITE;
                                                        data_out <= alu_result;
                                                end
                                                else begin
                                                        control <= MEM_READ;
                                                        data_out <= 8'h00;
                                                end
 
                                end
                                READ_MEM_FIX_ADDR: begin
                                        if (read) begin
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
 
                                                if (page_crossed) begin
                                                        address <= address_plus_index;
                                                        temp_addr <= address_plus_index;
                                                end
                                                else begin
                                                        address <= pc;
                                                        temp_data <= data_in;
                                                end
                                        end
                                        else if (write) begin
                                                control <= MEM_WRITE;
                                                data_out <= alu_result;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
 
                                        end
                                        else begin // read modify write
                                                control <= MEM_READ;
                                                data_out <= 8'h00;
                                                address <= address_plus_index;
                                                temp_addr <= address_plus_index;
                                        end
                                end
                                DUMMY_WRT_CALC: begin
                                        pc <= pc;
                                        address <= temp_addr;
                                        control <= MEM_WRITE;
                                        data_out <= alu_result;
                                end
                                WRITE_MEM: begin
                                        pc <= pc;
                                        address <= pc;
                                        control <= MEM_READ;
                                        data_out <= 8'h00;
                                end
                                default: begin
                                        $write("unknown state");        // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef 
                                        $finish(0);
                                end
 
                        endcase
                end
        end
 
        always @ (*) begin // this is the next_state logic and the output logic always block
                alu_opcode = 8'h00;
                alu_a = 8'h00;
                alu_enable = 1'b0;
 
                next_state = RESET; // this prevents the latch
 
                case (state)
                        RESET: begin
                                next_state = FETCH_OP;
                        end
                        FETCH_OP: begin
                                next_state = FETCH_LOW;
                        end
                        //FETCH_OP_CALC: begin // so far no addressing mode required the use of this state
                        //      next_state = FETCH_LOW;
                        //      alu_opcode = ir;
                        //      alu_enable = 1'b1;
                        //end
                        FETCH_OP_CALC_PARAM: begin
                                next_state = FETCH_LOW;
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = temp_data;
                        end
                        FETCH_LOW: begin
                                if (accumulator  || implied) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = FETCH_OP;
                                end
                                else if (immediate) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (zero_page) begin
                                        if (read || read_modify_write) begin
                                                next_state = READ_MEM;
                                        end
                                        else if (write) begin
                                                next_state = WRITE_MEM;
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                        else begin
                                                $write("unknown behavior");
                                                $finish(0);
                                        end
                                end
                                else if (zero_page_indexed) begin
                                        next_state = READ_MEM_CALC_INDEX;
                                end
                                else if (absolute) begin // at least the absolute address mode falls here
                                        next_state = FETCH_HIGH;
                                        if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
                                                alu_opcode = ir;
                                                alu_enable = 1'b1;
                                                alu_a = 8'h00;
                                        end
                                end
                                else if (absolute_indexed) begin
                                        next_state = FETCH_HIGH_CALC_INDEX;
                                end
                        end
                        FETCH_HIGH_CALC_INDEX: begin
                                next_state = READ_MEM_FIX_ADDR;
                        end
                        READ_MEM_FIX_ADDR: begin
                                if (read) begin
                                        if (page_crossed) begin
                                                next_state = READ_MEM;
                                        end
                                        else begin
                                                next_state = FETCH_OP_CALC_PARAM;
                                        end
                                end
                                else if (read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        FETCH_HIGH: begin
                                if (jump) begin
                                        next_state = FETCH_OP;
                                end
                                else if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM_CALC_INDEX: begin
                                if (read || read_modify_write) begin
                                        next_state = READ_MEM;
                                end
                                else if (write) begin
                                        alu_opcode = ir;
                                        alu_enable = 1'b1;
                                        next_state = WRITE_MEM;
                                end
                                else begin
                                        $write("unknown behavior");
                                        $finish(0);
                                end
                        end
                        READ_MEM: begin
                                if (read) begin
                                        next_state = FETCH_OP_CALC_PARAM;
                                end
                                else if (read_modify_write) begin
                                        next_state = DUMMY_WRT_CALC;
                                end
                        end
                        DUMMY_WRT_CALC: begin
                                alu_opcode = ir;
                                alu_enable = 1'b1;
                                alu_a = data_in;
                                next_state = WRITE_MEM;
                        end
                        WRITE_MEM: begin
                                next_state = FETCH_OP;
                        end
                        default: begin
                                next_state = RESET;
                        end
                endcase
        end
 
        // this always block is responsible for updating the address mode and the type of operation being done
        always @ (*) begin // 
                absolute = 1'b0;
                absolute_indexed = 1'b0;
                accumulator = 1'b0;
                immediate = 1'b0;
                implied = 1'b0;
                indirect = 1'b0;
                relative = 1'b0;
                zero_page = 1'b0;
                zero_page_indexed = 1'b0;
 
                index = 1'b0;
 
                read = 1'b0;
                read_modify_write = 1'b0;
                write = 1'b0;
                jump = 1'b0;
 
                case (ir)
                        BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
                        PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
                                implied = 1'b1;
                        end
                        ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
                                accumulator = 1'b1;
                        end
                        ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
                                immediate = 1'b1;
                        end
                        ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
                        LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
                                zero_page = 1'b1;
                        end
                        ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
                        SBC_ZPX, STA_ZPX, STY_ZPX: begin
                                zero_page_indexed = 1'b1;
                                index = alu_x;
                        end
                        LDX_ZPY, STX_ZPY: begin
                                zero_page_indexed = 1'b1;
                                index = alu_y;
                        end
                        BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
                                relative = 1'b1;
                        end
                        ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
                        LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
                                absolute = 1'b1;
                        end
                        ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
                        SBC_ABX, STA_ABX: begin
                                absolute_indexed = 1'b1;
                                index = alu_x;
                        end
                        ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
                                absolute_indexed = 1'b1;
                                index = alu_y;
                        end
                        ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
                        ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
                                indirect = 1'b1;
                        end
                        default: begin
                                if (reset_n == 1) begin // the processor is NOT being reset
                                        $write("\nunknown OPCODE!!!!! 0x%h\n", ir);
                                        $finish();
                                end
                        end
                endcase
 
                case (ir)
                        ASL_ACC, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ACC, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ACC, ROL_ZPG, ROL_ZPX, ROL_ABS,
                        ROL_ABX, ROR_ACC, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS,
                        DEC_ABX: begin
                                read_modify_write = 1'b1;
                        end
                        STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY, STX_ZPG, STX_ZPY, STX_ABS, STY_ZPG, STY_ZPX, STY_ABS: begin
                                write = 1'b1;
                        end
                        default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
                                read = 1'b1;
                        end
                endcase
 
                if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
                        jump = 1'b1;
                end
        end
endmodule
 
 
 

Line No.	Rev	Author	Line
1	61	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 FSM ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Fix absolute indexed mode ////`
13			`//// - Code the relative mode ////`
14			`//// - Code the indexed indirect mode ////`
15			`//// - Code the indirect indexed mode ////`
16			`//// - Code the absolute indirect mode ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
20			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
21			`//// ////`
22			`////////////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`////////////////////////////////////////////////////////////////////////////`
48
49			`timescale 1ns / 1ps
50
51	86	creep	`module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`
52	87	creep	`parameter DATA_SIZE = 8;`
53			`parameter ADDR_SIZE = 13;`
54	68	creep
55	83	creep	`localparam DATA_SIZE_ = DATA_SIZE - 4'b0001;`
56			`localparam ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
57	82	creep
58	71	creep	`input clk;`
59			`input reset_n;`
60	82	creep	`input [DATA_SIZE_:0] alu_result;`
61			`input [DATA_SIZE_:0] alu_status;`
62			`input [DATA_SIZE_:0] data_in;`
63			`output reg [ADDR_SIZE_:0] address;`
64	61	creep	`output reg control; // one bit is enough? read = 0, write = 1`
65	82	creep	`output reg [DATA_SIZE_:0] data_out;`
66			`output reg [DATA_SIZE_:0] alu_opcode;`
67			`output reg [DATA_SIZE_:0] alu_a;`
68	68	creep	`output reg alu_enable;`
69	61	creep
70	86	creep	`input [DATA_SIZE_:0] alu_x;`
71			`input [DATA_SIZE_:0] alu_y;`
72	68	creep
73	61	creep	`// FSM states`
74	63	creep	`localparam FETCH_OP = 4'b0000;`
75	68	creep	`localparam FETCH_OP_CALC = 4'b0001;`
76			`localparam FETCH_LOW = 4'b0010;`
77			`localparam FETCH_HIGH = 4'b0011;`
78	71	creep	`localparam READ_MEM = 4'b0100;`
79			`localparam DUMMY_WRT_CALC = 4'b0101;`
80			`localparam WRITE_MEM = 4'b0110;`
81			`localparam FETCH_OP_CALC_PARAM = 4'b0111;`
82	86	creep	`localparam READ_MEM_CALC_INDEX = 4'b1000;`
83	87	creep	`localparam FETCH_HIGH_CALC_INDEX = 4'b1001;`
84			`localparam READ_MEM_FIX_ADDR = 4'b1010;`
85			`localparam RESET = 4'b1111;`
86	61	creep
87			`// OPCODES TODO: verify how this get synthesised`
88			`include "../T6507LP_Package.v"
89
90			`// control signals`
91			`localparam MEM_READ = 1'b0;`
92			`localparam MEM_WRITE = 1'b1;`
93
94	82	creep	`reg [ADDR_SIZE_:0] pc; // program counter`
95			`reg [DATA_SIZE_:0] sp; // stack pointer`
96			`reg [DATA_SIZE_:0] ir; // instruction register`
97			`reg [ADDR_SIZE_:0] temp_addr; // temporary address`
98			`reg [DATA_SIZE_:0] temp_data; // temporary data`
99	61	creep
100			`reg [3:0] state, next_state; // current and next state registers`
101			`// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.`
102
103			`// wiring that simplifies the FSM logic`
104			`reg absolute;`
105			`reg absolute_indexed;`
106			`reg accumulator;`
107			`reg immediate;`
108			`reg implied;`
109			`reg indirect;`
110			`reg relative;`
111			`reg zero_page;`
112			`reg zero_page_indexed;`
113	86	creep	`reg [DATA_SIZE_:0] index; // will be assigned with either X or Y`
114	61	creep
115			`// regs that store the type of operation. again, this simplifies the FSM a lot.`
116			`reg read;`
117			`reg read_modify_write;`
118			`reg write;`
119			`reg jump;`
120
121	82	creep	`wire [ADDR_SIZE_:0] next_pc;`
122	63	creep	`assign next_pc = pc + 13'b0000000000001;`
123	61	creep
124	87	creep	`reg [ADDR_SIZE_:0] address_plus_index; // this would update more times than actually needed, consuming power.`
125			`reg page_crossed; // so the simple assign was changed into a combinational always block`
126
127			`always @(*) begin`
128			`address_plus_index = 0;`
129			`page_crossed = 0;`
130	86	creep
131	88	creep	`if (state == READ_MEM_CALC_INDEX \|\| state == READ_MEM_FIX_ADDR \|\| state == FETCH_HIGH_CALC_INDEX) begin`
132			`{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;`
133			`address_plus_index[12:8] = temp_addr[12:8] + page_crossed;`
134
135	87	creep	`end`
136			`end`
137
138	71	creep	`always @ (posedge clk or negedge reset_n) begin // sequencial always block`
139			`if (reset_n == 1'b0) begin`
140			`// all registers must assume default values`
141	68	creep	`pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.`
142			`sp <= 0; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.`
143	82	creep	`ir <= 8'h00;`
144	71	creep	`temp_addr <= 0;`
145	82	creep	`temp_data <= 8'h00;`
146	68	creep	`state <= RESET;`
147	71	creep	`// registered outputs also receive default values`
148			`address <= 0;`
149	82	creep	`control <= MEM_READ;`
150			`data_out <= 8'h00;`
151	61	creep	`end`
152			`else begin`
153			`state <= next_state;`
154	83	creep
155	61	creep	`case (state)`
156	68	creep	`RESET: begin`
157	82	creep	`// The processor was reset`
158			`$write("under reset");`
159	68	creep	`end`
160	61	creep	`FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or`
161			`// the last cycle was a memory write.`
162			`pc <= next_pc;`
163	71	creep	`address <= next_pc;`
164	83	creep	`control <= MEM_READ;`
165	70	creep	`ir <= data_in;`
166	61	creep	`end`
167	71	creep	`FETCH_OP_CALC, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!`
168	61	creep	`pc <= next_pc;`
169	71	creep	`address <= next_pc;`
170	83	creep	`control <= MEM_READ;`
171	70	creep	`ir <= data_in;`
172	61	creep	`end`
173	68	creep	`FETCH_LOW: begin // in this state the opcode is already known so truly execution begins`
174			`if (accumulator \|\| implied) begin`
175	70	creep	`pc <= pc; // is this better?`
176	71	creep	`address <= pc;`
177	83	creep	`control <= MEM_READ;`
178	61	creep	`end`
179	70	creep	`else if (immediate) begin`
180	68	creep	`pc <= next_pc;`
181	71	creep	`address <= next_pc;`
182	83	creep	`control <= MEM_READ;`
183	70	creep	`temp_data <= data_in; // the follow-up byte is saved in temp_data`
184	61	creep	`end`
185	87	creep	`else if (absolute \|\| absolute_indexed) begin`
186	71	creep	`pc <= next_pc;`
187			`address <= next_pc;`
188	83	creep	`control <= MEM_READ;`
189	87	creep	`temp_addr <= {{5{1'b0}},data_in};`
190	71	creep	`end`
191	77	creep	`else if (zero_page) begin`
192			`pc <= next_pc;`
193			`address <= {{5{1'b0}},data_in};`
194	78	creep	`temp_addr <= {{5{1'b0}},data_in};`
195
196	77	creep	`if (write) begin`
197			`control <= MEM_WRITE;`
198	78	creep	`data_out <= alu_result;`
199	77	creep	`end`
200	83	creep	`else begin`
201			`control <= MEM_READ;`
202			`data_out <= 8'h00;`
203			`end`
204	77	creep	`end`
205	86	creep	`else if (zero_page_indexed) begin`
206			`pc <= next_pc;`
207			`address <= {{5{1'b0}},data_in};`
208			`temp_addr <= {{5{1'b0}},data_in};`
209			`control <= MEM_READ;`
210			`end`
211	61	creep	`end`
212	87	creep	`FETCH_HIGH_CALC_INDEX: begin`
213			`pc <= next_pc;`
214			`temp_addr[12:8] <= data_in[4:0];`
215			`address <= {data_in[4:0], address_plus_index[7:0]};`
216			`control <= MEM_READ;`
217			`data_out <= 8'h00;`
218			`end`
219	71	creep	`FETCH_HIGH: begin`
220			`if (jump) begin`
221	83	creep	`pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte`
222			`address <= {data_in[4:0], temp_addr[7:0]};`
223			`control <= MEM_READ;`
224			`data_out <= 8'h00;`
225	71	creep	`end`
226			`else begin`
227			`if (write) begin`
228			`pc <= next_pc;`
229			`temp_addr[12:8] <= data_in[4:0];`
230			`address <= {data_in[4:0],temp_addr[7:0]};`
231			`control <= MEM_WRITE;`
232	77	creep	`data_out <= alu_result;`
233	71	creep	`end`
234			`else begin // read_modify_write or just read`
235			`pc <= next_pc;`
236			`temp_addr[12:8] <= data_in[4:0];`
237			`address <= {data_in[4:0],temp_addr[7:0]};`
238	83	creep	`control <= MEM_READ;`
239			`data_out <= 8'h00;`
240	71	creep	`end`
241			`end`
242			`//else begin`
243			`// $write("FETCHHIGH PROBLEM");`
244			`// $finish(0);`
245			`//end`
246	61	creep	`end`
247	71	creep	`READ_MEM: begin`
248			`if (read_modify_write) begin`
249			`pc <= pc;`
250			`address <= temp_addr;`
251			`control <= MEM_WRITE;`
252			`temp_data <= data_in;`
253			`data_out <= data_in; // writeback the same value`
254			`end`
255			`else begin`
256			`pc <= pc;`
257			`address <= pc;`
258			`temp_data <= data_in;`
259	83	creep	`control <= MEM_READ;`
260			`data_out <= 8'h00;`
261	71	creep	`end`
262	70	creep	`end`
263	86	creep	`READ_MEM_CALC_INDEX: begin`
264			`//pc <= next_pc; // pc was already updated in the previous cycle`
265			`address <= address_plus_index;`
266			`temp_addr <= address_plus_index;`
267
268			`if (write) begin`
269			`control <= MEM_WRITE;`
270			`data_out <= alu_result;`
271			`end`
272			`else begin`
273			`control <= MEM_READ;`
274			`data_out <= 8'h00;`
275			`end`
276
277			`end`
278	87	creep	`READ_MEM_FIX_ADDR: begin`
279			`if (read) begin`
280			`control <= MEM_READ;`
281			`data_out <= 8'h00;`
282
283			`if (page_crossed) begin`
284			`address <= address_plus_index;`
285			`temp_addr <= address_plus_index;`
286			`end`
287			`else begin`
288			`address <= pc;`
289			`temp_data <= data_in;`
290			`end`
291			`end`
292			`else if (write) begin`
293			`control <= MEM_WRITE;`
294			`data_out <= alu_result;`
295			`address <= address_plus_index;`
296			`temp_addr <= address_plus_index;`
297
298			`end`
299			`else begin // read modify write`
300			`control <= MEM_READ;`
301			`data_out <= 8'h00;`
302			`address <= address_plus_index;`
303			`temp_addr <= address_plus_index;`
304			`end`
305			`end`
306	71	creep	`DUMMY_WRT_CALC: begin`
307			`pc <= pc;`
308			`address <= temp_addr;`
309			`control <= MEM_WRITE;`
310			`data_out <= alu_result;`
311	70	creep	`end`
312	71	creep	`WRITE_MEM: begin`
313			`pc <= pc;`
314			`address <= pc;`
315	83	creep	`control <= MEM_READ;`
316			`data_out <= 8'h00;`
317	70	creep	`end`
318			`default: begin`
319			$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
320			`$finish(0);`
321			`end`
322
323			`endcase`
324			`end`
325			`end`
326
327	71	creep	`always @ (*) begin // this is the next_state logic and the output logic always block`
328			`alu_opcode = 8'h00;`
329			`alu_a = 8'h00;`
330			`alu_enable = 1'b0;`
331	70	creep
332	71	creep	`next_state = RESET; // this prevents the latch`
333	68	creep
334	71	creep	`case (state)`
335			`RESET: begin`
336			`next_state = FETCH_OP;`
337			`end`
338			`FETCH_OP: begin`
339			`next_state = FETCH_LOW;`
340			`end`
341	82	creep	`//FETCH_OP_CALC: begin // so far no addressing mode required the use of this state`
342			`// next_state = FETCH_LOW;`
343			`// alu_opcode = ir;`
344			`// alu_enable = 1'b1;`
345			`//end`
346	71	creep	`FETCH_OP_CALC_PARAM: begin`
347			`next_state = FETCH_LOW;`
348			`alu_opcode = ir;`
349			`alu_enable = 1'b1;`
350			`alu_a = temp_data;`
351			`end`
352			`FETCH_LOW: begin`
353			`if (accumulator \|\| implied) begin`
354			`alu_opcode = ir;`
355			`alu_enable = 1'b1;`
356			`next_state = FETCH_OP;`
357			`end`
358			`else if (immediate) begin`
359			`next_state = FETCH_OP_CALC_PARAM;`
360			`end`
361	77	creep	`else if (zero_page) begin`
362			`if (read \|\| read_modify_write) begin`
363			`next_state = READ_MEM;`
364			`end`
365			`else if (write) begin`
366			`next_state = WRITE_MEM;`
367	86	creep	`alu_opcode = ir;`
368			`alu_enable = 1'b1;`
369			`alu_a = 8'h00;`
370	77	creep	`end`
371			`else begin`
372			`$write("unknown behavior");`
373			`$finish(0);`
374			`end`
375			`end`
376	86	creep	`else if (zero_page_indexed) begin`
377			`next_state = READ_MEM_CALC_INDEX;`
378			`end`
379	87	creep	`else if (absolute) begin // at least the absolute address mode falls here`
380	71	creep	`next_state = FETCH_HIGH;`
381	87	creep	`if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly`
382	86	creep	`alu_opcode = ir;`
383			`alu_enable = 1'b1;`
384			`alu_a = 8'h00;`
385			`end`
386	71	creep	`end`
387	87	creep	`else if (absolute_indexed) begin`
388			`next_state = FETCH_HIGH_CALC_INDEX;`
389			`end`
390	71	creep	`end`
391	87	creep	`FETCH_HIGH_CALC_INDEX: begin`
392			`next_state = READ_MEM_FIX_ADDR;`
393			`end`
394			`READ_MEM_FIX_ADDR: begin`
395			`if (read) begin`
396			`if (page_crossed) begin`
397			`next_state = READ_MEM;`
398			`end`
399			`else begin`
400			`next_state = FETCH_OP_CALC_PARAM;`
401			`end`
402			`end`
403			`else if (read_modify_write) begin`
404			`next_state = READ_MEM;`
405			`end`
406			`else if (write) begin`
407			`next_state = WRITE_MEM;`
408			`end`
409			`else begin`
410			`$write("unknown behavior");`
411			`$finish(0);`
412			`end`
413			`end`
414	71	creep	`FETCH_HIGH: begin`
415			`if (jump) begin`
416	68	creep	`next_state = FETCH_OP;`
417	61	creep	`end`
418	71	creep	`else if (read \|\| read_modify_write) begin`
419			`next_state = READ_MEM;`
420	61	creep	`end`
421	71	creep	`else if (write) begin`
422			`next_state = WRITE_MEM;`
423	68	creep	`end`
424	71	creep	`else begin`
425			`$write("unknown behavior");`
426			`$finish(0);`
427	61	creep	`end`
428	71	creep	`end`
429	86	creep	`READ_MEM_CALC_INDEX: begin`
430			`if (read \|\| read_modify_write) begin`
431			`next_state = READ_MEM;`
432			`end`
433			`else if (write) begin`
434			`alu_opcode = ir;`
435			`alu_enable = 1'b1;`
436			`next_state = WRITE_MEM;`
437			`end`
438			`else begin`
439			`$write("unknown behavior");`
440			`$finish(0);`
441			`end`
442			`end`
443	71	creep	`READ_MEM: begin`
444			`if (read) begin`
445			`next_state = FETCH_OP_CALC_PARAM;`
446	61	creep	`end`
447	71	creep	`else if (read_modify_write) begin`
448			`next_state = DUMMY_WRT_CALC;`
449			`end`
450			`end`
451			`DUMMY_WRT_CALC: begin`
452			`alu_opcode = ir;`
453			`alu_enable = 1'b1;`
454			`alu_a = data_in;`
455			`next_state = WRITE_MEM;`
456			`end`
457			`WRITE_MEM: begin`
458			`next_state = FETCH_OP;`
459			`end`
460			`default: begin`
461			`next_state = RESET;`
462			`end`
463			`endcase`
464	61	creep	`end`
465
466	77	creep	`// this always block is responsible for updating the address mode and the type of operation being done`
467	68	creep	`always @ (*) begin //`
468	61	creep	`absolute = 1'b0;`
469			`absolute_indexed = 1'b0;`
470			`accumulator = 1'b0;`
471			`immediate = 1'b0;`
472			`implied = 1'b0;`
473			`indirect = 1'b0;`
474			`relative = 1'b0;`
475			`zero_page = 1'b0;`
476			`zero_page_indexed = 1'b0;`
477	86	creep
478			`index = 1'b0;`
479	61	creep
480			`read = 1'b0;`
481			`read_modify_write = 1'b0;`
482			`write = 1'b0;`
483			`jump = 1'b0;`
484
485	70	creep	`case (ir)`
486			`BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,`
487			`PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin`
488			`implied = 1'b1;`
489			`end`
490			`ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin`
491			`accumulator = 1'b1;`
492			`end`
493			`ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin`
494			`immediate = 1'b1;`
495			`end`
496			`ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,`
497			`LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin`
498			`zero_page = 1'b1;`
499			`end`
500			`ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,`

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