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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t6507 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t6507 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// I/O wrapper for the 6507 processor                                 ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "stubs.v"
module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);
        parameter [3:0] DATA_SIZE = 4'd8;
        parameter [3:0] ADDR_SIZE = 4'd13;
 
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
        input clk;
        wire clkIO;
 
        input reset_n;
        wire reset_nIO;
 
        input [DATA_SIZE_:0] data_in;
        reg [DATA_SIZE_:0] data_inIO;
 
        output rw_mem;
        wire rw_memIO;
 
        output [DATA_SIZE_:0] data_out;
        reg [DATA_SIZE_:0] data_outIO;
 
        output [ADDR_SIZE_:0] address;
        reg [ADDR_SIZE_:0] addressIO;
 
        wire clampc;
        wire pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, chainfinal;
 
        wire muxed;
 
        t6507lp t6507lp(  //core
                .clk            (clkIO),
                .reset_n        (reset_nIO),
                .data_in        (data_inIO),
                .rw_mem         (rw_memIO),
                .data_out       (data_outIO),
                .address        (addressIO)
        );
 
        assign muxed = (reset_nIO == 0) ? chainfinal : rw_memIO;
 
        wire dummy_vdd, dummy_gnd, dummy_clampc;
 
        ICP clk_pad(
                .PAD    (clk),
                .PI     (pipo9),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (chain_final),
                .Y      (clkIO)
        );
 
        ICP reset_n_pad(
                .PAD    (reset_n),
                .PI     (pipo8),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo9),
                .Y      (reset_nIO)
        );
 
        ICP data_in_pad0(
                .PAD    (data_in[0]),
                .PI     (pipo7),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo8),
                .Y      (data_inIO[0])
        );
 
        ICP data_in_pad1(
                .PAD    (data_in[1]),
                .PI     (pipo6),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo7),
                .Y      (data_inIO[1])
        );
 
        ICP data_in_pad2(
                .PAD    (data_in[2]),
                .PI     (pipo5),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo6),
                .Y      (data_inIO[2])
        );
 
        ICP data_in_pad3(
                .PAD    (data_in[3]),
                .PI     (pipo4),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo5),
                .Y      (data_inIO[3])
        );
 
        ICP data_in_pad4(
                .PAD    (data_in[4]),
                .PI     (pipo3),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo4),
                .Y      (data_inIO[4])
        );
 
        ICP data_in_pad5(
                .PAD    (data_in[5]),
                .PI     (pipo2),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo3),
                .Y      (data_inIO[5])
        );
 
        ICP data_in_pad6(
                .PAD    (data_in[6]),
                .PI     (pipo1),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo2),
                .Y      (data_inIO[6])
        );
 
        ICP data_in_pad7(
                .PAD    (data_in[7]),
                .PI     (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PO     (pipo1),
                .Y      (data_inIO[7])
        );
 
        BT4P rw_mem_pad(
                .A      (muxed),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (rw_mem)
        );
 
        BT4P data_out_pad0(
                .A      (data_outIO[0]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[0])
        );
 
        BT4P data_out_pad1(
                .A      (data_outIO[1]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[1])
        );
 
        BT4P data_out_pad2(
                .A      (data_outIO[2]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[2])
        );
 
        BT4P data_out_pad3(
                .A      (data_outIO[3]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[3])
        );
 
        BT4P data_out_pad4(
                .A      (data_outIO[4]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[4])
        );
 
        BT4P data_out_pad5(
                .A      (data_outIO[5]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[5])
        );
 
        BT4P data_out_pad6(
                .A      (data_outIO[6]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[6])
        );
 
        BT4P data_out_pad7(
                .A      (data_outIO[7]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (data_out[7])
        );
 
        BT4P address_pad0(
                .A      (addressIO[0]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[0])
        );
 
        BT4P address_pad1(
                .A      (addressIO[1]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[1])
        );
        BT4P address_pad2(
                .A      (addressIO[2]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[2])
        );
        BT4P address_pad3(
                .A      (addressIO[3]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[3])
        );
        BT4P address_pad4(
                .A      (addressIO[4]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[4])
        );
        BT4P address_pad5(
                .A      (addressIO[5]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[5])
        );
        BT4P address_pad6(
                .A      (addressIO[6]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[6])
        );
        BT4P address_pad7(
                .A      (addressIO[7]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[7])
        );
        BT4P address_pad8(
                .A      (addressIO[8]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[8])
        );
        BT4P address_pad9(
                .A      (addressIO[9]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[9])
        );
        BT4P address_pad10(
                .A      (addressIO[10]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[10])
        );
        BT4P address_pad11(
                .A      (addressIO[11]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[11])
        );
 
        BT4P address_pad12(
                .A      (addressIO[12]),
                .EN     (dummy_gnd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .CLAMPC (dummy_clampc),
                .PAD    (address[12])
        );
 
        CORNERCLMP left_up_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
 
        CORNERCLMP left_down_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
 
        CORNERCLMP right_up_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
 
        CORNERCLMP right_down_pad (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
 
        GND5ALLPADP gnd_pad_left (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND    (dummy_gnd)
        );
 
        GND5ALLPADP gnd_pad_right (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND    (dummy_gnd)
        );
 
        GND5ALLPADP gnd_pad_up (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND    (dummy_gnd)
        );
 
        GND5ALLPADP gnd_pad_down (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND    (dummy_gnd)
        );
 
        VDD5ALLPADP vdd_pad_left (
                .CLAMPC (dummy_clampc),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD    (dummy_vdd)
        );
 
        VDD5ALLPADP vdd_pad_right (
                .CLAMPC (dummy_clampc),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD    (dummy_vdd)
        );
 
        VDD5ALLPADP vdd_pad_up (
                .CLAMPC (dummy_clampc),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD    (dummy_vdd)
        );
 
        VDD5ALLPADP vdd_pad_down (
                .CLAMPC (dummy_clampc),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd),
                .VDD    (dummy_vdd)
        );
 
        FILLERP_110 filler0 (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
 
        FILLERP_110 filler1 (
                .CLAMPC (dummy_clampc),
                .VDD5O  (dummy_vdd),
                .VDD5R  (dummy_vdd),
                .GND5O  (dummy_gnd),
                .GND5R  (dummy_gnd)
        );
endmodule

Line No.	Rev	Author	Line
1	251	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	255	creep	`//// t6507 IP Core ////`
4	251	creep	`//// ////`
5	255	creep	`//// This file is part of the t6507 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7	251	creep	`//// ////`
8			`//// Description ////`
9	255	creep	`//// I/O wrapper for the 6507 processor ////`
10	251	creep	`//// ////`
11			`//// Author(s): ////`
12			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
13			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
14			`//// ////`
15			`////////////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`////////////////////////////////////////////////////////////////////////////`
41
42			`include "timescale.v"
43	252	creep	`include "stubs.v"
44	255	creep	`module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);`
45	251	creep	`parameter [3:0] DATA_SIZE = 4'd8;`
46			`parameter [3:0] ADDR_SIZE = 4'd13;`
47
48			`localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;`
49			`localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;`
50
51	252	creep	`input clk;`
52	255	creep	`wire clkIO;`
53	252	creep
54			`input reset_n;`
55	255	creep	`wire reset_nIO;`
56	252	creep
57			`input [DATA_SIZE_:0] data_in;`
58	255	creep	`reg [DATA_SIZE_:0] data_inIO;`
59	252	creep
60	255	creep	`output rw_mem;`
61			`wire rw_memIO;`
62	252	creep
63	255	creep	`output [DATA_SIZE_:0] data_out;`
64			`reg [DATA_SIZE_:0] data_outIO;`
65	252	creep
66	255	creep	`output [ADDR_SIZE_:0] address;`
67			`reg [ADDR_SIZE_:0] addressIO;`
68	252	creep
69	255	creep	`wire clampc;`
70			`wire pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, chainfinal;`
71
72			`wire muxed;`
73
74			`t6507lp t6507lp( //core`
75			`.clk (clkIO),`
76			`.reset_n (reset_nIO),`
77			`.data_in (data_inIO),`
78			`.rw_mem (rw_memIO),`
79			`.data_out (data_outIO),`
80			`.address (addressIO)`
81			`);`
82
83			`assign muxed = (reset_nIO == 0) ? chainfinal : rw_memIO;`
84
85			`wire dummy_vdd, dummy_gnd, dummy_clampc;`
86
87	252	creep	`ICP clk_pad(`
88	255	creep	`.PAD (clk),`
89			`.PI (pipo9),`
90			`.GND5O (dummy_gnd),`
91			`.GND5R (dummy_gnd),`
92			`.VDD5O (dummy_vdd),`
93			`.VDD5R (dummy_vdd),`
94			`.CLAMPC (dummy_clampc),`
95			`.PO (chain_final),`
96	252	creep	`.Y (clkIO)`
97	251	creep	`);`
98
99	252	creep	`ICP reset_n_pad(`
100	255	creep	`.PAD (reset_n),`
101			`.PI (pipo8),`
102			`.GND5O (dummy_gnd),`
103			`.GND5R (dummy_gnd),`
104			`.VDD5O (dummy_vdd),`
105			`.VDD5R (dummy_vdd),`
106			`.CLAMPC (dummy_clampc),`
107			`.PO (pipo9),`
108	252	creep	`.Y (reset_nIO)`
109			`);`
110
111			`ICP data_in_pad0(`
112	255	creep	`.PAD (data_in[0]),`
113			`.PI (pipo7),`
114			`.GND5O (dummy_gnd),`
115			`.GND5R (dummy_gnd),`
116			`.VDD5O (dummy_vdd),`
117			`.VDD5R (dummy_vdd),`
118			`.CLAMPC (dummy_clampc),`
119			`.PO (pipo8),`
120	252	creep	`.Y (data_inIO[0])`
121			`);`
122
123			`ICP data_in_pad1(`
124	255	creep	`.PAD (data_in[1]),`
125			`.PI (pipo6),`
126			`.GND5O (dummy_gnd),`
127			`.GND5R (dummy_gnd),`
128			`.VDD5O (dummy_vdd),`
129			`.VDD5R (dummy_vdd),`
130			`.CLAMPC (dummy_clampc),`
131			`.PO (pipo7),`
132	252	creep	`.Y (data_inIO[1])`
133			`);`
134
135			`ICP data_in_pad2(`
136	255	creep	`.PAD (data_in[2]),`
137			`.PI (pipo5),`
138			`.GND5O (dummy_gnd),`
139			`.GND5R (dummy_gnd),`
140			`.VDD5O (dummy_vdd),`
141			`.VDD5R (dummy_vdd),`
142			`.CLAMPC (dummy_clampc),`
143			`.PO (pipo6),`
144	252	creep	`.Y (data_inIO[2])`
145			`);`
146
147			`ICP data_in_pad3(`
148	255	creep	`.PAD (data_in[3]),`
149			`.PI (pipo4),`
150			`.GND5O (dummy_gnd),`
151			`.GND5R (dummy_gnd),`
152			`.VDD5O (dummy_vdd),`
153			`.VDD5R (dummy_vdd),`
154			`.CLAMPC (dummy_clampc),`
155			`.PO (pipo5),`
156	252	creep	`.Y (data_inIO[3])`
157			`);`
158
159			`ICP data_in_pad4(`
160	255	creep	`.PAD (data_in[4]),`
161			`.PI (pipo3),`
162			`.GND5O (dummy_gnd),`
163			`.GND5R (dummy_gnd),`
164			`.VDD5O (dummy_vdd),`
165			`.VDD5R (dummy_vdd),`
166			`.CLAMPC (dummy_clampc),`
167			`.PO (pipo4),`
168	252	creep	`.Y (data_inIO[4])`
169			`);`
170
171			`ICP data_in_pad5(`
172	255	creep	`.PAD (data_in[5]),`
173			`.PI (pipo2),`
174			`.GND5O (dummy_gnd),`
175			`.GND5R (dummy_gnd),`
176			`.VDD5O (dummy_vdd),`
177			`.VDD5R (dummy_vdd),`
178			`.CLAMPC (dummy_clampc),`
179			`.PO (pipo3),`
180	252	creep	`.Y (data_inIO[5])`
181			`);`
182
183			`ICP data_in_pad6(`
184	255	creep	`.PAD (data_in[6]),`
185			`.PI (pipo1),`
186			`.GND5O (dummy_gnd),`
187			`.GND5R (dummy_gnd),`
188			`.VDD5O (dummy_vdd),`
189			`.VDD5R (dummy_vdd),`
190			`.CLAMPC (dummy_clampc),`
191			`.PO (pipo2),`
192	252	creep	`.Y (data_inIO[6])`
193			`);`
194
195			`ICP data_in_pad7(`
196	255	creep	`.PAD (data_in[7]),`
197			`.PI (dummy_vdd),`
198			`.GND5O (dummy_gnd),`
199			`.GND5R (dummy_gnd),`
200			`.VDD5O (dummy_vdd),`
201			`.VDD5R (dummy_vdd),`
202			`.CLAMPC (dummy_clampc),`
203			`.PO (pipo1),`
204	252	creep	`.Y (data_inIO[7])`
205			`);`
206
207	255	creep	`BT4P rw_mem_pad(`
208			`.A (muxed),`
209			`.EN (dummy_gnd),`
210			`.GND5O (dummy_gnd),`
211			`.GND5R (dummy_gnd),`
212			`.VDD5O (dummy_vdd),`
213			`.VDD5R (dummy_vdd),`
214			`.CLAMPC (dummy_clampc),`
215			`.PAD (rw_mem)`
216	252	creep	`);`
217
218	255	creep	`BT4P data_out_pad0(`
219			`.A (data_outIO[0]),`
220			`.EN (dummy_gnd),`
221			`.GND5O (dummy_gnd),`
222			`.GND5R (dummy_gnd),`
223			`.VDD5O (dummy_vdd),`
224			`.VDD5R (dummy_vdd),`
225			`.CLAMPC (dummy_clampc),`
226			`.PAD (data_out[0])`
227	252	creep	`);`
228
229	255	creep	`BT4P data_out_pad1(`
230			`.A (data_outIO[1]),`
231			`.EN (dummy_gnd),`
232			`.GND5O (dummy_gnd),`
233			`.GND5R (dummy_gnd),`
234			`.VDD5O (dummy_vdd),`
235			`.VDD5R (dummy_vdd),`
236			`.CLAMPC (dummy_clampc),`
237			`.PAD (data_out[1])`
238	252	creep	`);`
239
240	255	creep	`BT4P data_out_pad2(`
241			`.A (data_outIO[2]),`
242			`.EN (dummy_gnd),`
243			`.GND5O (dummy_gnd),`
244			`.GND5R (dummy_gnd),`
245			`.VDD5O (dummy_vdd),`
246			`.VDD5R (dummy_vdd),`
247			`.CLAMPC (dummy_clampc),`
248			`.PAD (data_out[2])`
249	252	creep	`);`
250
251	255	creep	`BT4P data_out_pad3(`
252			`.A (data_outIO[3]),`
253			`.EN (dummy_gnd),`
254			`.GND5O (dummy_gnd),`
255			`.GND5R (dummy_gnd),`
256			`.VDD5O (dummy_vdd),`
257			`.VDD5R (dummy_vdd),`
258			`.CLAMPC (dummy_clampc),`
259			`.PAD (data_out[3])`
260	252	creep	`);`
261
262	255	creep	`BT4P data_out_pad4(`
263			`.A (data_outIO[4]),`
264			`.EN (dummy_gnd),`
265			`.GND5O (dummy_gnd),`
266			`.GND5R (dummy_gnd),`
267			`.VDD5O (dummy_vdd),`
268			`.VDD5R (dummy_vdd),`
269			`.CLAMPC (dummy_clampc),`
270			`.PAD (data_out[4])`
271	252	creep	`);`
272
273	255	creep	`BT4P data_out_pad5(`
274			`.A (data_outIO[5]),`
275			`.EN (dummy_gnd),`
276			`.GND5O (dummy_gnd),`
277			`.GND5R (dummy_gnd),`
278			`.VDD5O (dummy_vdd),`
279			`.VDD5R (dummy_vdd),`
280			`.CLAMPC (dummy_clampc),`
281			`.PAD (data_out[5])`
282	252	creep	`);`
283
284	255	creep	`BT4P data_out_pad6(`
285			`.A (data_outIO[6]),`
286			`.EN (dummy_gnd),`
287			`.GND5O (dummy_gnd),`
288			`.GND5R (dummy_gnd),`
289			`.VDD5O (dummy_vdd),`
290			`.VDD5R (dummy_vdd),`
291			`.CLAMPC (dummy_clampc),`
292			`.PAD (data_out[6])`
293	252	creep	`);`
294
295	255	creep	`BT4P data_out_pad7(`
296			`.A (data_outIO[7]),`
297			`.EN (dummy_gnd),`
298			`.GND5O (dummy_gnd),`
299			`.GND5R (dummy_gnd),`
300			`.VDD5O (dummy_vdd),`
301			`.VDD5R (dummy_vdd),`
302			`.CLAMPC (dummy_clampc),`
303			`.PAD (data_out[7])`
304	252	creep	`);`
305
306	255	creep	`BT4P address_pad0(`
307			`.A (addressIO[0]),`
308			`.EN (dummy_gnd),`
309			`.GND5O (dummy_gnd),`
310			`.GND5R (dummy_gnd),`
311			`.VDD5O (dummy_vdd),`
312			`.VDD5R (dummy_vdd),`
313			`.CLAMPC (dummy_clampc),`
314			`.PAD (address[0])`
315	252	creep	`);`
316
317	255	creep	`BT4P address_pad1(`
318			`.A (addressIO[1]),`
319			`.EN (dummy_gnd),`
320			`.GND5O (dummy_gnd),`
321			`.GND5R (dummy_gnd),`
322			`.VDD5O (dummy_vdd),`
323			`.VDD5R (dummy_vdd),`
324			`.CLAMPC (dummy_clampc),`
325			`.PAD (address[1])`
326	252	creep	`);`
327	255	creep	`BT4P address_pad2(`
328			`.A (addressIO[2]),`
329			`.EN (dummy_gnd),`
330			`.GND5O (dummy_gnd),`
331			`.GND5R (dummy_gnd),`
332			`.VDD5O (dummy_vdd),`
333			`.VDD5R (dummy_vdd),`
334			`.CLAMPC (dummy_clampc),`
335			`.PAD (address[2])`
336			`);`
337			`BT4P address_pad3(`
338			`.A (addressIO[3]),`
339			`.EN (dummy_gnd),`
340			`.GND5O (dummy_gnd),`
341			`.GND5R (dummy_gnd),`
342			`.VDD5O (dummy_vdd),`
343			`.VDD5R (dummy_vdd),`
344			`.CLAMPC (dummy_clampc),`
345			`.PAD (address[3])`
346			`);`
347			`BT4P address_pad4(`
348			`.A (addressIO[4]),`
349			`.EN (dummy_gnd),`
350			`.GND5O (dummy_gnd),`
351			`.GND5R (dummy_gnd),`
352			`.VDD5O (dummy_vdd),`
353			`.VDD5R (dummy_vdd),`
354			`.CLAMPC (dummy_clampc),`
355			`.PAD (address[4])`
356			`);`
357			`BT4P address_pad5(`
358			`.A (addressIO[5]),`
359			`.EN (dummy_gnd),`
360			`.GND5O (dummy_gnd),`
361			`.GND5R (dummy_gnd),`
362			`.VDD5O (dummy_vdd),`
363			`.VDD5R (dummy_vdd),`
364			`.CLAMPC (dummy_clampc),`
365			`.PAD (address[5])`
366			`);`
367			`BT4P address_pad6(`
368			`.A (addressIO[6]),`
369			`.EN (dummy_gnd),`
370			`.GND5O (dummy_gnd),`
371			`.GND5R (dummy_gnd),`
372			`.VDD5O (dummy_vdd),`
373			`.VDD5R (dummy_vdd),`
374			`.CLAMPC (dummy_clampc),`
375			`.PAD (address[6])`
376			`);`
377			`BT4P address_pad7(`
378			`.A (addressIO[7]),`
379			`.EN (dummy_gnd),`
380			`.GND5O (dummy_gnd),`
381			`.GND5R (dummy_gnd),`
382			`.VDD5O (dummy_vdd),`
383			`.VDD5R (dummy_vdd),`
384			`.CLAMPC (dummy_clampc),`
385			`.PAD (address[7])`
386			`);`
387			`BT4P address_pad8(`
388			`.A (addressIO[8]),`
389			`.EN (dummy_gnd),`
390			`.GND5O (dummy_gnd),`
391			`.GND5R (dummy_gnd),`
392			`.VDD5O (dummy_vdd),`
393			`.VDD5R (dummy_vdd),`
394			`.CLAMPC (dummy_clampc),`
395			`.PAD (address[8])`
396			`);`
397			`BT4P address_pad9(`
398			`.A (addressIO[9]),`
399			`.EN (dummy_gnd),`
400			`.GND5O (dummy_gnd),`
401			`.GND5R (dummy_gnd),`
402			`.VDD5O (dummy_vdd),`
403			`.VDD5R (dummy_vdd),`
404			`.CLAMPC (dummy_clampc),`
405			`.PAD (address[9])`
406			`);`
407			`BT4P address_pad10(`
408			`.A (addressIO[10]),`
409			`.EN (dummy_gnd),`
410			`.GND5O (dummy_gnd),`
411			`.GND5R (dummy_gnd),`
412			`.VDD5O (dummy_vdd),`
413			`.VDD5R (dummy_vdd),`
414			`.CLAMPC (dummy_clampc),`
415			`.PAD (address[10])`
416			`);`
417			`BT4P address_pad11(`
418			`.A (addressIO[11]),`
419			`.EN (dummy_gnd),`
420			`.GND5O (dummy_gnd),`
421			`.GND5R (dummy_gnd),`
422			`.VDD5O (dummy_vdd),`
423			`.VDD5R (dummy_vdd),`
424			`.CLAMPC (dummy_clampc),`
425			`.PAD (address[11])`
426			`);`
427	252	creep
428	255	creep	`BT4P address_pad12(`
429			`.A (addressIO[12]),`
430			`.EN (dummy_gnd),`
431			`.GND5O (dummy_gnd),`
432			`.GND5R (dummy_gnd),`
433			`.VDD5O (dummy_vdd),`
434			`.VDD5R (dummy_vdd),`
435			`.CLAMPC (dummy_clampc),`
436			`.PAD (address[12])`
437	252	creep	`);`
438
439	255	creep	`CORNERCLMP left_up_pad (`
440			`.CLAMPC (dummy_clampc),`
441			`.VDD5O (dummy_vdd),`
442			`.VDD5R (dummy_vdd),`
443			`.GND5O (dummy_gnd),`
444			`.GND5R (dummy_gnd)`
445	252	creep	`);`
446
447	255	creep	`CORNERCLMP left_down_pad (`
448			`.CLAMPC (dummy_clampc),`
449			`.VDD5O (dummy_vdd),`
450			`.VDD5R (dummy_vdd),`
451			`.GND5O (dummy_gnd),`
452			`.GND5R (dummy_gnd)`
453	252	creep	`);`
454
455	255	creep	`CORNERCLMP right_up_pad (`
456			`.CLAMPC (dummy_clampc),`
457			`.VDD5O (dummy_vdd),`
458			`.VDD5R (dummy_vdd),`
459			`.GND5O (dummy_gnd),`
460			`.GND5R (dummy_gnd)`
461	252	creep	`);`
462
463	255	creep	`CORNERCLMP right_down_pad (`
464			`.CLAMPC (dummy_clampc),`
465			`.VDD5O (dummy_vdd),`
466			`.VDD5R (dummy_vdd),`
467			`.GND5O (dummy_gnd),`
468			`.GND5R (dummy_gnd)`
469	252	creep	`);`
470
471	255	creep	`GND5ALLPADP gnd_pad_left (`
472			`.CLAMPC (dummy_clampc),`
473			`.VDD5O (dummy_vdd),`
474			`.VDD5R (dummy_vdd),`
475			`.GND (dummy_gnd)`
476	252	creep	`);`
477
478	255	creep	`GND5ALLPADP gnd_pad_right (`
479			`.CLAMPC (dummy_clampc),`
480			`.VDD5O (dummy_vdd),`
481			`.VDD5R (dummy_vdd),`
482			`.GND (dummy_gnd)`
483	252	creep	`);`
484
485	255	creep	`GND5ALLPADP gnd_pad_up (`
486			`.CLAMPC (dummy_clampc),`
487			`.VDD5O (dummy_vdd),`
488			`.VDD5R (dummy_vdd),`
489			`.GND (dummy_gnd)`
490	252	creep	`);`
491
492	255	creep	`GND5ALLPADP gnd_pad_down (`
493			`.CLAMPC (dummy_clampc),`
494			`.VDD5O (dummy_vdd),`
495			`.VDD5R (dummy_vdd),`
496			`.GND (dummy_gnd)`
497	252	creep	`);`
498
499	255	creep	`VDD5ALLPADP vdd_pad_left (`
500			`.CLAMPC (dummy_clampc),`

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