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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [video.v] - Blame information for rev 235

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1 215 creep
////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// t2600 IP Core                                                      ////
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////                                                                    ////
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//// This file is part of the t2600 project                             ////
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//// http://www.opencores.org/cores/t2600/                              ////
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////                                                                    ////
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//// Description                                                        ////
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//// Video module                                                       ////
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////                                                                    ////
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//// TODO:                                                              ////
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//// - Collision detection                                              ////
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//// - Pixel output                                                     ////
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////                                                                    ////
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//// Author(s):                                                         ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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////                                                                    ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
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////                                                                    ////
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//// This source file may be used and distributed without               ////
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//// restriction provided that this copyright statement is not          ////
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//// removed from the file and that any derivative work contains        ////
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//// the original copyright notice and the associated disclaimer.       ////
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////                                                                    ////
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//// This source file is free software; you can redistribute it         ////
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//// and/or modify it under the terms of the GNU Lesser General         ////
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//// Public License as published by the Free Software Foundation;       ////
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//// either version 2.1 of the License, or (at your option) any         ////
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//// later version.                                                     ////
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////                                                                    ////
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//// This source is distributed in the hope that it will be             ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
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//// PURPOSE. See the GNU Lesser General Public License for more        ////
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//// details.                                                           ////
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////                                                                    ////
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//// You should have received a copy of the GNU Lesser General          ////
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//// Public License along with this source; if not, download it         ////
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//// from http://www.opencores.org/lgpl.shtml                           ////
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////                                                                    ////
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////////////////////////////////////////////////////////////////////////////
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46
`include "timescale.v"
47
 
48 235 creep
module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel, write_addr, write_data, write_enable_n);
49 215 creep
        parameter [3:0] DATA_SIZE = 4'd8;
50
        parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
51
 
52
        localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
53
        localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
54
 
55
        input clk; // master clock signal, 1.19mhz
56
        input reset_n;
57
        input [15:0] io_lines; // inputs from the keyboard controller
58
        input enable; // since the address bus is shared an enable signal is used
59
        input mem_rw; // read == 0, write == 1
60
        input [ADDR_SIZE_:0] address; // system address bus
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        inout [DATA_SIZE_:0] data; // controler <=> video data bus
62
        output reg [2:0] pixel;
63
        output reg [10:0] write_addr; // for the video memory
64
        output reg [2:0] write_data;
65
        output reg write_enable_n;
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67 215 creep
        reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
68
 
69
        assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data. 
70
 
71
        reg VSYNC; // vertical sync set-clear
72 216 creep
        reg [2:0] VBLANK; // vertical blank set-clear
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        reg WSYNC; //  SEMI-strobe wait for leading edge of horizontal blank
74 215 creep
        reg RSYNC; //  s t r o b e reset horizontal sync counter
75 216 creep
        reg [5:0] NUSIZ0; //  number-size player-missile 0
76
        reg [5:0] NUSIZ1; //  number-size player-missile 1
77
        reg [6:0] COLUP0; //  color-lum player 0
78
        reg [6:0] COLUP1; //  color-lum player 1
79
        reg [6:0] COLUPF; //  color-lum playfield
80
        reg [6:0] COLUBK; //  color-lum background
81
        reg [4:0] CTRLPF; //  control playfield ball size & collisions
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                // D0 = REF (reflect playfield)
83
                // D1 = SCORE (left half of playfield gets color of player 0, right half gets color of player 1)
84
                // D2 = PFP (playfield gets priority over players so they can move behind the playfield)
85
                // D4 & D5 = BALL SIZE
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        reg REFP0; //  reflect player 0
87
        reg REFP1; //  reflect player 1
88
        reg [3:0] PF0; //  playfield register byte 0
89
        reg [7:0] PF1; //  playfield register byte 1
90
        reg [7:0] PF2; //  playfield register byte 2
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        //reg RESP0; //  s t r o b e reset player 0
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        reg RESP1; //  s t r o b e reset player 1
93
        reg RESM0; //  s t r o b e reset missile 0
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        reg RESM1; //  s t r o b e reset missile 1
95
        reg RESBL; //  s t r o b e reset ball
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        reg [3:0] AUDC0; //  audio control 0
97
        reg [4:0] AUDC1; //  audio control 1
98
        reg [4:0] AUDF0; //  audio frequency 0
99
        reg [3:0] AUDF1; //  audio frequency 1
100
        reg [3:0] AUDV0; //  audio volume 0
101
        reg [3:0] AUDV1; //  audio volume 1
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        reg [7:0] GRP0; //  graphics player 0
103
        reg [7:0] GRP1; //  graphics player 1
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        reg ENAM0; //  graphics (enable) missile 0
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        reg ENAM1; //  graphics (enable) missile 1
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        reg ENABL; //  graphics (enable) ball
107
        reg [3:0] HMP0; //  horizontal motion player 0
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        reg [3:0] HMP1; //  horizontal motion player 1
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        reg [3:0] HMM0; //  horizontal motion missile 0
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        reg [3:0] HMM1; //  horizontal motion missile 1
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        reg [3:0] HMBL; //  horizontal motion ball
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        reg VDELP0; //  vertical delay player 0
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        reg VDEL01; //  vertical delay player 1
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        reg VDELBL; //  vertical delay ball
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        reg RESMP0; //  reset missile 0 to player 0
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        reg RESMP1; //  reset missile 1 to player 1
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        reg HMOVE; //  s t r o b e apply horizontal motion
118
        reg HMCLR; //  s t r o b e clear horizontal motion registers
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        reg [1:0] CXM0P; // read collision MO P1 M0 P0
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        reg [1:0] CXM1P; // read collision M1 P0 M1 P1
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        reg [1:0] CXP0FB; // read collision P0 PF P0 BL
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        reg [1:0] CXP1FB; // read collision P1 PF P1 BL
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        reg [1:0] CXM0FB; // read collision M0 PF M0 BL
125
        reg [1:0] CXM1FB; // read collision M1 PF M1 BL
126
        reg CXBLPF; // read collision BL PF unused
127
        reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
128
        reg INPT0; // read pot port
129
        reg INPT1; // read pot port
130
        reg INPT2; // read pot port
131
        reg INPT3; // read pot port
132
        reg INPT4; // read input
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        reg INPT5; // read input
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135 235 creep
        reg [8:0] vert_counter;
136
        reg [7:0] hor_counter;
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138 216 creep
        always @(posedge clk  or negedge reset_n) begin
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                if (reset_n == 1'b0) begin
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                        hor_counter <= 8'd0;
141
                        vert_counter <= 9'd0;
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                end
143
                else begin
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                        if (hor_counter == 8'd227) begin
145
                                hor_counter <= 8'd0;
146
                                WSYNC <= 1'b0; // TODO: check this on stella pdf
147
 
148
                                if (vert_counter == 9'd261) begin
149
                                        vert_counter <= 9'd0;
150
                                end
151
                                else begin
152
                                        vert_counter <= vert_counter + 9'd1;
153
                                end
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                        end
155
                        else begin
156
                                hor_counter <= hor_counter + 6'd1;
157
                        end
158
                end
159
        end
160
 
161
        always @(posedge clk  or negedge reset_n) begin
162
                if (reset_n == 1'b0) begin
163 215 creep
                        data_drv <= 8'h00;
164 222 creep
                        WSYNC <= 1'b0;
165 215 creep
                end
166 235 creep
                else if (enable == 1'b1) begin
167 216 creep
                        if (mem_rw == 1'b0) begin // reading! 
168 215 creep
                                case (address)
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                                        6'h00: data_drv <= {CXM0P, 6'b000000};
170
                                        6'h01: data_drv <= {CXM1P, 6'b000000};
171
                                        6'h02: data_drv <= {CXP0FB, 6'b000000};
172
                                        6'h03: data_drv <= {CXP1FB, 6'b000000};
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                                        6'h04: data_drv <= {CXM0FB, 6'b000000};
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                                        6'h05: data_drv <= {CXM1FB, 6'b000000};
175
                                        6'h06: data_drv <= {CXBLPF, 7'b000000};
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                                        6'h07: data_drv <= {CXPPMM, 6'b000000};
177
                                        6'h08: data_drv <= {INPT0, 7'b000000};
178
                                        6'h09: data_drv <= {INPT1, 7'b000000};
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                                        6'h0A: data_drv <= {INPT2, 7'b000000};
180
                                        6'h0B: data_drv <= {INPT3, 7'b000000};
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                                        6'h0C: data_drv <= {INPT4, 7'b000000};
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                                        6'h0D: data_drv <= {INPT5, 7'b000000};
183
                                        default: ;
184 215 creep
                                endcase
185
                        end
186 216 creep
                        else begin // writing! 
187 215 creep
                                case (address)
188 216 creep
                                        6'h00: begin
189 217 creep
                                                VSYNC <= data[1];
190 215 creep
                                        end
191 216 creep
                                        6'h01: begin
192 217 creep
                                                VBLANK <= {data[7:6], data[1]};
193 215 creep
                                        end
194 216 creep
                                        6'h02: begin
195 217 creep
                                                WSYNC <= 1'b1; // STROBE
196 215 creep
                                        end
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                                        6'h03: begin
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                                                RSYNC <= 1'b1; // STROBE
199 215 creep
                                        end
200 216 creep
                                        6'h04: begin
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                                                NUSIZ0 <= data[5:0];
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                                        end
203
                                        6'h05: begin
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                                                NUSIZ1 <= data[5:0];
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                                        end
206
                                        6'h06: begin
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                                                COLUP0 <= data[7:1];
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                                        end
209
                                        6'h07: begin
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                                                COLUP1 <= data[7:1];
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                                        end
212
                                        6'h08: begin
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                                                COLUPF <= data[7:1];
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                                        end
215
                                        6'h09: begin
216 217 creep
                                                COLUBK <= data[7:1];
217 216 creep
                                        end
218
                                        6'h0a: begin
219 217 creep
                                                CTRLPF <= {data[5:4], data[2:0]};
220 216 creep
                                        end
221
                                        6'h0b: begin
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                                                REFP0 <= data[3];
223 216 creep
                                        end
224
                                        6'h0c: begin
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                                                REFP1 <= data[3];
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                                        end
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                                        6'h0d: begin
228
                                                PF0 <= data[7:4 ];
229
                                        end
230
                                        6'h0e: begin
231
                                                PF1 <= data;
232
                                        end
233
                                        6'h0f: begin
234
                                                PF2 <= data;
235
                                        end
236
                                        6'h10: begin
237 235 creep
                                                //RESP0 <= 1'b1; // STROBE
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                                        end
239
                                        6'h11: begin
240
                                                RESP1 <= 1'b1; // STROBE
241
                                        end
242
                                        6'h12: begin
243
                                                RESM0 <= 1'b1; // STROBE
244
                                        end
245
                                        6'h13: begin
246
                                                RESM1 <= 1'b1; // STROBE
247
                                        end
248
                                        6'h14: begin
249
                                                RESBL <= 1'b1; // STROBE
250
                                        end
251
                                        6'h15: begin
252
                                                AUDC0 <= data[3:0];
253
                                        end
254
                                        6'h16: begin
255
                                                AUDC1 <= data[4:0];
256
                                        end
257
                                        6'h17: begin
258
                                                AUDF0 <= data[4:0];
259
                                        end
260
                                        6'h18: begin
261
                                                AUDF1 <= data[3:0];
262
                                        end
263
                                        6'h19: begin
264
                                                AUDV0 <= data[3:0];
265
                                        end
266
                                        6'h1A: begin
267
                                                AUDV1 <= data[3:0];
268
                                        end
269
                                        6'h1B: begin
270
                                                GRP0 <= data;
271
                                        end
272
                                        6'h1C: begin
273
                                                GRP1 <= data;
274
                                        end
275
                                        6'h1D: begin
276
                                                ENAM0 <= data[1];
277
                                        end
278
                                        6'h1E: begin
279
                                                ENAM1 <= data[1];
280
                                        end
281
                                        6'h1F: begin
282
                                                ENABL <= data[1];
283
                                        end
284
                                        6'h20: begin
285
                                                HMP0 <= data[7:4];
286
                                        end
287
                                        6'h21: begin
288
                                                HMP1 <= data[7:4];
289
                                        end
290
                                        6'h22: begin
291
                                                HMM0 <= data[7:4];
292
                                        end
293
                                        6'h23: begin
294
                                                HMM1 <= data[7:4];
295
                                        end
296
                                        6'h24: begin
297
                                                HMBL <= data[7:4];
298
                                        end
299
                                        6'h25: begin
300
                                                VDELP0 <= data[0];
301
                                        end
302
                                        6'h26: begin
303
                                                VDEL01 <= data[0];
304
                                        end
305
                                        6'h27: begin
306
                                                VDELBL <= data[0];
307
                                        end
308
                                        6'h28: begin
309
                                                RESMP0 <= data[1];
310
                                        end
311
                                        6'h29: begin
312
                                                RESMP1 <= data[1];
313
                                        end
314
                                        6'h2a: begin
315
                                                HMOVE <= 1'b1; // STROBE
316
                                        end
317
                                        6'h2b: begin
318
                                                HMCLR <= 1'b1; // STROBE
319
                                        end
320 221 creep
                                        6'h2c: begin // cxclr STROBE
321
                                                CXM0P <= 2'b0; // read collision MO P1 M0 P0
322
                                                CXM1P <= 2'b0; // read collision M1 P0 M1 P1
323
                                                CXP0FB <= 2'b0; // read collision P0 PF P0 BL
324
                                                CXP1FB <= 2'b0; // read collision P1 PF P1 BL
325
                                                CXM0FB <= 2'b0; // read collision M0 PF M0 BL
326
                                                CXM1FB <= 2'b0; // read collision M1 PF M1 BL
327
                                                CXBLPF <= 2'b0; // read collision BL PF unused
328
                                                CXPPMM <= 2'b0; // read collision P0 P1 M0 M1
329 217 creep
                                        end
330 215 creep
                                        default: begin
331
                                        end
332
                                endcase
333
                        end
334
                end
335
        end
336 235 creep
 
337
reg draw_p0;
338
reg draw_p1;
339
reg draw_m0;
340
reg draw_m1;
341
reg draw_bl;
342
 
343
always @ (*) begin // always combinational block that handles strobe register
344
        draw_p0 = 1'b0;
345
        draw_p1 = 1'b0;
346
        draw_m0 = 1'b0;
347
        draw_m1 = 1'b0;
348
        draw_bl = 1'b0;
349
 
350
        if (enable == 1'b1 && mem_rw == 1'b1) begin // writing! 
351
                case (address)
352
                        6'h10: begin
353
                                draw_p0 = 1'b1;
354
                        end
355
                        6'h11: begin
356
                                draw_p1 = 1'b1;
357
                        end
358
                        6'h12: begin
359
                                draw_m0 = 1'b1;
360
                        end
361
                        6'h13: begin
362
                                draw_m1 = 1'b1;
363
                        end
364
                        6'h14: begin
365
                                draw_bl = 1'b1;
366
                        end
367
                endcase
368
        end
369
end
370
 
371
 
372
always @(*) begin // comb logic
373
        if (hor_counter < 68 || vert_counter < 40 || vert_counter > 232) begin
374
                pixel = 3'd0;
375
                write_enable_n = 1'b1;
376
                write_addr = 0;
377
                write_data = vert_counter[2:0];
378
        end
379
        else begin
380
                write_enable_n = 1'b0;
381
                write_addr = (hor_counter - 68) + (vert_counter - 40)*160;
382
                write_data = 3'd4;
383
 
384
                if (CTRLPF[2] == 1'b1) begin // playfield gets priority over players so they can move behind the playfield
385
                                // Priority Objects
386
                                // 1            PF, BL
387
                                // 2            P0, M0
388
                                // 3            P1, M1
389
                                // 4            BK
390
 
391
                end
392
                else begin // regular priority
393
                                // Priority     Objects
394
                                // 1            P0, M0
395
                                // 2            P1, M1
396
                                // 3            BL, PF
397
                                // 4            BK
398
                        if (CTRLPF[0] == 1'b1) begin// reflected PF
399
                                if (ENABL == 1'b1) begin // the ball is enabled
400
 
401
                                end
402
                                else begin
403
                                        if (vert_counter < 4) begin
404
                                                pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
405
                                        end
406
                                        else if (vert_counter < 12) begin
407
                                                pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
408
                                        end
409
                                        else if (vert_counter < 20) begin
410
                                                pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
411
                                        end
412
                                        else if (vert_counter < 28) begin
413
                                                pixel = (PF2[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
414
                                        end
415
                                        else if (vert_counter < 36) begin
416
                                                pixel = (PF1[vert_counter - 28] == 1'b1) ? COLUPF : COLUBK;
417
                                        end
418
                                        else begin
419
                                                pixel = (PF0[vert_counter - 36] == 1'b1) ? COLUPF : COLUBK;
420
                                        end
421
                                end
422
                        end
423
                        else begin
424
                                if (vert_counter < 4) begin
425
                                        pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
426
                                end
427
                                else if (vert_counter < 12) begin
428
                                        pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
429
                                end
430
                                else if (vert_counter < 20) begin
431
                                        pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
432
                                end
433
                                else if (vert_counter < 24) begin
434
                                        pixel = (PF0[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
435
                                end
436
                                else if (vert_counter < 32) begin
437
                                        pixel = (PF1[vert_counter - 24] == 1'b1) ? COLUPF : COLUBK;
438
                                end
439
                                else begin
440
                                        pixel = (PF2[vert_counter - 32] == 1'b1) ? COLUPF : COLUBK;
441
                                end
442
                        end
443
                end
444
                // 1: ordem de avaliacao
445
                // 2: pinta da cor do objeto
446
                // 3: senao pinta de bk
447
 
448
                        pixel = 3'd4;
449
 
450
        end
451
end
452
 
453 215 creep
 
454
endmodule
455
 

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