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hippo5329 |
OpenCores tiny SPI
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Author(s):
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- Thomas Chou
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This is an 8 bits SPI master controller. It features optional
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programmable baud rate and SPI mode selection. Altera SPI doesn't
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support programmable rate which is needed for MMC SPI, nor does
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Xilinx SPI.
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It is small. It combines transmit and receive buffer and remove unused
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functions. It takes only 36 LEs for SPI flash controller, or 53 LEs for
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MMC SPI controller in an Altera CycoloneIII SOPC project. While Altera
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SPI takes around 143 LEs. OpenCores SPI takes 857 LEs and simple SPI
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takes 171 LEs.
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It doesn't generate SS_n signal. Please use gpio core for SS_n, which
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costs 3- LEs per pin. The gpio number is used for the cs number in
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u-boot and linux drivers.
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Parameters:
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BAUD_WIDTH: bits width of programmable divider
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sclk = clk / ((baud_reg + 1) * 2)
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if BAUD_DIV is not zero, BAUD_WIDTH is ignored.
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BAUD_DIV: fixed divider, must be even
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sclk = clk / BAUD_DIV
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SPI_MODE: value 0-3 fixed mode CPOL,CPHA
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otherwise (eg, 4) programmable mode in control reg[1:0]
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Registers map:
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base+0 R shift register
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base+4 R buffer register
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W buffer register
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base+8 R status
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[1] TXR transfer ready
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[0] TXE transter end
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W irq enable
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[1] TXR_EN transfer ready irq enable
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[0] TXE_EN transter end irq enable
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base+12 W control (optional)
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[1:0] spi mode
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base+16 W baud divider (optional)
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Program flow:
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There is an 8-bits shift register and buffer register.
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1. after reset or idle, TXR=1, TXE=1
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2. first byte written to buffer register, TXR=0, TXE=1
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3. buffer register swabbed with shift register, TXR=1, TXE=0
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shift register has the first byte and starts shifting
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buffer register has (useless) old byte of shift register
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4. second byte written to buffer register, TXR=0, TXE=0
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5. first byte shifted,
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buffer register swabbed with shift register, TXR=1, TXE=0
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shift register has the second byte and starts shifting
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buffer register has the first received byte from shift register
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6. third byte written to buffer register, TXR=0, TXE=0
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7. repeat like 5.
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9. last byte written to buffer register, TXR=0, TXE=0
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10. last-1 byte shifted,
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buffer register swabbed with shift register, TXR=1, TXE=0
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shift register has the last byte and starts shifting
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buffer register has the last-1 received byte from shift register
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11. last byte shifted, no more to write, TXR=1, TXE=1
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shift register has the last received byte
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Interrupt usage:
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Interrupt is controlled with irq enable reg.
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For performace issue, at sclk > 200KHz, interrupt should not be used and
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polling will get better result. In this case, interrupt can be
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disconnected in SOPC builder to save 2 LEs. A 100MHz Nios2 is able to
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serve 25 MHz sclk using polling.
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This core uses zero-wait bus access. Clock crossing bridges between
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CPU and this core might reduce performance.
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