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URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

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[/] [uart16750/] [trunk/] [sim/] [rtl_sim/] [bin/] [uart_test_stim.pl] - Blame information for rev 25

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1 2 hasw
#!/usr/bin/perl
2
 
3
use strict;
4
 
5 12 hasw
# Create stimulus/test file for 16550/16750 compatible UART cores
6 2 hasw
#
7
# Author:   Sebastian Witt
8
# Date:     06.02.2008
9 14 hasw
# Version:  1.4
10 2 hasw
# License:  GPL
11
#
12
# History:  1.0 - Initial version
13
#           1.1 - Update
14
#           1.2 - FIFO test update
15 12 hasw
#           1.3 - Automatic flow control tests
16 14 hasw
#           1.4 - FIFO 64 tests
17 2 hasw
#
18
 
19
 
20
#
21
# Global control settings
22
#
23 14 hasw
use constant CYCLE => 30e-9;            # Cycle time
24
#use constant CYCLE => 1e-9;             # Cycle time
25
use constant LOCAL_LOOP     => 1;       # Use UART local loopback
26
use constant INITREGS       => 1;       # Initialize registers
27
use constant TEST_CONTROL   => 1;       # Test control lines
28
use constant TEST_INTERRUPT => 1;       # Test interrupts
29
use constant TEST_DEFAULT   => 1;       # Test standard modes
30
use constant TEST_FIFO      => 1;       # Test 64 byte FIFO mode
31
use constant TEST_FIFO64    => 1;       # Test 64 byte FIFO mode
32
use constant TEST_AFC       => 1;       # Test automatic flow control
33
use constant UART_ADDRESS   => 0x3f8;   # UART base address
34 2 hasw
 
35
# Prototypes
36
sub logmessage($);          # Message
37
sub uart_write($$);         # Address, Data
38
sub uart_read($$);          # Address, Expected data
39
sub uart_setbaudrate($);    # Baudrate
40 25 hasw
sub uart_eu_send($);        # Send serial data from external UART
41 2 hasw
 
42
##################################################################
43
# Main process
44
##################################################################
45
# Register addresses
46
use constant {
47
    RBR => 0x00,
48
    DLL => 0x00,
49
    THR => 0x00,
50
    DLM => 0x01,
51
    IER => 0x01,
52
    IIR => 0x02,
53
    FCR => 0x02,
54
    LCR => 0x03,
55
    MCR => 0x04,
56
    LSR => 0x05,
57
    MSR => 0x06,
58
    SCR => 0x07,
59
};
60
# Register settings
61
use constant {
62
    IER_ERBI    => 0x01,
63
    IER_ETBEI   => 0x02,
64
    IER_ELSI    => 0x04,
65
    IER_EDSSI   => 0x08,
66
    IIR_IP      => 0x01,
67
    IIR_NONE    => 0x01,
68
    IIR_RLSI    => 0x06,
69
    IIR_RDAI    => 0x04,
70
    IIR_CTOI    => 0x0C,
71
    IIR_THRI    => 0x02,
72
    IIR_MSRI    => 0x00,
73
    IIR_F64E    => 0x20,
74
    IIR_FE      => 0xC0,
75
    FCR_FE      => 0x01,
76
    FCR_RXFR    => 0x02,
77
    FCR_TXFR    => 0x04,
78
    FCR_DMS     => 0x08,
79 14 hasw
    FCR_F64E    => 0x20,
80 2 hasw
    FCR_RT1     => 0x00,
81
    FCR_RT4     => 0x40,
82
    FCR_RT8     => 0x80,
83
    FCR_RT14    => 0xC0,
84 14 hasw
    FCR_RT16    => 0x40,
85
    FCR_RT32    => 0x80,
86
    FCR_RT56    => 0xC0,
87 2 hasw
    LCR_WLS5    => 0x00,
88
    LCR_WLS6    => 0x01,
89
    LCR_WLS7    => 0x02,
90
    LCR_WLS8    => 0x03,
91
    LCR_STB     => 0x04,
92
    LCR_PEN     => 0x08,
93
    LCR_EPS     => 0x10,
94
    LCR_SP      => 0x20,
95
    LCR_BC      => 0x40,
96
    LCR_DLAB    => 0x80,
97
    MCR_DTR     => 0x01,
98
    MCR_RTS     => 0x02,
99
    MCR_OUT1    => 0x04,
100
    MCR_OUT2    => 0x08,
101
    MCR_LOOP    => 0x10,
102
    MCR_AFE     => 0x20,
103
    LSR_DR      => 0x01,
104
    LSR_OE      => 0x02,
105
    LSR_PE      => 0x04,
106
    LSR_FE      => 0x08,
107
    LSR_BI      => 0x10,
108
    LSR_THRE    => 0x20,
109
    LSR_TEMT    => 0x40,
110
    LSR_RXFE    => 0x80,
111
    MSR_DCTS    => 0x01,
112
    MSR_DDSR    => 0x02,
113
    MSR_TERI    => 0x04,
114
    MSR_DDCD    => 0x08,
115
    MSR_CTS     => 0x10,
116
    MSR_DSR     => 0x20,
117
    MSR_RI      => 0x40,
118
    MSR_DCD     => 0x80,
119
};
120
 
121
# Baudrate generator clock input period
122
use constant BAUDGENCLK => 1.8432e6;
123
# Current DLM/DLL register
124
my $divisor = 0x0000;
125
 
126
# Shadow registers with default values after reset
127
my $RBR = 0x00;
128
my $IER = 0x00;
129
my $IIR = IIR_IP;
130
my $FCR = 0x00;
131
my $LCR = 0x00;
132
my $MCR = 0x00;
133
my $LSR = LSR_THRE | LSR_TEMT;
134
#my $MSR = 0x00;
135
my $MSR = 0x0F;
136
my $SCR = 0x00;
137
 
138
 
139
# De-assert reset (if available)
140
waitcycle (10);
141
print ("#SET 0 1 1 1 1\n");
142
 
143
if (INITREGS) {
144
    logmessage ("UART: Initializing...");
145
    uart_write (IER, $IER);
146
    uart_write (FCR, $FCR);
147
    uart_write (LCR, $LCR);
148
    uart_write (MCR, $MCR);
149
    uart_write (SCR, $SCR);
150
}
151
 
152
logmessage ("UART: Checking registers after reset...");
153
uart_read (RBR, $RBR);
154
uart_read (RBR, $RBR);
155
uart_read (IER, $IER);
156
uart_read (IIR, $IIR);
157
uart_read (LCR, $LCR);
158
uart_read (MCR, $MCR);
159
uart_read (LSR, $LSR);
160
uart_read (MSR, $MSR);
161
uart_read (SCR, $SCR);
162
 
163
#logmessage ("UART: Checking SCR write/read...");
164
#for (my $i = 0; $i <= 0x10; $i++) {
165
#    uart_write (SCR, $i);
166
#    uart_read (SCR, $i);
167
#}
168
 
169
if (LOCAL_LOOP) {
170
    logmessage ("UART: Enabling local LOOP mode...");
171
    uart_write (MCR, MCR_LOOP);
172
    uart_read (MCR, MCR_LOOP);
173
}
174
 
175
uart_setbaudrate (115200);
176
 
177
logmessage ("UART: Enabling interrupts...");
178
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
179
uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
180
uart_read  (IIR, IIR_THRI);
181
uart_read  (IIR, IIR_NONE);
182
 
183
sub uart_check_control_lines ()
184
{
185
    logmessage ("UART: Checking control lines...");
186
    uart_write (MCR, $MCR | MCR_DTR);
187
    uart_read  (MCR, $MCR);
188
    uart_read  (IIR, IIR_MSRI);
189
    uart_read  (MSR, MSR_DSR | MSR_DDSR);
190
    uart_read  (MSR, MSR_DSR);
191
    uart_read  (IIR, IIR_NONE);
192
    uart_write (MCR, $MCR | MCR_RTS);
193
    uart_read  (MCR, $MCR);
194
    uart_read  (IIR, IIR_MSRI);
195
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
196
    uart_read  (MSR, MSR_CTS | MSR_DSR);
197
    uart_read  (IIR, IIR_NONE);
198
    uart_write (MCR, $MCR | MCR_OUT1);
199
    uart_read  (MCR, $MCR);
200 14 hasw
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_RI);
201
    uart_read  (IIR, IIR_NONE);
202 2 hasw
    uart_write (MCR, $MCR & ~MCR_OUT1);
203
    uart_read  (MCR, $MCR);
204
    uart_read  (IIR, IIR_MSRI);
205
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
206
    uart_read  (IIR, IIR_NONE);
207
    uart_read  (MSR, MSR_CTS | MSR_DSR);
208
    uart_write (MCR, $MCR | MCR_OUT2);
209
    uart_read  (MCR, $MCR);
210
    uart_read  (IIR, IIR_MSRI);
211
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
212
    uart_read  (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
213
    uart_read  (IIR, IIR_NONE);
214
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
215
    uart_read  (MCR, $MCR);
216
    uart_read  (IIR, IIR_MSRI);
217
    uart_read  (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
218
    uart_read  (IIR, IIR_NONE);
219
}
220
 
221
sub uart_check_interrupt_control ()
222
{
223
    logmessage ("UART: Checking interrupt priority control...");
224
    uart_write (MCR, $MCR | MCR_DTR);
225
    uart_write (MCR, $MCR & ~MCR_DTR);
226
    uart_write (THR, 0x12);
227
    uart_wait (1);
228
    uart_write (LCR, $LCR | LCR_BC);
229
    uart_wait (1);
230
    uart_write (LCR, $LCR & ~LCR_BC);
231
    uart_read  (IIR, IIR_RLSI);
232
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
233
    uart_read  (IIR, IIR_RDAI);
234
    uart_read  (IIR, IIR_RDAI);
235
    uart_rrbr  (0x00);
236
    uart_write (THR, 0x34);
237
    uart_wait (1);
238
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
239
    uart_write (THR, 0x56);
240
    uart_read  (IIR, IIR_RDAI);
241
    uart_wait (1);
242
    uart_read  (IIR, IIR_RLSI);
243
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
244
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
245
    uart_read  (IIR, IIR_RDAI);
246
    uart_rrbr  (0x56);
247
    uart_read  (IIR, IIR_THRI);
248
    uart_read  (IIR, IIR_MSRI);
249
    uart_read  (IIR, IIR_MSRI);
250
    uart_read  (MSR, MSR_DDSR);
251
    uart_read  (IIR, IIR_NONE);
252
    uart_write (THR, 0x78);
253
    uart_wait (1);
254
    uart_read  (IIR, IIR_RDAI);
255
    uart_rrbr  (0x78);
256
    uart_read  (IIR, IIR_THRI);
257
    uart_read  (IIR, IIR_NONE);
258
}
259
 
260
sub uart_check_default ()
261
{
262
    for (my $mode = 0; $mode < 0x40; $mode++) {
263
        logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
264
        uart_write (LCR, $mode);
265
 
266
        logmessage ("UART: Transmission test single byte (FIFO disabled)");
267
        uart_wait (1);
268
        uart_write (THR, 0x55);
269
        uart_wait (1);
270
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
271
        uart_read  (IIR, IIR_RDAI);
272
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
273
        uart_rrbr  (0x55);
274
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
275
        uart_read  (IIR, IIR_THRI);
276
        uart_read  (IIR, IIR_NONE);
277
 
278
        logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
279
        for (my $i = 0; $i < 10; $i++) {
280
            uart_read  (IIR, IIR_NONE);
281
            uart_write (THR, $i);
282
            uart_wait (1);
283
            uart_read  (IIR, IIR_RDAI);
284
            uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
285
            uart_rrbr  ($i);
286
            uart_read  (IIR, IIR_THRI);
287
            uart_read  (LSR, LSR_THRE | LSR_TEMT);
288
        }
289
 
290
        #logmessage ("UART: Transmission test loop (FIFO disabled)");
291
        #for (my $i = 0; $i < 1000; $i++) {
292
        #    if (!($i % 100)) {
293
        #        logmessage ("UART:   Loop " . $i);
294
        #    }
295
        #    uart_write (THR, $i);
296
        #    uart_read  (IIR, IIR_THRI);
297
        #    uart_wait (1);
298
        #    uart_read  (IIR, IIR_RDAI);
299
        #    uart_rrbr  ($i);
300
        #    uart_read  (IIR, IIR_NONE);
301
        #}
302
 
303
        logmessage ("UART: Transmission test overflow (FIFO disabled)");
304
        uart_write (THR, 0x55);
305
        uart_wait (1);
306
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
307
        uart_read  (IIR, IIR_RDAI);
308
        uart_write (THR, 0xAA);
309
        uart_wait (1);
310
        uart_read  (IIR, IIR_RLSI);
311
        uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
312
        uart_read  (IIR, IIR_RDAI);
313
        uart_wait (1);
314
        uart_read  (IIR, IIR_RDAI);
315
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
316
        uart_rrbr  (0xAA);
317
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
318
        uart_read  (IIR, IIR_THRI);
319
        uart_read  (IIR, IIR_NONE);
320
 
321
        logmessage ("UART: Break control test");
322
        uart_write (LCR, $LCR | LCR_BC);
323
        uart_read  (LCR, $LCR);
324
        uart_wait (2);
325
        uart_read  (IIR, IIR_RLSI);
326
        if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
327
            uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
328
        } else {
329
            uart_read (LSR, LSR_DR |          LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
330
        }
331
        uart_read  (IIR, IIR_RDAI);
332
        uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
333
        uart_read  (RBR, 0x00);
334
        uart_read  (IIR, IIR_NONE);
335
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
336
        uart_write (LCR, $LCR & ~LCR_BC);
337
        uart_read  (LCR, $LCR);
338
        uart_wait (2);
339
        uart_read  (LSR, LSR_THRE | LSR_TEMT);
340
        uart_read  (IIR, IIR_NONE);
341
    }
342
 
343
    uart_write (LCR, 0x00);
344
}
345
 
346
sub uart_check_fifo ()
347
{
348
    logmessage ("UART: Enabling FIFO...");
349
    uart_write (FCR, FCR_FE);
350
    uart_read  (IIR, IIR_THRI | IIR_FE);
351
    uart_read  (IIR, IIR_NONE | IIR_FE);
352
 
353
    logmessage ("UART: Testing FIFO trigger level 1 byte...");
354
    uart_write (FCR, FCR_FE | FCR_RT1);
355
    uart_send  (1);
356
    uart_wait  (4);
357
    uart_read  (IIR, IIR_CTOI | IIR_FE);
358
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
359
    uart_rrbr  (0x00);
360
    uart_read  (IIR, IIR_THRI | IIR_FE);
361
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
362
    uart_read  (IIR, IIR_NONE | IIR_FE);
363
 
364
    logmessage ("UART: Testing FIFO trigger level 4 byte...");
365
    uart_write (FCR, FCR_FE | FCR_RT4);
366
    uart_send  (3);
367
    uart_wait  (7);
368
    uart_read  (IIR, IIR_CTOI | IIR_FE);
369
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
370
    uart_rrbr  (0x00);
371
    uart_send  (2);
372
    uart_wait  (6);
373
    uart_read  (IIR, IIR_CTOI | IIR_FE);
374
    uart_wait  (2);
375
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
376
    uart_rrbr  (1);
377
    uart_read  (IIR, IIR_THRI | IIR_FE);
378
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
379
    uart_read  (IIR, IIR_NONE | IIR_FE);
380
    uart_rrbr  (2);
381
    uart_rrbr  (0);
382
    uart_rrbr  (1);
383
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
384
    uart_read  (IIR, IIR_NONE | IIR_FE);
385
 
386
    logmessage ("UART: Testing FIFO trigger level 8 byte...");
387
    uart_write (FCR, FCR_FE | FCR_RT8);
388
    uart_send  (7);
389
    uart_read  (IIR, IIR_NONE | IIR_FE);
390
    uart_wait  (11);
391
    uart_read  (IIR, IIR_CTOI | IIR_FE);
392
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
393
    uart_rrbr  (0x00);
394
    uart_read  (IIR, IIR_THRI | IIR_FE);
395
    uart_read  (IIR, IIR_NONE | IIR_FE);
396
    uart_send  (2);
397
    uart_wait  (6);
398
    uart_read  (IIR, IIR_CTOI | IIR_FE);
399
    uart_wait  (2);
400
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
401
    uart_rrbr  (1);
402
    uart_read  (IIR, IIR_THRI | IIR_FE);
403
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
404
    uart_read  (IIR, IIR_NONE | IIR_FE);
405
    uart_rrbr  (2);
406
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
407
    uart_rrbr  (3);
408
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
409
    uart_rrbr  (4);
410
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
411
    uart_rrbr  (5);
412
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
413
    uart_rrbr  (6);
414
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
415
    uart_rrbr  (0);
416
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
417
    uart_rrbr  (1);
418
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
419
    uart_read  (IIR, IIR_NONE | IIR_FE);
420
 
421
    logmessage ("UART: Testing FIFO trigger level 14 byte...");
422
    uart_write (FCR, FCR_FE | FCR_RT14);
423
    uart_send  (13);
424
    uart_wait  (17);
425
    uart_read  (IIR, IIR_CTOI | IIR_FE);
426
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
427
    uart_rrbr  (0x00);
428
    uart_read  (IIR, IIR_THRI | IIR_FE);
429
    uart_read  (IIR, IIR_NONE | IIR_FE);
430
    uart_send  (2);
431
    uart_wait  (6);
432
    uart_read  (IIR, IIR_CTOI | IIR_FE);
433
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
434
    uart_rrbr  (1);
435
    uart_read  (IIR, IIR_THRI | IIR_FE);
436
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
437
    uart_read  (IIR, IIR_NONE | IIR_FE);
438
    uart_rrbr  (2);
439
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
440
    uart_rrbr  (3);
441
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
442
    uart_rrbr  (4);
443
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
444
    uart_rrbr  (5);
445
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
446
    uart_rrbr  (6);
447
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
448
    uart_rrbr  (7);
449
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
450
    uart_rrbr  (8);
451
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
452
    uart_rrbr  (9);
453
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
454
    uart_rrbr  (10);
455
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
456
    uart_rrbr  (11);
457
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
458
    uart_rrbr  (12);
459
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
460
    uart_rrbr  (0);
461
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
462
    uart_rrbr  (1);
463
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
464
    uart_read  (IIR, IIR_NONE | IIR_FE);
465
 
466
    logmessage ("UART: Testing FIFO overrun...");
467
    uart_write (FCR, FCR_FE | FCR_RT1);
468
    uart_send  (17);
469
    uart_wait  (17);
470
    uart_read  (IIR, IIR_RLSI | IIR_FE);
471
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
472
    uart_read  (IIR, IIR_CTOI | IIR_FE);
473
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
474
    uart_rrbr  (0x00);
475
    uart_read  (IIR, IIR_RDAI | IIR_FE);
476
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
477
    uart_write (FCR, FCR_FE | FCR_RXFR);
478 12 hasw
    uart_wait  (1);
479 2 hasw
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
480
    uart_read  (IIR, IIR_THRI | IIR_FE);
481
    uart_read  (IIR, IIR_NONE | IIR_FE);
482
 
483
    logmessage ("UART: Miscellaneous FIFO tests...");
484
    uart_write (LCR, 0x03);
485
    uart_write (IER, IER_ERBI);
486
    uart_read  (IIR, IIR_NONE | IIR_FE);
487
    uart_write (FCR, FCR_FE | FCR_RT14);
488
    uart_read  (IIR, IIR_NONE | IIR_FE);
489
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
490
    logmessage ("UART: Sending 8 words");
491
    uart_send  (8);
492
    uart_read  (IIR, IIR_NONE | IIR_FE);
493
    uart_wait  (12);
494
    uart_read  (IIR, IIR_CTOI | IIR_FE);
495
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
496
    logmessage ("UART: Receiving 8 words");
497
    uart_recv  (8, 0);
498
    uart_read  (IIR, IIR_NONE | IIR_FE);
499
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
500
    logmessage ("UART: Sending 16 words");
501
    uart_send  (16);
502
    uart_wait  (4);
503
    logmessage ("UART: Receiving 4 words");
504
    uart_recv  (4, 0);
505
    logmessage ("UART: Sending 4 words");
506
    uart_send  (4);
507
    uart_wait  (12);
508
    logmessage ("UART: Receiving 12 words");
509
    uart_recv  (12, 4);
510
    uart_wait  (8);
511
    logmessage ("UART: Receiving 2 words");
512
    uart_recv  (2, 0);
513
    uart_read  (IIR, IIR_NONE | IIR_FE);
514
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
515
    logmessage ("UART: Sending 40 words");
516
    uart_send  (40);
517
    uart_wait  (4);
518
    uart_read  (LSR, LSR_DR);
519
    uart_wait  (20);
520
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
521
    uart_read  (IIR, IIR_CTOI | IIR_FE);
522
    logmessage ("UART: Receiving 3 words");
523
    uart_recv  (2, 2);
524
    uart_rrbr  (0x00);
525
    uart_read  (IIR, IIR_NONE | IIR_FE);
526
    logmessage ("UART: Receiving 13 words");
527
    uart_recv  (13, 1);
528
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
529
    uart_read  (IIR, IIR_NONE | IIR_FE);
530
 
531
    logmessage ("UART: Testing FIFO error counter...");
532
    uart_write (IER, IER_ERBI | IER_ELSI);
533
    logmessage ("UART: Sending 2 words");
534
    uart_send  (2);
535
    uart_wait  (2);
536
    logmessage ("UART: Sending break");
537
    uart_write (LCR, $LCR | LCR_BC);
538
    uart_wait  (1);
539
    uart_write (LCR, $LCR & ~LCR_BC);
540
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
541
    logmessage ("UART: Sending 4 words");
542
    uart_send  (4);
543
    uart_wait  (4);
544
    logmessage ("UART: Sending break");
545
    uart_write (LCR, $LCR | LCR_BC);
546
    uart_wait  (1);
547
    uart_write (LCR, $LCR & ~LCR_BC);
548
    logmessage ("UART: Sending 2 words");
549
    uart_send  (2);
550
    uart_wait  (6);
551
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
552
    uart_read  (IIR, IIR_CTOI | IIR_FE);
553
    logmessage ("UART: Reading 2 words");
554
    uart_rrbr  (0x00);
555
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
556
    uart_rrbr  (0x01);
557 12 hasw
    uart_wait  (1);
558 2 hasw
    uart_read  (IIR, IIR_RLSI | IIR_FE);
559
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
560
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
561
    logmessage ("UART: Reading break word");
562
    uart_rrbr  (0x00);
563
    uart_read  (IIR, IIR_NONE | IIR_FE);
564
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
565
    logmessage ("UART: Reading 4 words");
566
    uart_rrbr  (0x00);
567
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
568
    uart_rrbr  (0x01);
569
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
570
    uart_rrbr  (0x02);
571
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
572
    uart_rrbr  (0x03);
573 12 hasw
    uart_wait  (1);
574 2 hasw
    uart_read  (IIR, IIR_RLSI | IIR_FE);
575
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
576
    uart_read  (IIR, IIR_NONE | IIR_FE);
577
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
578
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
579
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
580
    logmessage ("UART: Reading break word");
581
    uart_rrbr  (0x00);
582
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
583
    uart_rrbr  (0x00);
584
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
585
    uart_rrbr  (0x01);
586
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
587
 
588
    logmessage ("UART: Sending break");
589
    uart_write (LCR, $LCR | LCR_BC);
590
    uart_wait  (1);
591
    uart_write (LCR, $LCR & ~LCR_BC);
592
    uart_read  (IIR, IIR_RLSI | IIR_FE);
593
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
594
    uart_read  (IIR, IIR_NONE | IIR_FE);
595
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
596
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
597
    logmessage ("UART: Reading break word");
598
    uart_rrbr  (0x00);
599
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
600
 
601
    logmessage ("UART: FIFO test end");
602
}
603
 
604 14 hasw
sub uart_check_fifo64 ()
605
{
606
    logmessage ("UART: Testing FIFO in 64 byte mode...");
607
    uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
608
    uart_write (FCR, FCR_F64E | FCR_FE | FCR_RXFR | FCR_TXFR);
609
    uart_read  (IIR, IIR_THRI | IIR_FE);
610
    uart_write (LCR, $LCR | LCR_DLAB);
611
    uart_write (FCR, FCR_F64E | FCR_FE);
612
    uart_write (LCR, $LCR & ~LCR_DLAB);
613
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
614
 
615
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
616
    logmessage ("UART: Testing FIFO trigger level 1 byte...");
617
    uart_write (FCR, FCR_FE | FCR_RT1);
618
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
619
    uart_send  (1);
620
    uart_wait  (4);
621
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
622
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
623
    uart_rrbr  (0x00);
624
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
625
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
626
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
627
 
628
    logmessage ("UART: Testing FIFO trigger level 16 byte...");
629
    uart_write (FCR, FCR_FE | FCR_RT16);
630
    uart_send  (15);
631
    uart_wait  (15);
632
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
633
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
634
    uart_rrbr  (0x00);
635
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
636
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
637
    uart_send  (3);
638
    uart_wait  (3);
639
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
640
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
641
    uart_rrbr  (0x01);
642
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
643
    uart_rrbr  (0x02);
644
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
645
    uart_recv  (12, 3);
646
    uart_recv  (3);
647
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
648
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
649
 
650
    logmessage ("UART: Testing FIFO trigger level 32 byte...");
651
    uart_write (FCR, FCR_FE | FCR_RT32);
652
    uart_send  (31);
653
    uart_wait  (31);
654
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
655
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
656
    uart_rrbr  (0x00);
657
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
658
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
659
    uart_send  (3);
660
    uart_wait  (3);
661
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
662
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
663
    uart_rrbr  (0x01);
664
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
665
    uart_rrbr  (0x02);
666
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
667
    uart_recv  (28, 3);
668
    uart_recv  (3);
669
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
670
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
671
 
672
    logmessage ("UART: Testing FIFO trigger level 56 byte...");
673
    uart_write (FCR, FCR_FE | FCR_RT56);
674
    uart_send  (55);
675
    uart_wait  (55);
676
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
677
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
678
    uart_rrbr  (0x00);
679
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
680
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
681
    uart_send  (3);
682
    uart_wait  (3);
683
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
684
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
685
    uart_rrbr  (0x01);
686
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
687
    uart_rrbr  (0x02);
688
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
689
    uart_recv  (52, 3);
690
    uart_recv  (3);
691
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
692
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
693
 
694
    uart_write (LCR, $LCR | LCR_DLAB);
695
    uart_write (FCR, $FCR & ~FCR_F64E);
696
    uart_write (LCR, $LCR & ~LCR_DLAB);
697
    uart_read  (IIR, IIR_NONE | IIR_FE);
698
 
699
    logmessage ("UART: FIFO64 test end");
700
}
701
 
702 12 hasw
sub uart_check_afc ()
703
{
704
    logmessage ("UART: Automatic flow control test");
705
    uart_write (LCR, LCR_WLS8);
706
    uart_read  (LCR, LCR_WLS8);
707
    uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
708
    uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
709
    logmessage ("UART: Setting FIFO trigger level to 4 bytes");
710
    uart_write (FCR, FCR_FE | FCR_RT4);
711
    uart_read  (IIR, IIR_THRI | IIR_FE);
712
    uart_read  (IIR, IIR_NONE | IIR_FE);
713
    logmessage ("UART: Enabling Auto-CTS");
714
    uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
715
    uart_read  (MSR, 0);
716
    uart_read  (IIR, IIR_NONE | IIR_FE);
717
    logmessage ("UART: Send 3 words");
718
    uart_send  (3);
719
    uart_wait  (6);
720
    logmessage ("UART: Expecting no data was sent");
721
    uart_read  (IIR, IIR_NONE | IIR_FE);
722
    uart_read  (LSR, 0);
723
    logmessage ("UART: Enabling Auto-RTS");
724
    uart_write (MCR, $MCR | MCR_RTS);
725
    logmessage ("UART: Check if CTS is enabled");
726
    uart_read  (IIR, IIR_NONE | IIR_FE);
727
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
728
    uart_wait  (8);
729
    uart_read  (IIR, IIR_CTOI | IIR_FE);
730
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
731
    logmessage ("UART: Check if CTS is enabled");
732
    uart_read  (MSR, MSR_CTS);
733
    logmessage ("UART: Send 1 word");
734
    uart_send  (1);
735
    uart_wait  (2);
736
    logmessage ("UART: Check if CTS is disabled");
737
    uart_read  (MSR, MSR_DCTS);
738
    logmessage ("UART: Check LSR");
739
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
740
    uart_read  (IIR, IIR_CTOI | IIR_FE);
741
    logmessage ("UART: Receive 3 words");
742
    uart_recv  (3);
743
    logmessage ("UART: Check if CTS is disabled");
744
    uart_read  (MSR, 0);
745
    logmessage ("UART: Receive 1 word");
746
    uart_recv  (1);
747
    logmessage ("UART: Check LSR");
748
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
749
    uart_read  (IIR, IIR_THRI | IIR_FE);
750
    uart_read  (IIR, IIR_NONE | IIR_FE);
751
    logmessage ("UART: Check if CTS is enabled again");
752
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
753
    logmessage ("UART: Send 6 words");
754
    uart_send  (5);
755
    uart_send  (1);
756
    uart_wait  (4);
757
    logmessage ("UART: Check if CTS is disabled");
758
    uart_read  (MSR, MSR_DCTS);
759
    logmessage ("UART: Check LSR");
760
    uart_read  (LSR, LSR_DR);
761
    uart_wait  (1);
762
    logmessage ("UART: Receive 5 words");
763
    uart_recv  (5);
764
    uart_read  (IIR, IIR_NONE | IIR_FE);
765
    uart_wait  (2);
766
    logmessage ("UART: Check LSR");
767
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
768
    logmessage ("UART: Check if CTS is enabled again");
769
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
770
    logmessage ("UART: Receive 1 words");
771
    uart_recv  (1);
772
    logmessage ("UART: Check LSR");
773
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
774
    uart_read  (IIR, IIR_THRI | IIR_FE);
775
    uart_read  (IIR, IIR_NONE | IIR_FE);
776
    logmessage ("UART: Check if CTS is enabled");
777
    uart_read  (MSR, MSR_CTS);
778
    logmessage ("UART: Disable Automatic flow control");
779
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
780
    uart_read  (MSR, MSR_DCTS);
781
    uart_read  (IIR, IIR_NONE | IIR_FE);
782
    uart_read  (MCR, $MCR);
783
    logmessage ("UART: Automatic flow control test finished");
784
}
785
 
786 14 hasw
if (TEST_CONTROL) {
787
    uart_check_control_lines ();
788
}
789
if (TEST_INTERRUPT) {
790
    uart_check_interrupt_control ();
791
}
792
if (TEST_DEFAULT) {
793
    uart_check_default ();
794
}
795
if (TEST_FIFO) {
796
    uart_check_fifo ();
797
}
798
if (TEST_FIFO64) {
799
    uart_check_fifo64 ();
800
}
801 12 hasw
if (TEST_AFC) {
802
    uart_check_afc ();
803
}
804 2 hasw
 
805
##################################################################
806
# End main process
807
##################################################################
808
 
809
 
810
 
811
##################################################################
812
# Sub functions
813
##################################################################
814
 
815
# Convert number to binary string
816
sub num2binary($$)
817
{
818
  my($num) = @_;
819
  my $binary = $num ? '' : '0';    # in case $num is zero
820
  my $len = $_[1];
821
  my $result;
822
 
823
  while ($num) {
824
    $binary .= $num & 1 ? 1 : 0;  # do the LSB
825
    $num >>= 1;                   # on to the next bit
826
  }
827
 
828
  $result = scalar reverse $binary;
829
  while (length($result)<$len) {
830
    $result = "0".$result;
831
  }
832
 
833
  return $result;
834
}
835
 
836
 
837
# Insert wait cycles
838
sub waitcycle($)
839
{
840
    printf ("#WAIT %d\n", $_[0]);
841
    #printf ("DE %d\n", $_[0]+5);
842
}
843
 
844
# Log message
845
sub logmessage($)
846
{
847
    print "#LOG $_[0]\n";
848
    #print "LO $_[0]\n";
849
}
850
 
851
# Read from UART
852
sub uart_read($$)
853
{
854
    printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
855
    #printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
856
}
857
 
858
# Filter read from RBR (mask word length)
859
sub uart_rrbr($)
860
{
861
    my $wls  = $LCR & 0x03;
862
    my $data = $_[0];
863
 
864
    if ($wls == 0x00) { $data &= 0x1F; }
865
    if ($wls == 0x01) { $data &= 0x3F; }
866
    if ($wls == 0x02) { $data &= 0x7F; }
867
    uart_read (RBR, $data);
868
}
869
 
870
# Write to UART
871
sub uart_write($$)
872
{
873
    # Shadow register writes to local copy
874
    SWITCH: {
875
        if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
876
        if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
877
        if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
878
        if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
879
        if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
880
        if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
881
    }
882
 
883
    printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
884
    #printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
885
}
886
 
887
# Set UART baudrate
888
sub uart_setbaudrate($)
889
{
890
    logmessage ("UART: Setting baudrate to $_[0]");
891
    $divisor = BAUDGENCLK / (16 * $_[0]);
892
    uart_write (LCR, $LCR | LCR_DLAB);
893
    uart_write (DLL, $divisor);
894
    uart_write (DLM, $divisor >> 8);
895
    uart_read  (LCR, $LCR);
896
    uart_read  (DLL, $divisor);
897
    uart_read  (DLM, $divisor >> 8);
898
    uart_write (LCR, $LCR & ~LCR_DLAB);
899
    uart_read  (LCR, $LCR);
900
}
901
 
902
# Wait until n words are transmitted/received
903
sub uart_wait ($)
904
{
905
    my $steps  = 1;                         # Start bit
906
       $steps += 5 + ($LCR & 0x03);         # Data
907
       $steps += $LCR & LCR_PEN ? 1 : 0;    # Parity
908
       $steps += $LCR & LCR_STB ? 2 : 1;    # Stop bit
909
       $steps += 2;                         # Extra delay
910
 
911
    my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
912
    waitcycle ($txtime/CYCLE);
913
}
914
 
915
# Send n bytes
916
sub uart_send ($)
917
{
918
    for (my $i = 0; $i < $_[0]; $i++) {
919
        uart_write (THR, $i);
920
        if (!($FCR & FCR_FE)) {
921
            uart_wait  (1);
922
        }
923
    }
924
}
925
 
926
# Receive n bytes
927
sub uart_recv ($$)
928
{
929
    for (my $i = 0; $i < $_[0]; $i++) {
930
        uart_rrbr ($i + $_[1]);
931
    }
932
}
933
 
934 25 hasw
# Send serial data from external UART
935
sub uart_eu_send($)
936
{
937
    printf ("#EUS  8 %d\n", $_[0]);
938
}
939
 

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