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HanySalah |
//-----------------------------------------------------------------------------
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//
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// UART2BUS VERIFICATION
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//
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//-----------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : ANALYSIS
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//-----------------------------------------------------------------------------
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// TITLE : UART ANALYSIS
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// DESCRIPTION: This
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//-----------------------------------------------------------------------------
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// LOG DETAILS
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 22012016 FILE CREATION
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//-----------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// CREATOR'S PERMISSION
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//-----------------------------------------------------------------------------
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class uart_scoreboard extends uvm_scoreboard;
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uvm_tlm_analysis_fifo #(uart_transaction) mon_fifo;
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uvm_analysis_export #(uart_transaction) scbd_mon;
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uvm_tlm_analysis_fifo #(uart_transaction) drv_fifo;
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uvm_analysis_export #(uart_transaction) scbd_drv;
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uart_transaction frm_drv,frm_drv_tmp;
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uart_transaction frm_mon,frm_mon_tmp;
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`uvm_component_utils(uart_scoreboard)
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function new (string name , uvm_component parent);
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super.new(name,parent);
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endfunction:new
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extern function void build_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern task run_phase (uvm_phase phase);
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endclass:uart_scoreboard
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function void uart_scoreboard::build_phase (uvm_phase phase);
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super.build_phase(phase);
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frm_drv = uart_transaction::type_id::create("frm_drv");
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frm_drv_tmp = uart_transaction::type_id::create("frm_drv_tmp");
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frm_mon = uart_transaction::type_id::create("frm_mon");
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frm_mon_tmp = uart_transaction::type_id::create("frm_mon_tmp");
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mon_fifo = new ("mon_fifo",this);
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scbd_mon = new ("scbd_mon",this);
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drv_fifo = new ("drv_fifo",this);
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scbd_drv = new ("scbd_drv",this);
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endfunction:build_phase
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function void uart_scoreboard::connect_phase (uvm_phase phase);
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scbd_mon.connect(mon_fifo.analysis_export);
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scbd_drv.connect(drv_fifo.analysis_export);
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endfunction:connect_phase
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task uart_scoreboard::run_phase (uvm_phase phase);
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int iteration;
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iteration = 0;
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forever
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begin
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iteration++;
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drv_fifo.get(frm_drv_tmp);
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$cast(frm_drv,frm_drv_tmp.clone());
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mon_fifo.get(frm_mon_tmp);
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$cast(frm_mon,frm_mon_tmp.clone());
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if (frm_drv._mode != frm_mon._mode)
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begin
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`uvm_fatal("Testbench Bug",$sformatf("Modes aren't similiar .. @time=%0t, It was requested to use %p mode and the applied mode is %p ",$time,frm_drv._mode,frm_mon._mode))
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end
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else
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begin
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case (frm_drv._mode)
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text:
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begin
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if(frm_drv._command != frm_mon._command)
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begin
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`uvm_fatal("Testbench Bug",$sformatf("Commands aren't identical .. @time=%0t, It was requested to drive %p command and the applied command is %p ",$time,frm_drv._command,frm_mon._command))
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end
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else
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begin
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case(frm_drv._command)
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read:
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begin
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if (frm_drv._data != frm_mon._data)
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begin
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`uvm_error("Failed Read Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut reply with the data %p",$time,frm_drv._data,frm_mon._data))
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end
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else if((frm_drv._data == frm_mon._data) &&
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(frm_drv.address == frm_mon.address) &&
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(frm_drv._spacetype1 == frm_mon._spacetype1) &&
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(frm_drv._eoltype == frm_mon._eoltype) &&
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(frm_drv._chartype == frm_mon._chartype))
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begin
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`uvm_info("Passed Read Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to read from the address %h and dut reply with the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
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frm_drv._eoltype),UVM_NONE)
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end
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else
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begin
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`uvm_error("Failed Read Text Mode",$sformatf("@time=%0t .. It is Requested to request to read data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
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frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
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end
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end
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write:
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begin
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if (frm_drv._data != frm_mon._data)
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begin
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`uvm_error("Failed Write Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut register the data %p",$time,frm_drv._data,frm_mon._data))
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end
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else if((frm_drv._data == frm_mon._data) &&
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(frm_drv.address == frm_mon.address) &&
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(frm_drv._spacetype1 == frm_mon._spacetype1) &&
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(frm_drv._eoltype == frm_mon._eoltype) &&
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(frm_drv._chartype == frm_mon._chartype))
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begin
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`uvm_info("Passed write Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to write to the address %h and dut register the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
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frm_drv._eoltype),UVM_NONE)
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end
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else
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begin
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`uvm_error("Failed write Text Mode",$sformatf("@time=%0t .. It is Requested to request to write data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
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frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
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end
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end
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default:
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begin
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`uvm_fatal("Testbench Bug",$sformatf("@time = %0t .. It isn't allowablt to drive %p command through text mode",$time,frm_drv._command))
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end
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endcase
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end
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end
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binary:
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begin
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end
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wrong_mode:
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begin
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end
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default:
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begin
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`uvm_fatal("Testbench Bug",$sformatf("Mode is undefined = %p",frm_drv._mode))
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end
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endcase
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end
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end
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endtask:run_phase
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