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[/] [udp_ipv4_for_10g_ethernet/] [trunk/] [src/] [hdl/] [crc/] [crc32_fast16_tab.vhd] - Blame information for rev 3

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1 3 DFC 
--
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-- crc_fast16_tab.vhd: A 32-bit CRC (IEEE) table for processing fixed 16 bits in parallel
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-- Copyright (C) 2011 CESNET
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-- Author(s): Lukas Kekely <xkekel00@stud.fit.vutbr.cz>
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in
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--    the documentation and/or other materials provided with the
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--    distribution.
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-- 3. Neither the name of the Company nor the names of its contributors
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--    may be used to endorse or promote products derived from this
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--    software without specific prior written permission.
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--
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-- This software is provided ``as is'', and any express or implied
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-- warranties, including, but not limited to, the implied warranties of
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-- merchantability and fitness for a particular purpose are disclaimed.
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-- In no event shall the company or contributors be liable for any
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-- direct, indirect, incidental, special, exemplary, or consequential
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-- damages (including, but not limited to, procurement of substitute
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-- goods or services; loss of use, data, or profits; or business
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-- interruption) however caused and on any theory of liability, whether
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-- in contract, strict liability, or tort (including negligence or
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-- otherwise) arising in any way out of the use of this software, even
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-- if advised of the possibility of such damage.
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--
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-- $Id$
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--
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-- TODO:
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--
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use WORK.math_pack.all;
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-- ----------------------------------------------------------------------------
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--                        Entity declaration
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-- ----------------------------------------------------------------------------
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entity crc32_fast16_tab is
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   port(
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      DI    : in  std_logic_vector(16-1 downto 0);
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      DO    : out std_logic_vector(31 downto 0)
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   );
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end entity crc32_fast16_tab;
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-- ----------------------------------------------------------------------------
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--                      Architecture declaration
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-- ----------------------------------------------------------------------------
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architecture arch of crc32_fast16_tab is
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begin
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-- 32-bit CRC equations processing 16 bits in parallel (VHDL code)
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-- Generator polynomial: 0x104C11DB7
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   DO(0) <= DI(6) XOR DI(7) XOR DI(0) XOR DI(4) XOR DI(10);
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   DO(1) <= DI(7) XOR DI(8) XOR DI(1) XOR DI(5) XOR DI(11);
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   DO(2) <= DI(8) XOR DI(9) XOR DI(2) XOR DI(6) XOR DI(12);
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   DO(3) <= DI(9) XOR DI(10) XOR DI(3) XOR DI(7) XOR DI(13);
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   DO(4) <= DI(10) XOR DI(11) XOR DI(4) XOR DI(8) XOR DI(14);
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   DO(5) <= DI(11) XOR DI(12) XOR DI(5) XOR DI(9) XOR DI(15);
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   DO(6) <= DI(0) XOR DI(12) XOR DI(4) XOR DI(7) XOR DI(13);
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   DO(7) <= DI(1) XOR DI(13) XOR DI(5) XOR DI(8) XOR DI(14);
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   DO(8) <= DI(0) XOR DI(2) XOR DI(14) XOR DI(6) XOR DI(9) XOR DI(15);
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   DO(9) <= DI(1) XOR DI(4) XOR DI(6) XOR DI(3) XOR DI(15);
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   DO(10) <= DI(2) XOR DI(5) XOR DI(6) XOR DI(10);
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   DO(11) <= DI(3) XOR DI(6) XOR DI(7) XOR DI(11);
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   DO(12) <= DI(4) XOR DI(7) XOR DI(8) XOR DI(0) XOR DI(12);
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   DO(13) <= DI(5) XOR DI(8) XOR DI(0) XOR DI(9) XOR DI(1) XOR DI(13);
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   DO(14) <= DI(6) XOR DI(9) XOR DI(1) XOR DI(10) XOR DI(2) XOR DI(14);
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   DO(15) <= DI(7) XOR DI(10) XOR DI(2) XOR DI(11) XOR DI(3) XOR DI(15);
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   DO(16) <= DI(7) XOR DI(8) XOR DI(10) XOR DI(11) XOR DI(3) XOR DI(0) XOR DI(6) XOR DI(12);
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   DO(17) <= DI(8) XOR DI(9) XOR DI(11) XOR DI(0) XOR DI(12) XOR DI(4) XOR DI(1) XOR DI(7) XOR DI(13);
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   DO(18) <= DI(9) XOR DI(10) XOR DI(12) XOR DI(1) XOR DI(13) XOR DI(5) XOR DI(2) XOR DI(8) XOR DI(14);
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   DO(19) <= DI(0) XOR DI(10) XOR DI(11) XOR DI(13) XOR DI(2) XOR DI(14) XOR DI(6) XOR DI(3) XOR DI(9) XOR DI(15);
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   DO(20) <= DI(1) XOR DI(11) XOR DI(0) XOR DI(12) XOR DI(14) XOR DI(6) XOR DI(3) XOR DI(15);
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   DO(21) <= DI(10) XOR DI(2) XOR DI(12) XOR DI(1) XOR DI(13) XOR DI(6) XOR DI(15);
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   DO(22) <= DI(6) XOR DI(10) XOR DI(11) XOR DI(3) XOR DI(13) XOR DI(4) XOR DI(2) XOR DI(14);
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   DO(23) <= DI(7) XOR DI(11) XOR DI(12) XOR DI(4) XOR DI(14) XOR DI(5) XOR DI(3) XOR DI(15);
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   DO(24) <= DI(8) XOR DI(10) XOR DI(0) XOR DI(12) XOR DI(7) XOR DI(13) XOR DI(5) XOR DI(15);
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   DO(25) <= DI(9) XOR DI(10) XOR DI(11) XOR DI(1) XOR DI(7) XOR DI(13) XOR DI(4) XOR DI(8) XOR DI(14);
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   DO(26) <= DI(10) XOR DI(11) XOR DI(12) XOR DI(2) XOR DI(8) XOR DI(14) XOR DI(5) XOR DI(9) XOR DI(15);
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   DO(27) <= DI(11) XOR DI(0) XOR DI(12) XOR DI(4) XOR DI(7) XOR DI(13) XOR DI(3) XOR DI(9) XOR DI(15);
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   DO(28) <= DI(0) XOR DI(6) XOR DI(12) XOR DI(1) XOR DI(7) XOR DI(13) XOR DI(5) XOR DI(8) XOR DI(14);
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   DO(29) <= DI(1) XOR DI(7) XOR DI(13) XOR DI(2) XOR DI(8) XOR DI(14) XOR DI(6) XOR DI(9) XOR DI(15);
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   DO(30) <= DI(4) XOR DI(2) XOR DI(8) XOR DI(14) XOR DI(6) XOR DI(3) XOR DI(9) XOR DI(15);
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   DO(31) <= DI(5) XOR DI(6) XOR DI(3) XOR DI(9) XOR DI(15);
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end architecture;

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