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DFC |
-------------------------------------------------------------------------------
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--
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-- (C) Copyright 2013 DFC Design, s.r.o., Brno, Czech Republic
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--
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-------------------------------------------------------------------------------
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-- This file is part of UDP/IPv4 for 10 G Ethernet core.
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--
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-- UDP/IPv4 for 10 G Ethernet core is free software: you can
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-- redistribute it and/or modify it under the terms of
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-- the GNU Lesser General Public License as published by the Free
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-- Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- UDP/IPv4 for 10 G Ethernet core is distributed in the hope that
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-- it will be useful, but WITHOUT ANY WARRANTY; without even
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-- the implied warranty of MERCHANTABILITY or FITNESS FOR A
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-- PARTICULAR PURPOSE. See the GNU Lesser General Public License
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-- for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with UDP/IPv4 for 10 G Ethernet core. If not,
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-- see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------
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--
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-- This core generates UDP/IPv4 Ethernet frames.
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-- It is supposed to be connected to XGMII like interface.
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-- UDP checksum is not used (set 0).
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-- IP fragmentation is not supported. User is responsible for keeping packet
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-- size under MTU.
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-- Core ensures minimal standard IPG 96 bits is transmitted between every
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-- two frames.
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-- No checks are performed on validity of IP and MAC addresses.
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-- ARP is not implemented - user must provide valid MAC & IP address pair.
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-- Broadcasts are supported setting destination MAC to ff:ff:ff:ff:ff:ff and
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-- IP to correct broadcast IP based on netmask or 255.255.255.255.
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--
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-- If BUSY signal is low, transmission starts when user asserts
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-- TX_EN signal. All inputs - MAC and IP addresses, UDP ports, data length -
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-- must be valid when TX_EN is asserted until BUSY goes high (so if BUSY is
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-- low for one cycle together with TX_EN only).
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--
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-- After preamble and all headers are transmitted DATA_REN is asserted high
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-- by the core to indicate that data transfer will begin. One cycle latency
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-- is assumed, so data must be valid (and are consumed) in cycle
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-- following the one DATA_REN is asserted.
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--
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-- User has to provide new word in each cycle. There is no flow control.
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--
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-- Exactly DATA_LEN bytes is captured on DATA_IN and sent as UDP payload.
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--
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-- All ports must be synchronized to TX_CLK which should be XGMII TX clock.
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-- It is normally 156.25 MHz.
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--
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity frame_gen is
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port (
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RESET : in std_logic; -- Async reset
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TX_EN : in std_logic := '1'; -- Transmitt enable
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BUSY : out std_logic;
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IDLE_IFG : out std_logic;
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--
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DATA_REN : out std_logic; -- Data read enable (1 cycle latency is assumed)
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DATA_IN : in std_logic_vector(63 downto 0); -- Data input
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DATA_LEN : in std_logic_vector(15 downto 0); -- Number of data bytes to be transferred (should be multiple of 8)
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-- ETH/IP/UDP Configuration
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SRC_MAC : in std_logic_vector(47 downto 0); --
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DST_MAC : in std_logic_vector(47 downto 0); --
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SRC_IP : in std_logic_vector(31 downto 0); --
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DST_IP : in std_logic_vector(31 downto 0); --
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SRC_PORT : in std_logic_vector(15 downto 0); --
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DST_PORT : in std_logic_vector(15 downto 0); --
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-- XGMII TX interface
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TX_CLK : in std_logic; -- XGMII TX clock input
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TXD : out std_logic_vector(63 downto 0); -- XGMII TX data, TX_CLK sync
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TXC : out std_logic_vector( 7 downto 0) -- XGMII TX command, TX_CLK sync
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);
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end frame_gen;
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architecture behavioral of frame_gen is
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constant C_SOP : std_logic_vector(7 downto 0) := X"FB";
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constant C_EOP : std_logic_vector(7 downto 0) := X"FD";
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type t_state is (IDLE,
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PREAMBLE, --
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MAC0, -- SRC_MAC(1:0) & DST_MAC
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MAC_IP0, -- SERVICES & IP_VER & TYPE & SRC_MAC(5:2) 2
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IP1, -- PROTO(0x11) & TTL(0x80) & FLGS_OFFSET & ID(zeros) & Length(hdr+data [bytes]) 64
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IP2, -- DST_IP & SRC_IP & CHKSUM 64
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IP3_UDP, -- UDP_LEN & UDP_DST_P & UDP_SRC_P & DST_IP
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UDP_DATA, -- Data & UDP_CHSUM
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DATA, -- Data
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DATA_LAST,
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EOP,
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IFG);
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signal fsm_state : t_state;
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signal sum : std_logic_vector(19 downto 0);
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signal data_cntr : std_logic_vector(15 downto 0);
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signal data_dly : std_logic_vector(15 downto 0);
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signal tx_d_i : std_logic_vector(63 downto 0) := (others => '0');
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signal tx_c_i : std_logic_vector( 7 downto 0) := (others => '0');
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signal txd_i_dly0 : std_logic_vector(63 downto 0) := (others => '0');
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signal txc_i_dly0 : std_logic_vector( 7 downto 0) := (others => '0');
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signal txd_i_dly1 : std_logic_vector(63 downto 0) := (others => '0');
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signal txc_i_dly1 : std_logic_vector( 7 downto 0) := (others => '0');
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signal txd_i_dly2 : std_logic_vector(63 downto 0) := (others => '0');
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signal txc_i_dly2 : std_logic_vector( 7 downto 0) := (others => '0');
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signal txd_i_dly3 : std_logic_vector(63 downto 0) := (others => '0');
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signal txc_i_dly3 : std_logic_vector( 7 downto 0) := (others => '0');
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signal crc_mask_dly0 : std_logic_vector( 2 downto 0);
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signal crc_mask_dly1 : std_logic_vector( 2 downto 0);
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signal crc_mask_dly2 : std_logic_vector( 2 downto 0);
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signal crc_mask_dly3 : std_logic_vector( 2 downto 0);
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signal crc_mask_dly4 : std_logic_vector( 2 downto 0);
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signal tx_d_i_vld : std_logic;
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signal crc32_i : std_logic_vector(31 downto 0);
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signal crc32 : std_logic_vector(31 downto 0);
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signal crc_dly : std_logic_vector(31 downto 0);
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signal crc_mask : std_logic_vector( 2 downto 0) := "000";
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signal crc_eop : std_logic;
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signal crc_vld : std_logic;
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signal crc_vld_dly : std_logic;
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signal src_mac_reg : std_logic_vector(47 downto 0);
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signal dst_mac_reg : std_logic_vector(47 downto 0);
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signal src_ip_reg : std_logic_vector(31 downto 0);
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signal dst_ip_reg : std_logic_vector(31 downto 0);
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signal src_port_reg : std_logic_vector(15 downto 0);
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signal dst_port_reg : std_logic_vector(15 downto 0);
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signal data_len_reg : std_logic_vector(DATA_LEN'range);
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begin
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FRAME_GEN_FSM: process(RESET, TX_CLK)
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variable chksum : std_logic_vector(15 downto 0);
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variable tmpsum : std_logic_vector(19 downto 0);
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begin
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if RESET = '1' then
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fsm_state <= IDLE;
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tx_d_i_vld <= '0';
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DATA_REN <= '0';
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elsif TX_CLK'event and TX_CLK = '1' then
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crc_eop <= '0';
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IDLE_IFG <= '0';
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case fsm_state is
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when IDLE =>
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tx_d_i <= X"0707070707070707";
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tx_c_i <= "11111111";
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crc_eop <= '0';
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crc_mask <= "000";
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BUSY <= '0';
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if TX_EN = '1' then
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BUSY <= '1';
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fsm_state <= PREAMBLE;
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src_mac_reg <= SRC_MAC;
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dst_mac_reg <= DST_MAC;
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src_ip_reg <= SRC_IP;
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dst_ip_reg <= DST_IP;
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src_port_reg <= SRC_PORT;
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dst_port_reg <= DST_PORT;
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data_len_reg <= DATA_LEN;
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end if;
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when PREAMBLE =>
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tx_d_i <= X"D5555555555555FB";
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tx_c_i <= "00000001";
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fsm_state <= MAC0;
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when MAC0 =>
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tx_d_i_vld <= '1';
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tx_d_i(47 downto 0) <= dst_mac_reg(7 downto 0) & dst_mac_reg(15 downto 8) & dst_mac_reg(23 downto 16) & dst_mac_reg(31 downto 24) & dst_mac_reg(39 downto 32) & dst_mac_reg(47 downto 40); -- DST MAC
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tx_d_i(63 downto 48) <= src_mac_reg(39 downto 32) & src_mac_reg(47 downto 40); -- src_mac_reg(5:4)
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tx_c_i <= "00000000";
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fsm_state <= MAC_IP0;
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when MAC_IP0 =>
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tx_d_i(31 downto 0) <= src_mac_reg(7 downto 0) & src_mac_reg(15 downto 8) & src_mac_reg(23 downto 16) & src_mac_reg(31 downto 24); -- src_mac_reg(3:0)
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tx_d_i(63 downto 32) <= X"0045" & X"0008"; -- SERVICES & IP_VER & ETH_TYPE
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tx_c_i <= "00000000";
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sum <= "0000" & X"4500";
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fsm_state <= IP1;
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when IP1 =>
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tmpsum := ("0000" & data_len_reg) + X"1C";
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tx_d_i(15 downto 0) <= tmpsum(7 downto 0) & tmpsum(15 downto 8); -- IP data length (ip_hdr+udp_hdr+data [bytes])
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tx_d_i(63 downto 16) <= X"118000000000"; -- PROTO(0x11) & TTL(0x80) & FLGS_OFFSET & ID(zeros)
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tx_c_i <= "00000000";
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sum <= sum + X"8011" + tmpsum(15 downto 0);
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fsm_state <= IP2;
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when IP2 =>
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tmpsum := sum + src_ip_reg(15 downto 0) + src_ip_reg(31 downto 16) + dst_ip_reg(15 downto 0) + dst_ip_reg(31 downto 16);
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chksum := tmpsum(19 downto 16) + tmpsum(15 downto 0);
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tx_d_i(15 downto 0) <= not chksum(7 downto 0) & not chksum(15 downto 8); -- IP header CHKSUM
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tx_d_i(47 downto 16) <= src_ip_reg(7 downto 0) & src_ip_reg(15 downto 8) & src_ip_reg(23 downto 16) & src_ip_reg(31 downto 24); -- src_ip_reg
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tx_d_i(63 downto 48) <= dst_ip_reg(23 downto 16) & dst_ip_reg(31 downto 24); -- Destination IP
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tx_c_i <= "00000000";
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DATA_REN <= '1'; -- Enable reading data
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fsm_state <= IP3_UDP;
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when IP3_UDP =>
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tmpsum := ("0000" & data_len_reg) + 8;
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tx_d_i(15 downto 0) <= dst_ip_reg(7 downto 0) & dst_ip_reg(15 downto 8); -- Destionation IP
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tx_d_i(31 downto 16) <= src_port_reg(7 downto 0) & src_port_reg(15 downto 8); -- UDP SRC port
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tx_d_i(47 downto 32) <= dst_port_reg(7 downto 0) & dst_port_reg(15 downto 8); -- UDP DST port
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tx_d_i(63 downto 48) <= tmpsum(7 downto 0) & tmpsum(15 downto 8); -- UDP Data length
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tx_c_i <= "00000000";
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if data_len_reg > 8 then
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DATA_REN <= '1'; -- Enable reading data
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else
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DATA_REN <= '0'; -- Enable reading data
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end if;
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fsm_state <= UDP_DATA;
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when UDP_DATA => -- The reset of UDP header & first data
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tx_d_i(15 downto 0) <= X"0000"; -- UDP checksum
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tx_d_i(63 downto 16) <= DATA_IN(47 downto 0);
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if data_len_reg > 18 then -- Min packet length is 60 so MAC hdr 14, IP hdr 20, UDP hdr 8, the rest is 18
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data_cntr <= data_len_reg - 6; -- 6 bytes are transmitted in this cycle
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230 |
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else
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231 |
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data_cntr <= x"000c";
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232 |
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end if;
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data_dly <= DATA_IN(63 downto 48);
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fsm_state <= DATA;
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if data_len_reg > 16 then
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DATA_REN <= '1'; -- Enable reading data
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237 |
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else
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238 |
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DATA_REN <= '0'; -- Enable reading data
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239 |
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end if;
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240 |
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when DATA =>
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242 |
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tx_d_i <= DATA_IN(47 downto 0) & data_dly;
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tx_c_i <= "00000000";
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data_dly <= DATA_IN(63 downto 48);
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245 |
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data_cntr <= data_cntr - 8;
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246 |
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DATA_REN <= '1';
|
247 |
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if data_cntr < 16 then
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248 |
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fsm_state <= DATA_LAST;
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249 |
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end if;
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250 |
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if data_cntr < 19 then
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DATA_REN <= '0';
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252 |
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end if;
|
253 |
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if data_cntr = 8 then
|
254 |
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crc_eop <= '1';
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255 |
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crc_mask <= "000";
|
256 |
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end if;
|
257 |
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|
258 |
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when DATA_LAST =>
|
259 |
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crc_eop <= '1';
|
260 |
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DATA_REN <= '0';
|
261 |
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case data_cntr(2 downto 0) is
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262 |
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when "000" =>
|
263 |
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crc_eop <= '0';
|
264 |
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tx_d_i <= X"070707FD00000000";
|
265 |
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tx_c_i <= "11110000";
|
266 |
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tx_d_i_vld <= '0';
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267 |
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fsm_state <= IDLE;
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268 |
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BUSY <= '0';
|
269 |
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IDLE_IFG <= '1';
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270 |
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when "001" =>
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271 |
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crc_mask <= "111";
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272 |
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tx_d_i <= X"0707FD00000000" & data_dly(7 downto 0);
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273 |
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tx_c_i <= "11100000";
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274 |
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fsm_state <= IFG;
|
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when "010" =>
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276 |
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crc_mask <= "110";
|
277 |
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tx_d_i <= X"07FD00000000" & data_dly(15 downto 0);
|
278 |
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tx_c_i <= "11000000";
|
279 |
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fsm_state <= IFG;
|
280 |
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when "011" =>
|
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crc_mask <= "101";
|
282 |
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tx_d_i <= X"FD00000000" & DATA_IN(7 downto 0) & data_dly(15 downto 0);
|
283 |
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tx_c_i <= "10000000";
|
284 |
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fsm_state <= IFG;
|
285 |
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when "100" =>
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286 |
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crc_mask <= "100";
|
287 |
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tx_d_i <= X"00000000" & DATA_IN(15 downto 0) & data_dly(15 downto 0);
|
288 |
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tx_c_i <= "00000000";
|
289 |
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fsm_state <= EOP;
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when "101" =>
|
291 |
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crc_mask <= "011";
|
292 |
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tx_d_i <= X"000000" & DATA_IN(23 downto 0) & data_dly(15 downto 0);
|
293 |
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tx_c_i <= "00000000";
|
294 |
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fsm_state <= EOP;
|
295 |
|
|
when "110" =>
|
296 |
|
|
crc_mask <= "010";
|
297 |
|
|
tx_d_i <= X"0000" & DATA_IN(31 downto 0) & data_dly(15 downto 0);
|
298 |
|
|
tx_c_i <= "00000000";
|
299 |
|
|
fsm_state <= EOP;
|
300 |
|
|
when "111" =>
|
301 |
|
|
crc_mask <= "001";
|
302 |
|
|
tx_d_i <= X"00" & DATA_IN(39 downto 0) & data_dly(15 downto 0);
|
303 |
|
|
tx_c_i <= "00000000";
|
304 |
|
|
fsm_state <= EOP;
|
305 |
|
|
when others => null;
|
306 |
|
|
end case;
|
307 |
|
|
|
308 |
|
|
when EOP =>
|
309 |
|
|
tx_d_i_vld <= '0';
|
310 |
|
|
case crc_mask is
|
311 |
|
|
when "100" =>
|
312 |
|
|
tx_d_i <= X"07070707070707FD";
|
313 |
|
|
tx_c_i <= "11111111";
|
314 |
|
|
BUSY <= '0';
|
315 |
|
|
fsm_state <= IDLE;
|
316 |
|
|
IDLE_IFG <= '1';
|
317 |
|
|
when "011" =>
|
318 |
|
|
tx_d_i <= X"070707070707FD00"; -- Last byte of CRC
|
319 |
|
|
tx_c_i <= "11111110";
|
320 |
|
|
BUSY <= '0';
|
321 |
|
|
fsm_state <= IDLE;
|
322 |
|
|
IDLE_IFG <= '1';
|
323 |
|
|
when "010" =>
|
324 |
|
|
tx_d_i <= X"0707070707FD0000"; -- Last two bytes of CRC
|
325 |
|
|
tx_c_i <= "11111100";
|
326 |
|
|
BUSY <= '0';
|
327 |
|
|
fsm_state <= IDLE;
|
328 |
|
|
IDLE_IFG <= '1';
|
329 |
|
|
when "001" =>
|
330 |
|
|
tx_d_i <= X"07070707FD000000"; -- Last three bytes of CRC
|
331 |
|
|
tx_c_i <= "11111000";
|
332 |
|
|
BUSY <= '0';
|
333 |
|
|
fsm_state <= IDLE;
|
334 |
|
|
IDLE_IFG <= '1';
|
335 |
|
|
|
336 |
|
|
when others => null;
|
337 |
|
|
end case;
|
338 |
|
|
|
339 |
|
|
when IFG =>
|
340 |
|
|
tx_d_i_vld <= '0';
|
341 |
|
|
tx_d_i <= X"0707070707070707";
|
342 |
|
|
tx_c_i <= "11111111";
|
343 |
|
|
BUSY <= '0';
|
344 |
|
|
fsm_state <= IDLE;
|
345 |
|
|
IDLE_IFG <= '1';
|
346 |
|
|
|
347 |
|
|
when others => null;
|
348 |
|
|
|
349 |
|
|
end case;
|
350 |
|
|
end if;
|
351 |
|
|
end process;
|
352 |
|
|
|
353 |
|
|
CRC_GEN: entity work.crc32_gen
|
354 |
|
|
generic map (
|
355 |
|
|
DATA_WIDTH => 64
|
356 |
|
|
)
|
357 |
|
|
port map(
|
358 |
|
|
DI => tx_d_i,
|
359 |
|
|
DI_DV => tx_d_i_vld,
|
360 |
|
|
EOP => crc_eop,
|
361 |
|
|
MASK => crc_mask,
|
362 |
|
|
CLK => TX_CLK,
|
363 |
|
|
RESET => RESET,
|
364 |
|
|
CRC => crc32_i,
|
365 |
|
|
DO_DV => crc_vld
|
366 |
|
|
);
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
-- Swap bytes in the CRC word
|
370 |
|
|
crc32 <= crc32_i(7 downto 0) & crc32_i(15 downto 8) & crc32_i(23 downto 16) & crc32_i(31 downto 24);
|
371 |
|
|
|
372 |
|
|
-- Delay the frame data till the end of CRC computation
|
373 |
|
|
XGMII_DELAY: process(TX_CLK)
|
374 |
|
|
begin
|
375 |
|
|
if (TX_CLK'event and TX_CLK = '1') then
|
376 |
|
|
txd_i_dly0 <= tx_d_i;
|
377 |
|
|
txc_i_dly0 <= tx_c_i;
|
378 |
|
|
crc_mask_dly0 <= crc_mask;
|
379 |
|
|
|
380 |
|
|
txd_i_dly1 <= txd_i_dly0;
|
381 |
|
|
txc_i_dly1 <= txc_i_dly0;
|
382 |
|
|
crc_mask_dly1 <= crc_mask_dly0;
|
383 |
|
|
|
384 |
|
|
txd_i_dly2 <= txd_i_dly1;
|
385 |
|
|
txc_i_dly2 <= txc_i_dly1;
|
386 |
|
|
crc_mask_dly2 <= crc_mask_dly1;
|
387 |
|
|
|
388 |
|
|
txd_i_dly3 <= txd_i_dly2;
|
389 |
|
|
txc_i_dly3 <= txc_i_dly2;
|
390 |
|
|
crc_mask_dly3 <= crc_mask_dly2;
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
|
394 |
|
|
crc_mask_dly4 <= crc_mask_dly3;
|
395 |
|
|
|
396 |
|
|
end if;
|
397 |
|
|
end process;
|
398 |
|
|
|
399 |
|
|
-- process will insert result of crc computation to output
|
400 |
|
|
CRC_INSERT: process(TX_CLK)
|
401 |
|
|
begin
|
402 |
|
|
if (TX_CLK'event and TX_CLK = '1') then
|
403 |
|
|
crc_dly <= crc32;
|
404 |
|
|
crc_vld_dly <= crc_vld;
|
405 |
|
|
TXD <= txd_i_dly3;
|
406 |
|
|
TXC <= txc_i_dly3;
|
407 |
|
|
|
408 |
|
|
if crc_vld = '1' then
|
409 |
|
|
case crc_mask_dly3 is
|
410 |
|
|
when "001" => TXD <= crc32( 7 downto 0) & txd_i_dly3(55 downto 0);
|
411 |
|
|
when "010" => TXD <= crc32(15 downto 0) & txd_i_dly3(47 downto 0);
|
412 |
|
|
when "011" => TXD <= crc32(23 downto 0) & txd_i_dly3(39 downto 0);
|
413 |
|
|
when "100" => TXD <= crc32(31 downto 0) & txd_i_dly3(31 downto 0);
|
414 |
|
|
when "101" => TXD <= txd_i_dly3(63 downto 56) & crc32(31 downto 0) & txd_i_dly3(23 downto 0);
|
415 |
|
|
when "110" => TXD <= txd_i_dly3(63 downto 48) & crc32(31 downto 0) & txd_i_dly3(15 downto 0);
|
416 |
|
|
when "111" => TXD <= txd_i_dly3(63 downto 40) & crc32(31 downto 0) & txd_i_dly3(7 downto 0);
|
417 |
|
|
when others => null;
|
418 |
|
|
end case;
|
419 |
|
|
elsif crc_vld_dly = '1' then
|
420 |
|
|
case crc_mask_dly4 is
|
421 |
|
|
when "000" => TXD <= txd_i_dly3(63 downto 32) & crc_dly(31 downto 0);
|
422 |
|
|
when "001" => TXD <= txd_i_dly3(63 downto 24) & crc_dly(31 downto 8);
|
423 |
|
|
when "010" => TXD <= txd_i_dly3(63 downto 16) & crc_dly(31 downto 16);
|
424 |
|
|
when "011" => TXD <= txd_i_dly3(63 downto 8) & crc_dly(31 downto 24);
|
425 |
|
|
when others => null;
|
426 |
|
|
end case;
|
427 |
|
|
end if;
|
428 |
|
|
|
429 |
|
|
end if;
|
430 |
|
|
end process;
|
431 |
|
|
|
432 |
|
|
end behavioral;
|
433 |
|
|
|