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Subversion Repositories udp_ipv4_for_10g_ethernet

[/] [udp_ipv4_for_10g_ethernet/] [trunk/] [src/] [hdl/] [frame_pkg.vhd] - Blame information for rev 3

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1 3 DFC
-------------------------------------------------------------------------------
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--
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-- (C) Copyright 2013 DFC Design, s.r.o., Brno, Czech Republic
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-- Author: Marek Kvas (m.kvas@dfcdesign.cz)
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--
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-------------------------------------------------------------------------------
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-- This file is part of UDP/IPv4 for 10 G Ethernet core.
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-- 
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-- UDP/IPv4 for 10 G Ethernet core is free software: you can 
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-- redistribute it and/or modify it under the terms of 
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-- the GNU Lesser General Public License as published by the Free 
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-- Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- UDP/IPv4 for 10 G Ethernet core is distributed in the hope that 
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-- it will be useful, but WITHOUT ANY WARRANTY; without even 
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-- the implied warranty of MERCHANTABILITY or FITNESS FOR A 
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-- PARTICULAR PURPOSE.  See the GNU Lesser General Public License 
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-- for more details.
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-- 
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-- You should have received a copy of the GNU Lesser General Public 
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-- License along with UDP/IPv4 for 10 G Ethernet core.  If not, 
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-- see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------
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-- 
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-- This package is collection of types and constants that are shared between
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-- several modules in the UDP/IPv4 frame processing components.
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package frame_pkg is
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   -- Type to hold MAC and IP addresses and UDP ports
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   subtype mac_addr_type is std_logic_vector(47 downto 0);
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   type mac_addr_array_type is array (natural range <>) of mac_addr_type;
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   subtype ip_addr_type is std_logic_vector(31 downto 0);
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   type ip_addr_array_type is array (natural range <>) of ip_addr_type;
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   subtype udp_port_type is std_logic_vector(15 downto 0);
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   type udp_port_array_type is array (natural range <>) of udp_port_type;
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   -- Types for 64 bit data ports
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   subtype data64_port_type is std_logic_vector(63 downto 0);
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   type data64_port_array_type is array (natural range <>) of data64_port_type;
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   -- Frame process constants and types
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   constant C_FP_TAG_LENGTH_BITLEN : integer := 16;
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   constant C_FP_TAG_RET_INFO_LENGTH_BITLEN : integer :=
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                                             C_FP_TAG_LENGTH_BITLEN +16;
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   constant C_FP_TAG_FLAGS_BITLEN : integer := 2;
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   constant C_FP_TAG_UDP : std_logic_vector
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                  (C_FP_TAG_FLAGS_BITLEN - 1 downto 0) := "01";
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   constant C_FP_TAG_DISCARD : std_logic_vector
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                  (C_FP_TAG_FLAGS_BITLEN - 1 downto 0) := "10";
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   constant C_FP_TAG_RETINF : std_logic_vector
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                  (C_FP_TAG_FLAGS_BITLEN - 1 downto 0) := "00";
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   -- Type for tag fifo 2b flags + 32bit return info or length
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   subtype fp_tfifo_data_type is std_logic_vector(C_FP_TAG_FLAGS_BITLEN + C_FP_TAG_RET_INFO_LENGTH_BITLEN  - 1 downto 0);
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   subtype fp_dfifo_data_type is std_logic_vector(71 downto 0);
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   subtype txi_tfifo_data_type is std_logic_vector(C_FP_TAG_LENGTH_BITLEN - 1 downto 0);
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   subtype txi_dfifo_data_type is std_logic_vector(71 downto 0);
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   -- Mainly for CMP registers
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   subtype data32_port_type is std_logic_vector(31 downto 0);
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   type data32_port_array_type is array (natural range <>) of data32_port_type;
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   -- Function that sets one bit only according to addr
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   function one_of_n(vec_len: integer; addr : integer) return std_logic_vector;
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   function one_of_n(vec: std_logic_vector; addr : integer) return std_logic_vector;
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   -- Returns position of the first bit
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   function first_bit_set(vec : std_logic_vector) return integer;
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   -- Returns number of bits in 1
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   function num_of_ones(vec : std_logic_vector) return integer;
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end package;
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package body frame_pkg is
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   -- Returns vector of length of vec with one bit set only at
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   -- position addr
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   function one_of_n(vec: std_logic_vector; addr : integer) return std_logic_vector is
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      variable res : std_logic_vector(vec'range) := (others => '0');
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   begin
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      res(addr) := '1';
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      return res;
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   end function;
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   -- Returns vector of length of vec_len with one bit set only at
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   -- position addr
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   function one_of_n(vec_len: integer; addr : integer) return std_logic_vector is
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      variable res : std_logic_vector(vec_len - 1 downto 0) := (others => '0');
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   begin
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      res(addr) := '1';
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      return res;
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   end function;
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   function first_bit_set(vec : std_logic_vector) return integer is
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   begin
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      -- find first bit set
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      for i in vec'range loop
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         if vec(i) = '1' then
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            return i;
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         end if;
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      end loop;
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      return 0;
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   end function;
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   -- Returns number of bits in 1
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   function num_of_ones(vec : std_logic_vector) return integer is
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      variable res   : integer := 0;
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   begin
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      for i in 0 to vec'left loop
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         if vec(i) = '1' then
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            res := res + 1;
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         end if;
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      end loop;
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      return res;
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   end function;
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end package body;
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