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[/] [v65c816/] [trunk/] [BCDAdder.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library STD;
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use IEEE.NUMERIC_STD.ALL;
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library work;
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entity bit_adder is
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        port(
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                A               : in std_logic;
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                B               : in std_logic;
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                CI              : in std_logic;
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                S               : out std_logic;
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                CO              : out std_logic
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        );
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end bit_adder;
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architecture rtl of bit_adder is
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begin
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        S <= (not A and not B and     CI) or
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                  (not A and     B and not CI) or
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                  (    A and not B and not CI) or
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                  (    A and     B and     CI);
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        CO <= (not A and     B and     CI) or
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                        (    A and not B and     CI) or
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                        (    A and     B and not CI) or
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                        (    A and     B and     CI);
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end rtl;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library STD;
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use IEEE.NUMERIC_STD.ALL;
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library work;
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entity adder4 is
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        port(
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                A               : in std_logic_vector(3 downto 0);
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                B               : in std_logic_vector(3 downto 0);
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                CI              : in std_logic;
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                S               : out std_logic_vector(3 downto 0);
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                CO              : out std_logic
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        );
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end adder4;
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architecture rtl of adder4 is
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        component bit_adder is
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        port(
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                A               : in std_logic;
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                B               : in std_logic;
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                CI              : in std_logic;
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                S               : out std_logic;
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                CO              : out std_logic
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        );
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        end component;
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        signal CO0, CO1, CO2 : std_logic;
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begin
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        b_add0: bit_adder port map (A(0), B(0), CI,  S(0), CO0);
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        b_add1: bit_adder port map (A(1), B(1), CO0, S(1), CO1);
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        b_add2: bit_adder port map (A(2), B(2), CO1, S(2), CO2);
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        b_add3: bit_adder port map (A(3), B(3), CO2, S(3), CO);
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end rtl;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library STD;
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use IEEE.NUMERIC_STD.ALL;
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library work;
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entity BCDAdder is
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        port(
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                A               : in std_logic_vector(3 downto 0);
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                B               : in std_logic_vector(3 downto 0);
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                CI              : in std_logic;
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                S               : out std_logic_vector(3 downto 0);
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                CO              : out std_logic;
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                VO              : out std_logic;
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                ADD     : in std_logic;
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                BCD     : in std_logic
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        );
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end BCDAdder;
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architecture rtl of BCDAdder is
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        signal B2               : std_logic_vector(3 downto 0);
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        signal BIN_S    : std_logic_vector(3 downto 0);
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        signal BIN_CO   : std_logic;
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        signal BCD_B    : std_logic_vector(3 downto 0);
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        signal BCD_CO   : std_logic;
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begin
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        B2 <= B xor (3 downto 0 => not ADD);
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        bin_adder : entity work.adder4
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        port map(
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                A               => A,
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                B               => B2,
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                CI              => CI,
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                S               => BIN_S,
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                CO              => BIN_CO
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        );
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        BCD_CO <= (BIN_S(3) and BIN_S(2)) or (BIN_S(3) and BIN_S(1)) or (BIN_CO xor not ADD);
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        BCD_B <= not ADD & ((BCD_CO and BCD) xor not ADD) & ((BCD_CO and BCD) xor not ADD) & not ADD;
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        bcd_corr_adder : entity work.adder4
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        port map(
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                A               => BIN_S,
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                B               => BCD_B,
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                CI              => not ADD,
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                S               => S
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        );
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        CO <= BIN_CO when BCD = '0' else BCD_CO xor not ADD;
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        VO <= (not (A(3) xor B2(3))) and (A(3) xor BIN_S(3));
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end rtl;

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