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[/] [v65c816/] [trunk/] [cpufsm.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- CPU FSM main state machine
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entity cpufsm is
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  port(      clk:  in STD_LOGIC;
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             clr:  in STD_LOGIC;
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           fwait:  in STD_LOGIC;
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            ireq:  in STD_LOGIC;
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             aim:  in STD_LOGIC;
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          bcarry:  in STD_LOGIC;
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          icarry:  in STD_LOGIC;
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              p1:  in STD_LOGIC_VECTOR(2 downto 0);
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            e_ei:  in STD_LOGIC;
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           mc_ei:  in STD_LOGIC;
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          addsub:  in STD_LOGIC;
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        dec_mode:  in STD_LOGIC;
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           fetch: out STD_LOGIC;
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         op_sync: out STD_LOGIC;
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             pci: out STD_LOGIC;
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              pq: out STD_LOGIC_VECTOR(2 downto 0);
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              fb: out STD_LOGIC;
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              od: out STD_LOGIC;
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          mc_nop: out STD_LOGIC
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      );
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end cpufsm;
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architecture rtl of cpufsm is
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type states is (s0,s1,s2,s3,s4,s5,s6);
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attribute ENUM_ENCODING:STRING;
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attribute ENUM_ENCODING of states: type is "000000001 000000010 000000100 000001000 000010000 000100000 001000000";  -- one hot encoding for all states
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signal present,nxt:states;
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begin
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  process(clk)
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  begin
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    if (clk'event and clk = '1') then
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      if fwait = '1' then
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        present <= present;
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      else
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        present <= nxt;
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      end if;
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    end if;
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  end process;
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  process(present,ireq,bcarry,icarry,p1,e_ei,mc_ei,aim,clr,addsub,dec_mode)
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  begin
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    case present is
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      -- reset
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      when s0 =>
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      fetch <= '0';
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      op_sync <= '0';
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      pci <= '0';
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      pq <= "000";
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      fb <= '1';                              -- force BRK                              
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      od <= '1';                              -- clear microcode sequencer
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      mc_nop <= '0';
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      if clr = '1' then
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        nxt <= s0;
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      else
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        nxt <= s2;
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      end if;
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      -- fetch opcode
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      when s1 =>
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      pq <= "000";
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      if ireq = '1' then                      -- if interrupt request
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        od <= '0';
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                  fetch <= '0';
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        fb <= '0';
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        pci <= '0';                           -- PC doesn't increment
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        op_sync <= '0';
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        mc_nop <= '1';                        -- stop microcode execution
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        nxt <= s6;                            -- goto s6
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      else
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        od <= '1';                            -- clear microcode sequencer
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        fetch <= '1';                         -- fetch opcode
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                  fb <= '0';
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        pci <= '1';                           -- PC increment
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        if addsub = '1'then                   -- if ADD/SUB opcode may require an extra cycle for DAA/DAS adjustement
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          op_sync <= '0';
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          mc_nop <= '0';
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          nxt <= s5;                          -- goto s5
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        else
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          if e_ei = '1' then                  -- if end of instruction is reached on fetch 
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            mc_nop <= '1';
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            if clr = '1' then                 -- if reset
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              op_sync <= '0';
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              nxt <= s0;                      -- goto reset 
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            else
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              op_sync <= '1';                 -- remain in this state to fetch a new opcode
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              nxt <= s1;
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            end if;
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          else
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            mc_nop <= '0';
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            op_sync <= '0';                   -- goto s2
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            nxt <= s2;
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          end if;
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        end if;
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      end if;
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      -- wait until end of instruction
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      when s2 =>
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      fetch <= '0';
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      pq <= p1;
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      fb <= '0';
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      od <= '0';
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      mc_nop <= '0';
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      pci <= '0';
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      if aim = '1' then                     -- opcode with indexed mode
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        op_sync <= '0';
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        nxt <= s3;
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      else
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        if mc_ei = '1' then                 -- if end of instruction is reached 
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          if clr = '1' then
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            op_sync <= '0';
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            nxt <= s0;
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          else
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            op_sync <= '1';
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            nxt <= s1;
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          end if;
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        else
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            op_sync <= '0';
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            nxt <= s2;
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        end if;
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      end if;
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      when s3 =>                            -- opcode with absolute indexed mode
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      fetch <= '0';
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      pq <= p1;
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      fb <= '0';
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      od <= '0';
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      pci <= '0';
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      if mc_ei = '1' then                   -- if end of instruction is reached 
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        if icarry = '0' then
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          mc_nop <= '1';
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          if clr = '1' then
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            op_sync <= '0';
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            nxt <= s0;
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          else
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            op_sync <= '1';
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            nxt <= s1;
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          end if;
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        else
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          op_sync <= '0';
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          mc_nop <= '0';
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          nxt <= s4;
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        end if;
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      else
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        op_sync <= '0';
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        mc_nop <= '0';
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        nxt <= s3;
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      end if;
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      when s4 =>                            -- opcode with absolute indexed mode: add carry to msb PC
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      fetch <= '0';
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      pq <= p1;
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      fb <= '0';
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      od <= '0';
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      pci <= '0';
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      if clr = '1' then
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        mc_nop <= '0';
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        op_sync <= '0';
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        nxt <= s0;
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      else
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        mc_nop <= '1';
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        op_sync <= '1';
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        nxt <= s1;
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      end if;
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      -- ADD/SUB decimal adjustement extra cycle
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      when s5 =>
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      fetch <= '0';
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      pq <= p1;
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      fb <= '0';
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      od <= '0';
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      pci <= '0';
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      if mc_ei = '1' then
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        if dec_mode = '0' then
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          mc_nop <= '1';
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        else
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          mc_nop <= '0';
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        end if;
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        if clr = '1' then
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          op_sync <= '0';
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          nxt <= s0;
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        else
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          op_sync <= '1';
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          nxt <= s1;
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        end if;
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      else
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        mc_nop <= '0';
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        op_sync <= '0';
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        nxt <= s5;
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      end if;
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      when s6 =>
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      pq <= "000";
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      od <= '1';                            -- clear microcode sequencer
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      fetch <= '0';
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      fb <= '1';                            -- force load BRK to opcode register 
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      pci <= '0';                           -- PC doesn't increment
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      op_sync <= '1';
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      mc_nop <= '0';
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      nxt <= s2;                            -- goto s2
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      -- illegal state covering
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      when others =>
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      fetch <= '0';
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      op_sync <= '0';
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      pci <= '0';
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      pq <= "000";
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      fb <= '0';
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      od <= '1';
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      mc_nop <= '0';
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      nxt <= s0;
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    end case;
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  end process;
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end rtl;
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