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[/] [v65c816/] [trunk/] [dr.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 16 bit zero page/direct register "D"
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entity dr is
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  port(     clk:  in STD_LOGIC;
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            clr:  in STD_LOGIC;
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          fwait:  in STD_LOGIC;
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         ld_lsb:  in STD_LOGIC;                        -- load lsb
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         ld_msb:  in STD_LOGIC;                        -- load msb
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            din:  in STD_LOGIC_VECTOR(15 downto 0);
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           dout: out STD_LOGIC_VECTOR(15 downto 0)
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      );
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end dr;
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architecture rtl of dr is
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signal reg: STD_LOGIC_VECTOR(15 downto 0);
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signal op:  STD_LOGIC_VECTOR(1 downto 0);
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begin
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  op <= ld_msb & ld_lsb;
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  process(clk)
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    begin
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      if (clk'event and clk = '1') then
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        if fwait = '1' then
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          reg <= reg;
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        else
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          if clr = '1' then
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            reg <= "0000000000000000";
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          else
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                                 case op is
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                                        when   "01" => reg(7 downto 0) <= din(7 downto 0);              -- load lsb
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                                                                                reg(15 downto 8) <= reg(15 downto 8);
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                                        when   "10" => reg(15 downto 8) <= din(7 downto 0);             -- load msb
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                                                                                reg(7 downto 0) <= reg(7 downto 0);
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                                        when   "11" => reg <= din;                                      -- load msb & lsb                                               
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                                        when others => reg <= reg;
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                                 end case;
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          end if;
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        end if;
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      end if;
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  end process;
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  dout <= reg;
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end rtl;
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