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[/] [v65c816/] [trunk/] [mcpla.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- microcode 65C816
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-- Written by Valerio Venturi
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-- output fields format:
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-- fields:
10
-- RSEL:  registers output multiplexer select
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-- REGOP: registers load/increment/decrement etc.
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-- ALUOP: ALU operation
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-- P_OP:  register P set/reset bit
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-- MPR:   register MP 
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-- PCR:   register PC 
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-- CLI:   clear interrupt request
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-- EI:    end of microcode sequence
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-- W:     read/write control
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-- PD:    PC/MP output multiplexer select
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-- VPA:   valid program address
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-- VDA:   valid data address
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-- ML:    memory lock
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entity mcpla is
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  port(em:  in STD_LOGIC;                           -- emulation mode (1)/native mode (0)
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        m:  in STD_LOGIC;                           -- M memory/acc. 8 bit (1), M memory/acc. 16 bit (0)  
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        x:  in STD_LOGIC;                           -- X index reg. 8 bit (1), X index reg. 16 bit (0)  
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        a:  in STD_LOGIC_VECTOR(12 downto 0);
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        q: out STD_LOGIC_VECTOR(44 downto 0)
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      );
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end mcpla;
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architecture comb of mcpla is
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constant  MC_ADDR_LENGTH: INTEGER := 12;
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-- opcode definition:
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-- <EXPANSION OPCODE (1 BIT) (WDM)>-<OPCODE (8 bits)>-<MICROCODE (4 BITS)>
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38
------------------------------------
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--            IMPLIED             --
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------------------------------------
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constant   NOP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010100000"; -- 0xEA NOP
42
 
43
-- interrupts/coprocessor
44
constant   BRK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000000"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000001"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000010"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000011"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000100"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000101"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000110"; -- 0x00 BRK/IRQ/NMI/RES
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constant   BRK_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000000111"; -- 0x00 BRK/IRQ/NMI/RES
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constant   COP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100000"; -- 0x02 COP
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constant   COP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100001"; -- 0x02 COP
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constant   COP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100010"; -- 0x02 COP
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constant   COP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100011"; -- 0x02 COP
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constant   COP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100100"; -- 0x02 COP
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constant   COP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100101"; -- 0x02 COP
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constant   COP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100110"; -- 0x02 COP
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constant   COP_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000100111"; -- 0x02 COP
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62
-- IMPLIED
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constant   CLC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110000000"; -- 0x18 CLC 0->C 
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constant   SEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110000000"; -- 0x38 SEC 1->C
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constant   CLI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110000000"; -- 0x58 CLI 0->I
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constant   SEI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110000000"; -- 0x78 SEI 1->I
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constant   CLV_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110000000"; -- 0xB8 CLV 0->V
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constant   CLD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110000000"; -- 0xD8 CLD 0->D
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constant   SED_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110000000"; -- 0xF8 SED 1->D
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constant   TAX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010100000"; -- 0xAA TAX A->X
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constant   TAY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010000000"; -- 0xA8 TAY A->Y
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constant   TXA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010100000"; -- 0x8A TXA X->A
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constant   TYA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110000000"; -- 0x98 TYA Y->A
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constant   TXY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110110000"; -- 0x9B TXY X->Y
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constant   TYX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110110000"; -- 0xBB TYX Y->X
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constant   TXS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110100000"; -- 0x9A TXS X->S
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constant   TSX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110100000"; -- 0xBA TSX S->X
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constant   TCD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110110000"; -- 0x5B TCD C->D
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constant   TDC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110110000"; -- 0x7B TDC D->C
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constant   PHP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010000000"; -- 0x08 PHP P->S
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constant   PHA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010000000"; -- 0x48 PHA A->S
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constant   PHA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010000001"; -- 0x48 PHA A->S
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constant   PHX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110100000"; -- 0xDA PHX X->S
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constant   PHX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110100001"; -- 0xDA PHX X->S
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constant   PHY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110100000"; -- 0x5A PHY X->S
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constant   PHY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110100001"; -- 0x5A PHY X->S
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constant   PHD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010110000"; -- 0x0B PHD D->S
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constant   PHD_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010110001"; -- 0x0B PHD D->S
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constant   PLP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010000000"; -- 0x28 PLP S->P
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constant   PLP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010000001"; -- 0x28 PLP S->P
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constant   PLA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010000000"; -- 0x68 PLA S->A
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constant   PLA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010000001"; -- 0x68 PLA S->A
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constant   PLA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010000010"; -- 0x68 PLA S->A
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constant   PLA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010000011"; -- 0x68 PLA S->A
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constant   PLX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110100000"; -- 0xFA PLX S->X
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constant   PLX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110100001"; -- 0xFA PLX S->X
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constant   PLX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110100010"; -- 0xFA PLX S->X
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constant   PLX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110100011"; -- 0xFA PLX S->X
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constant   PLY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110100000"; -- 0x7A PLY S->Y
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constant   PLY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110100001"; -- 0x7A PLY S->Y
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constant   PLY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110100010"; -- 0x7A PLY S->Y
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constant   PLY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110100011"; -- 0x7A PLY S->Y
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constant   PLD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010110000"; -- 0x2B PLD S->D
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constant   PLD_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010110001"; -- 0x2B PLD S->D
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constant   PLD_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010110010"; -- 0x2B PLD S->D
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constant   INC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110100000"; -- 0x1A INC A +1
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constant   DEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110100000"; -- 0x3A DEC A -1
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constant   INX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010000000"; -- 0xE8 INX X +1
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constant   DEX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010100000"; -- 0xCA DEX X -1
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constant   INY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010000000"; -- 0xC8 INY Y +1
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constant   DEY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010000000"; -- 0x88 DEY Y -1
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constant   RTS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000000000"; -- 0x60 RTS    
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constant   RTS_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000000001"; -- 0x60 RTS    
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constant   RTS_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000000010"; -- 0x60 RTS    
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constant   RTS_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000000011"; -- 0x60 RTS    
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constant   RTS_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000000100"; -- 0x60 RTS    
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constant   RTI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000000"; -- 0x40 RTI    
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constant   RTI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000001"; -- 0x40 RTI    
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constant   RTI_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000010"; -- 0x40 RTI    
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constant   RTI_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000011"; -- 0x40 RTI    
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constant   RTI_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000100"; -- 0x40 RTI    
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constant   RTI_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000101"; -- 0x40 RTI    
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constant   RTI_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000000110"; -- 0x40 RTI    
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constant   ASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010100000"; -- 0x0A ASL A  
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constant   LSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010100000"; -- 0x4A LSR A  
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constant   ROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010100000"; -- 0x2A ROL A  
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constant   ROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010100000"; -- 0x6A ROR A  
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constant   TCS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110110000"; -- 0x1B A->S
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constant   TSC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110110000"; -- 0x3B S->A
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constant   XCE_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110110000"; -- 0xFB XCE E<->C 
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constant   WDM_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000100000"; -- 0x42 WDM
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constant   PHK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010110000"; -- 0x4B PHK K->S
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constant   PHB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010110000"; -- 0x8B PHB B->S
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constant   PLB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010110000"; -- 0xAB PLB S->B
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constant   PLB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010110001"; -- 0xAB PLB S->B
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constant   RTL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110000"; -- 0x6B RTL    
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constant   RTL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110001"; -- 0x6B RTL    
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constant   RTL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110010"; -- 0x6B RTL    
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constant   RTL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110011"; -- 0x6B RTL    
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constant   RTL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110100"; -- 0x6B RTL    
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constant   RTL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110101"; -- 0x6B RTL    
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constant   RTL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010110110"; -- 0x6B RTL    
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constant   XBA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010110000"; -- 0xEB XBA (swap A)
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constant   WAI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010110000"; -- 0xCB WAI
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constant   WAI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010110001"; -- 0xCB WAI
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constant   STP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110110000"; -- 0xDB STP
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constant   STP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110110001"; -- 0xDB STP
148
 
149
------------------------------------
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--           IMMEDIATE            --
151
------------------------------------
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constant IMLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010010000"; -- 0xA9 LDA #IMM
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constant IMLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101010010001"; -- 0xA9 LDA #IMM
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constant IMLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000100000"; -- 0xA2 LDX #IMM
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constant IMLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000100001"; -- 0xA2 LDX #IMM
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constant IMLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000000000"; -- 0xA0 LDY #IMM
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constant IMLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000000001"; -- 0xA0 LDY #IMM
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constant IMADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010010000"; -- 0x69 ADC #IMM 
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constant IMADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010010001"; -- 0x69 ADC #IMM 
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constant IMADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011010010010"; -- 0x69 ADC #IMM 
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constant IMSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010010000"; -- 0xE9 SBC #IMM 
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constant IMSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010010001"; -- 0xE9 SBC #IMM 
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constant IMSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111010010010"; -- 0xE9 SBC #IMM 
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constant IMAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010010000"; -- 0x29 AND #IMM 
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constant IMAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001010010001"; -- 0x29 AND #IMM 
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constant IMORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010010000"; -- 0x09 ORA #IMM 
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constant IMORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000010010001"; -- 0x09 ORA #IMM 
168
constant IMEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010010000"; -- 0x49 EOR #IMM 
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constant IMEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010010010001"; -- 0x49 EOR #IMM 
170
constant IMCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010010000"; -- 0xC9 CMP #IMM 
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constant IMCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110010010001"; -- 0xC9 CMP #IMM 
172
constant IMCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000000000"; -- 0xE0 CPX #IMM 
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constant IMCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000000001"; -- 0xE0 CPX #IMM 
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constant IMCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000000000"; -- 0xC0 CPY #IMM 
175
constant IMCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000000001"; -- 0xC0 CPY #IMM 
176
constant IMBRK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010010000"; -- 0x89 BRK #IMM 
177
constant IMBRK_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010010001"; -- 0x89 BRK #IMM 
178
constant IMSEP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000100000"; -- 0xE2 SEP #IMM 
179
constant IMREP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000100000"; -- 0xC2 REP #IMM 
180
constant IMBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010010000"; -- 0x89 BIT #IMM 
181
constant IMBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100010010001"; -- 0x89 BIT #IMM 
182
 
183
------------------------------------
184
--           ZERO PAGE            --
185
------------------------------------
186
constant ZPLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001010000"; -- 0xA5 LDA ZP
187
constant ZPLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001010001"; -- 0xA5 LDA ZP
188
constant ZPLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001010010"; -- 0xA5 LDA ZP
189
constant ZPLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001100000"; -- 0xA6 LDX ZP
190
constant ZPLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001100001"; -- 0xA6 LDX ZP
191
constant ZPLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001100010"; -- 0xA6 LDX ZP
192
constant ZPLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001000000"; -- 0xA4 LDY ZP
193
constant ZPLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001000001"; -- 0xA4 LDY ZP
194
constant ZPLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001000010"; -- 0xA4 LDY ZP
195
constant ZPSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001010000"; -- 0x85 STA ZP
196
constant ZPSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001010001"; -- 0x85 STA ZP
197
constant ZPSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001010010"; -- 0x85 STA ZP
198
constant ZPSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001100000"; -- 0x86 STX ZP
199
constant ZPSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001100001"; -- 0x86 STX ZP
200
constant ZPSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001100010"; -- 0x86 STX ZP
201
constant ZPSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001000000"; -- 0x84 STY ZP
202
constant ZPSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001000001"; -- 0x84 STY ZP
203
constant ZPSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001000010"; -- 0x84 STY ZP
204
constant ZPSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001000000"; -- 0x64 STZ ZP
205
constant ZPSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001000001"; -- 0x64 STZ ZP
206
constant ZPSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001000010"; -- 0x64 STZ ZP
207
constant ZPADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001010000"; -- 0x65 ADC ZP
208
constant ZPADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001010001"; -- 0x65 ADC ZP
209
constant ZPADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001010010"; -- 0x65 ADC ZP
210
constant ZPADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001010011"; -- 0x65 ADC ZP
211
constant ZPSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001010000"; -- 0xE5 SBC ZP
212
constant ZPSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001010001"; -- 0xE5 SBC ZP
213
constant ZPSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001010010"; -- 0xE5 SBC ZP
214
constant ZPSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001010011"; -- 0xE5 SBC ZP
215
constant ZPCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001010000"; -- 0xC5 CMP ZP
216
constant ZPCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001010001"; -- 0xC5 CMP ZP
217
constant ZPCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001010010"; -- 0xC5 CMP ZP
218
constant ZPCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001000000"; -- 0xE4 CPX ZP
219
constant ZPCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001000001"; -- 0xE4 CPX ZP
220
constant ZPCPX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001000010"; -- 0xE4 CPX ZP
221
constant ZPCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001000000"; -- 0xC4 CPY ZP
222
constant ZPCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001000001"; -- 0xC4 CPY ZP
223
constant ZPCPY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001000010"; -- 0xC4 CPY ZP
224
constant ZPAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001010000"; -- 0x25 AND ZP
225
constant ZPAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001010001"; -- 0x25 AND ZP
226
constant ZPAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001010010"; -- 0x25 AND ZP
227
constant ZPORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001010000"; -- 0x05 ORA ZP
228
constant ZPORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001010001"; -- 0x05 ORA ZP
229
constant ZPORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001010010"; -- 0x05 ORA ZP
230
constant ZPEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001010000"; -- 0x45 EOR ZP
231
constant ZPEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001010001"; -- 0x45 EOR ZP
232
constant ZPEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001010010"; -- 0x45 EOR ZP
233
constant ZPBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001000000"; -- 0x24 BIT ZP
234
constant ZPBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001000001"; -- 0x24 BIT ZP
235
constant ZPBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001000010"; -- 0x24 BIT ZP
236
constant ZPASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100000"; -- 0x06 ASL ZP 
237
constant ZPASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100001"; -- 0x06 ASL ZP 
238
constant ZPASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100010"; -- 0x06 ASL ZP 
239
constant ZPASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100011"; -- 0x06 ASL ZP 
240
constant ZPASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100100"; -- 0x06 ASL ZP 
241
constant ZPASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001100101"; -- 0x06 ASL ZP 
242
constant ZPLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100000"; -- 0x46 LSR ZP 
243
constant ZPLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100001"; -- 0x46 LSR ZP 
244
constant ZPLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100010"; -- 0x46 LSR ZP 
245
constant ZPLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100011"; -- 0x46 LSR ZP 
246
constant ZPLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100100"; -- 0x46 LSR ZP 
247
constant ZPLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001100101"; -- 0x46 LSR ZP 
248
constant ZPROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100000"; -- 0x26 ROL ZP 
249
constant ZPROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100001"; -- 0x26 ROL ZP 
250
constant ZPROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100010"; -- 0x26 ROL ZP 
251
constant ZPROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100011"; -- 0x26 ROL ZP 
252
constant ZPROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100100"; -- 0x26 ROL ZP 
253
constant ZPROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001100101"; -- 0x26 ROL ZP 
254
constant ZPROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100000"; -- 0x66 ROR ZP 
255
constant ZPROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100001"; -- 0x66 ROR ZP 
256
constant ZPROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100010"; -- 0x66 ROR ZP 
257
constant ZPROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100011"; -- 0x66 ROR ZP 
258
constant ZPROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100100"; -- 0x66 ROR ZP 
259
constant ZPROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001100101"; -- 0x66 ROR ZP 
260
constant ZPINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100000"; -- 0xE6 INC ZP 
261
constant ZPINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100001"; -- 0xE6 INC ZP 
262
constant ZPINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100010"; -- 0xE6 INC ZP 
263
constant ZPINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100011"; -- 0xE6 INC ZP 
264
constant ZPINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100100"; -- 0xE6 INC ZP 
265
constant ZPINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001100101"; -- 0xE6 INC ZP 
266
constant ZPDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100000"; -- 0xC6 DEC ZP 
267
constant ZPDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100001"; -- 0xC6 DEC ZP 
268
constant ZPDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100010"; -- 0xC6 DEC ZP 
269
constant ZPDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100011"; -- 0xC6 DEC ZP 
270
constant ZPDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100100"; -- 0xC6 DEC ZP 
271
constant ZPDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001100101"; -- 0xC6 DEC ZP 
272
constant ZPTSB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000000"; -- 0x04 TSB ZP 
273
constant ZPTSB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000001"; -- 0x04 TSB ZP 
274
constant ZPTSB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000010"; -- 0x04 TSB ZP 
275
constant ZPTSB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000011"; -- 0x04 TSB ZP 
276
constant ZPTSB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000100"; -- 0x04 TSB ZP 
277
constant ZPTSB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000101"; -- 0x04 TSB ZP 
278
constant ZPTSB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001000110"; -- 0x04 TSB ZP 
279
constant ZPTRB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000000"; -- 0x14 TRB ZP 
280
constant ZPTRB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000001"; -- 0x14 TRB ZP 
281
constant ZPTRB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000010"; -- 0x14 TRB ZP 
282
constant ZPTRB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000011"; -- 0x14 TRB ZP 
283
constant ZPTRB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000100"; -- 0x14 TRB ZP 
284
constant ZPTRB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000101"; -- 0x14 TRB ZP 
285
constant ZPTRB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101000110"; -- 0x14 TRB ZP 
286
 
287
------------------------------------
288
--          ZERO PAGE,X           --
289
------------------------------------
290
constant ZXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101010000"; -- 0xB5 LDA ZP,X
291
constant ZXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101010001"; -- 0xB5 LDA ZP,X
292
constant ZXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101010010"; -- 0xB5 LDA ZP,X
293
constant ZXLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101000000"; -- 0xB4 LDY ZP,X
294
constant ZXLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101000001"; -- 0xB4 LDY ZP,X
295
constant ZXLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101000010"; -- 0xB4 LDY ZP,X
296
constant ZXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101010000"; -- 0x95 STA ZP,X
297
constant ZXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101010001"; -- 0x95 STA ZP,X
298
constant ZXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101010010"; -- 0x95 STA ZP,X
299
constant ZXSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101000000"; -- 0x94 STY ZP,X
300
constant ZXSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101000001"; -- 0x94 STY ZP,X
301
constant ZXSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101000010"; -- 0x94 STY ZP,X
302
constant ZXSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101000000"; -- 0x74 STZ ZP,X
303
constant ZXSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101000001"; -- 0x74 STZ ZP,X
304
constant ZXSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101000010"; -- 0x74 STZ ZP,X
305
constant ZXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101010000"; -- 0x75 ADC ZP,X
306
constant ZXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101010001"; -- 0x75 ADC ZP,X
307
constant ZXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101010010"; -- 0x75 ADC ZP,X
308
constant ZXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101010000"; -- 0xF5 SBC ZP,X
309
constant ZXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101010001"; -- 0xF5 SBC ZP,X
310
constant ZXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101010010"; -- 0xF5 SBC ZP,X
311
constant ZXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101010000"; -- 0xD5 CMP ZP,X
312
constant ZXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101010001"; -- 0xD5 CMP ZP,X
313
constant ZXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101010010"; -- 0xD5 CMP ZP,X
314
constant ZXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101010000"; -- 0x35 AND ZP,X
315
constant ZXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101010001"; -- 0x35 AND ZP,X
316
constant ZXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101010010"; -- 0x35 AND ZP,X
317
constant ZXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101010000"; -- 0x15 ORA ZP,X
318
constant ZXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101010001"; -- 0x15 ORA ZP,X
319
constant ZXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101010010"; -- 0x15 ORA ZP,X
320
constant ZXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101010000"; -- 0x55 EOR ZP,X
321
constant ZXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101010001"; -- 0x55 EOR ZP,X
322
constant ZXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101010010"; -- 0x55 EOR ZP,X
323
constant ZXASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100000"; -- 0x16 ASL ZP,X
324
constant ZXASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100001"; -- 0x16 ASL ZP,X
325
constant ZXASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100010"; -- 0x16 ASL ZP,X
326
constant ZXASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100011"; -- 0x16 ASL ZP,X
327
constant ZXASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100100"; -- 0x16 ASL ZP,X
328
constant ZXASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101100101"; -- 0x16 ASL ZP,X
329
constant ZXLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100000"; -- 0x56 LSR ZP,X
330
constant ZXLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100001"; -- 0x56 LSR ZP,X
331
constant ZXLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100010"; -- 0x56 LSR ZP,X
332
constant ZXLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100011"; -- 0x56 LSR ZP,X
333
constant ZXLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100100"; -- 0x56 LSR ZP,X
334
constant ZXLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101100101"; -- 0x56 LSR ZP,X
335
constant ZXROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100000"; -- 0x36 ROL ZP,X
336
constant ZXROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100001"; -- 0x36 ROL ZP,X
337
constant ZXROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100010"; -- 0x36 ROL ZP,X
338
constant ZXROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100011"; -- 0x36 ROL ZP,X
339
constant ZXROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100100"; -- 0x36 ROL ZP,X
340
constant ZXROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101100101"; -- 0x36 ROL ZP,X
341
constant ZXROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100000"; -- 0x76 ROR ZP,X
342
constant ZXROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100001"; -- 0x76 ROR ZP,X
343
constant ZXROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100010"; -- 0x76 ROR ZP,X
344
constant ZXROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100011"; -- 0x76 ROR ZP,X
345
constant ZXROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100100"; -- 0x76 ROR ZP,X
346
constant ZXROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101100101"; -- 0x76 ROR ZP,X
347
constant ZXDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100000"; -- 0xD6 DEC ZP,X
348
constant ZXDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100001"; -- 0xD6 DEC ZP,X
349
constant ZXDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100010"; -- 0xD6 DEC ZP,X
350
constant ZXDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100011"; -- 0xD6 DEC ZP,X
351
constant ZXDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100100"; -- 0xD6 DEC ZP,X
352
constant ZXDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101100101"; -- 0xD6 DEC ZP,X
353
constant ZXINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100000"; -- 0xF6 INC ZP,X
354
constant ZXINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100001"; -- 0xF6 INC ZP,X
355
constant ZXINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100010"; -- 0xF6 INC ZP,X
356
constant ZXINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100011"; -- 0xF6 INC ZP,X
357
constant ZXINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100100"; -- 0xF6 INC ZP,X
358
constant ZXINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101100101"; -- 0xF6 INC ZP,X
359
constant ZXBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101000000"; -- 0x34 BIT ZP,X
360
constant ZXBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101000001"; -- 0x34 BIT ZP,X
361
constant ZXBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101000010"; -- 0x34 BIT ZP,X
362
 
363
------------------------------------
364
--          ZERO PAGE,Y           --
365
------------------------------------
366
constant ZYLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101100000"; -- 0xB6 LDX ZP,Y
367
constant ZYLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101100001"; -- 0xB6 LDX ZP,Y
368
constant ZYLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101100010"; -- 0xB6 LDX ZP,Y
369
constant ZYLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101100011"; -- 0xB6 LDX ZP,Y
370
 
371
constant ZYSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101100000"; -- 0x96 STX ZP,Y
372
constant ZYSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101100001"; -- 0x96 STX ZP,Y
373
constant ZYSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101100010"; -- 0x96 STX ZP,Y
374
 
375
------------------------------------
376
--           INDIRECT             --
377
------------------------------------
378
constant INJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011000000"; -- 0x6C JMP (IND)
379
constant INJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011000001"; -- 0x6C JMP (IND)
380
constant INJMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011000010"; -- 0x6C JMP (IND)
381
constant INJMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011000011"; -- 0x6C JMP (IND)
382
constant INJML_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111000000"; -- 0xDC JML (IND)
383
constant INJML_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111000001"; -- 0xDC JML (IND)
384
constant INJML_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111000010"; -- 0xDC JML (IND)
385
constant INJML_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111000011"; -- 0xDC JML (IND)
386
constant INJML_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111000100"; -- 0xDC JML (IND)
387
 
388
 
389
------------------------------------
390
--          INDIRECT,Y            --
391
------------------------------------
392
constant IYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010000"; -- 0xB1 LDA [DIR],Y
393
constant IYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010001"; -- 0xB1 LDA [DIR],Y
394
constant IYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010010"; -- 0xB1 LDA [DIR],Y
395
constant IYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010011"; -- 0xB1 LDA [DIR],Y
396
constant IYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010100"; -- 0xB1 LDA [DIR],Y
397
constant IYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100010101"; -- 0xB1 LDA [DIR],Y
398
constant IYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010000"; -- 0x91 STA [DIR],Y
399
constant IYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010001"; -- 0x91 STA [DIR],Y
400
constant IYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010010"; -- 0x91 STA [DIR],Y
401
constant IYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010011"; -- 0x91 STA [DIR],Y
402
constant IYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010100"; -- 0x91 STA [DIR],Y
403
constant IYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100010101"; -- 0x91 STA [DIR],Y
404
constant IYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010000"; -- 0x71 ADC [DIR],Y
405
constant IYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010001"; -- 0x71 ADC [DIR],Y
406
constant IYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010010"; -- 0x71 ADC [DIR],Y
407
constant IYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010011"; -- 0x71 ADC [DIR],Y
408
constant IYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010100"; -- 0x71 ADC [DIR],Y
409
constant IYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100010101"; -- 0x71 ADC [DIR],Y
410
constant IYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010000"; -- 0xF1 SBC [DIR],Y
411
constant IYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010001"; -- 0xF1 SBC [DIR],Y
412
constant IYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010010"; -- 0xF1 SBC [DIR],Y
413
constant IYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010011"; -- 0xF1 SBC [DIR],Y
414
constant IYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010100"; -- 0xF1 SBC [DIR],Y
415
constant IYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100010101"; -- 0xF1 SBC [DIR],Y
416
constant IYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010000"; -- 0xD1 CMP [DIR],Y
417
constant IYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010001"; -- 0xD1 CMP [DIR],Y
418
constant IYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010010"; -- 0xD1 CMP [DIR],Y
419
constant IYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010011"; -- 0xD1 CMP [DIR],Y
420
constant IYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010100"; -- 0xD1 CMP [DIR],Y
421
constant IYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100010101"; -- 0xD1 CMP [DIR],Y
422
constant IYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010000"; -- 0x31 AND [DIR],Y
423
constant IYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010001"; -- 0x31 AND [DIR],Y
424
constant IYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010010"; -- 0x31 AND [DIR],Y
425
constant IYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010011"; -- 0x31 AND [DIR],Y
426
constant IYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010100"; -- 0x31 AND [DIR],Y
427
constant IYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100010101"; -- 0x31 AND [DIR],Y
428
constant IYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010000"; -- 0x11 ORA [DIR],Y
429
constant IYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010001"; -- 0x11 ORA [DIR],Y
430
constant IYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010010"; -- 0x11 ORA [DIR],Y
431
constant IYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010011"; -- 0x11 ORA [DIR],Y
432
constant IYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010100"; -- 0x11 ORA [DIR],Y
433
constant IYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100010101"; -- 0x11 ORA [DIR],Y
434
constant IYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010000"; -- 0x51 EOR [DIR],Y
435
constant IYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010001"; -- 0x51 EOR [DIR],Y
436
constant IYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010010"; -- 0x51 EOR [DIR],Y
437
constant IYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010011"; -- 0x51 EOR [DIR],Y
438
constant IYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010100"; -- 0x51 EOR [DIR],Y
439
constant IYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100010101"; -- 0x51 EOR [DIR],Y
440
 
441
------------------------------------
442
--          INDIRECT,X            --
443
------------------------------------
444
constant IXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000010000"; -- 0xA1 LDA (IND_ZP,X)
445
constant IXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000010001"; -- 0xA1 LDA (IND_ZP,X)
446
constant IXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000010010"; -- 0xA1 LDA (IND_ZP,X)
447
constant IXLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000010011"; -- 0xA1 LDA (IND_ZP,X)
448
constant IXLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000010100"; -- 0xA1 LDA (IND_ZP,X)
449
constant IXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000010000"; -- 0x81 STA (IND_ZP,X)
450
constant IXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000010001"; -- 0x81 STA (IND_ZP,X)
451
constant IXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000010010"; -- 0x81 STA (IND_ZP,X)
452
constant IXSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000010011"; -- 0x81 STA (IND_ZP,X)
453
constant IXSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000010100"; -- 0x81 STA (IND_ZP,X)
454
constant IXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000010000"; -- 0x21 AND (IND_ZP,X)
455
constant IXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000010001"; -- 0x21 AND (IND_ZP,X)
456
constant IXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000010010"; -- 0x21 AND (IND_ZP,X)
457
constant IXAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000010011"; -- 0x21 AND (IND_ZP,X)
458
constant IXAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000010100"; -- 0x21 AND (IND_ZP,X)
459
constant IXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000010000"; -- 0x01 ORA (IND_ZP,X)
460
constant IXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000010001"; -- 0x01 ORA (IND_ZP,X)
461
constant IXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000010010"; -- 0x01 ORA (IND_ZP,X)
462
constant IXORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000010011"; -- 0x01 ORA (IND_ZP,X)
463
constant IXORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000010100"; -- 0x01 ORA (IND_ZP,X)
464
constant IXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000010000"; -- 0x41 EOR (IND_ZP,X)
465
constant IXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000010001"; -- 0x41 EOR (IND_ZP,X)
466
constant IXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000010010"; -- 0x41 EOR (IND_ZP,X)
467
constant IXEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000010011"; -- 0x41 EOR (IND_ZP,X)
468
constant IXEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000010100"; -- 0x41 EOR (IND_ZP,X)
469
constant IXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000010000"; -- 0xC1 CMP (IND_ZP,X)
470
constant IXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000010001"; -- 0xC1 CMP (IND_ZP,X)
471
constant IXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000010010"; -- 0xC1 CMP (IND_ZP,X)
472
constant IXCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000010011"; -- 0xC1 CMP (IND_ZP,X)
473
constant IXCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000010100"; -- 0xC1 CMP (IND_ZP,X)
474
constant IXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000010000"; -- 0x61 ADC (IND_ZP,X)
475
constant IXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000010001"; -- 0x61 ADC (IND_ZP,X)
476
constant IXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000010010"; -- 0x61 ADC (IND_ZP,X)
477
constant IXADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000010011"; -- 0x61 ADC (IND_ZP,X)
478
constant IXADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000010100"; -- 0x61 ADC (IND_ZP,X)
479
constant IXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000010000"; -- 0xE1 SBC (IND_ZP,X)
480
constant IXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000010001"; -- 0xE1 SBC (IND_ZP,X)
481
constant IXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000010010"; -- 0xE1 SBC (IND_ZP,X)
482
constant IXSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000010011"; -- 0xE1 SBC (IND_ZP,X)
483
constant IXSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000010100"; -- 0xE1 SBC (IND_ZP,X)
484
constant IXJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111000000"; -- 0x7C JMP (IND,X)
485
constant IXJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111000001"; -- 0x7C JMP (IND,X)
486
constant IXJMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111000010"; -- 0x7C JMP (IND,X)
487
constant IXJMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111000011"; -- 0x7C JMP (IND,X)
488
constant IXJMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111000100"; -- 0x7C JMP (IND,X)
489
constant IXJSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000000"; -- 0xFC JSR (IND,X)
490
constant IXJSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000001"; -- 0xFC JSR (IND,X)
491
constant IXJSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000010"; -- 0xFC JSR (IND,X)
492
constant IXJSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000011"; -- 0xFC JSR (IND,X)
493
constant IXJSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000100"; -- 0xFC JSR (IND,X)
494
constant IXJSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111000101"; -- 0xFC JSR (IND,X)
495
 
496
------------------------------------
497
--            ABSOLUTE            --
498
------------------------------------
499
constant ABLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011010000"; -- 0xAD LDA ABS
500
constant ABLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011010001"; -- 0xAD LDA ABS
501
constant ABLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011010010"; -- 0xAD LDA ABS
502
constant ABLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011010011"; -- 0xAD LDA ABS
503
constant ABLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011100000"; -- 0xAE LDX ABS
504
constant ABLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011100001"; -- 0xAE LDX ABS
505
constant ABLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011100010"; -- 0xAE LDX ABS
506
constant ABLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011100011"; -- 0xAE LDX ABS
507
constant ABLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011000000"; -- 0xAC LDY ABS
508
constant ABLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011000001"; -- 0xAC LDY ABS
509
constant ABLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011000010"; -- 0xAC LDY ABS
510
constant ABLDY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011000011"; -- 0xAC LDY ABS
511
constant ABSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011010000"; -- 0x8D STA ABS
512
constant ABSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011010001"; -- 0x8D STA ABS
513
constant ABSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011010010"; -- 0x8D STA ABS
514
constant ABSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011010011"; -- 0x8D STA ABS
515
constant ABSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011100000"; -- 0x8E STX ABS
516
constant ABSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011100001"; -- 0x8E STX ABS
517
constant ABSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011100010"; -- 0x8E STX ABS
518
constant ABSTX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011100011"; -- 0x8E STX ABS
519
constant ABSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011000000"; -- 0x8C STY ABS
520
constant ABSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011000001"; -- 0x8C STY ABS
521
constant ABSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011000010"; -- 0x8C STY ABS
522
constant ABSTY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011000011"; -- 0x8C STY ABS
523
constant ABSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111000000"; -- 0x9C STZ ABS
524
constant ABSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111000001"; -- 0x9C STZ ABS
525
constant ABSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111000010"; -- 0x9C STZ ABS
526
constant ABSTZ_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111000011"; -- 0x9C STZ ABS
527
constant ABADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011010000"; -- 0x6D ADC ABS
528
constant ABADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011010001"; -- 0x6D ADC ABS
529
constant ABADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011010010"; -- 0x6D ADC ABS
530
constant ABADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011010011"; -- 0x6D ADC ABS
531
constant ABADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011010100"; -- 0x6D ADC ABS
532
constant ABSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011010000"; -- 0xED SBC ABS
533
constant ABSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011010001"; -- 0xED SBC ABS
534
constant ABSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011010010"; -- 0xED SBC ABS
535
constant ABSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011010011"; -- 0xED SBC ABS
536
constant ABSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011010100"; -- 0xED SBC ABS
537
constant ABORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011010000"; -- 0x0D ORA ABS
538
constant ABORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011010001"; -- 0x0D ORA ABS
539
constant ABORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011010010"; -- 0x0D ORA ABS
540
constant ABORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011010011"; -- 0x0D ORA ABS
541
constant ABAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011010000"; -- 0x2D AND ABS
542
constant ABAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011010001"; -- 0x2D AND ABS
543
constant ABAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011010010"; -- 0x2D AND ABS
544
constant ABAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011010011"; -- 0x2D AND ABS
545
constant ABEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011010000"; -- 0x4D EOR ABS
546
constant ABEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011010001"; -- 0x4D EOR ABS
547
constant ABEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011010010"; -- 0x4D EOR ABS
548
constant ABEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011010011"; -- 0x4D EOR ABS
549
constant ABCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011010000"; -- 0xCD CMP ABS
550
constant ABCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011010001"; -- 0xCD CMP ABS
551
constant ABCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011010010"; -- 0xCD CMP ABS
552
constant ABCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011010011"; -- 0xCD CMP ABS
553
constant ABCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011000000"; -- 0xEC CPX ABS
554
constant ABCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011000001"; -- 0xEC CPX ABS
555
constant ABCPX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011000010"; -- 0xEC CPX ABS
556
constant ABCPX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011000011"; -- 0xEC CPX ABS
557
constant ABCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011000000"; -- 0xCC CPY ABS
558
constant ABCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011000001"; -- 0xCC CPY ABS
559
constant ABCPY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011000010"; -- 0xCC CPY ABS
560
constant ABCPY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011000011"; -- 0xCC CPY ABS
561
constant ABJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011000000"; -- 0x4C JMP ABS
562
constant ABJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011000001"; -- 0x4C JMP ABS
563
constant ABJSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000000000"; -- 0x20 JSR ABS
564
constant ABJSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000000001"; -- 0x20 JSR ABS
565
constant ABJSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000000010"; -- 0x20 JSR ABS
566
constant ABJSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000000011"; -- 0x20 JSR ABS
567
constant ABBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011000000"; -- 0x2C BIT ABS
568
constant ABBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011000001"; -- 0x2C BIT ABS
569
constant ABBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011000010"; -- 0x2C BIT ABS
570
constant ABBIT_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011000011"; -- 0x2C BIT ABS
571
constant ABASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100000"; -- 0x0E ASL ABS
572
constant ABASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100001"; -- 0x0E ASL ABS
573
constant ABASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100010"; -- 0x0E ASL ABS
574
constant ABASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100011"; -- 0x0E ASL ABS
575
constant ABASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100100"; -- 0x0E ASL ABS
576
constant ABASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100101"; -- 0x0E ASL ABS
577
constant ABASL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011100110"; -- 0x0E ASL ABS
578
constant ABLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100000"; -- 0x4E LSR ABS
579
constant ABLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100001"; -- 0x4E LSR ABS
580
constant ABLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100010"; -- 0x4E LSR ABS
581
constant ABLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100011"; -- 0x4E LSR ABS
582
constant ABLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100100"; -- 0x4E LSR ABS
583
constant ABLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100101"; -- 0x4E LSR ABS
584
constant ABLSR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011100110"; -- 0x4E LSR ABS
585
constant ABROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100000"; -- 0x2E ROL ABS
586
constant ABROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100001"; -- 0x2E ROL ABS
587
constant ABROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100010"; -- 0x2E ROL ABS
588
constant ABROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100011"; -- 0x2E ROL ABS
589
constant ABROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100100"; -- 0x2E ROL ABS
590
constant ABROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100101"; -- 0x2E ROL ABS
591
constant ABROL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011100110"; -- 0x2E ROL ABS
592
constant ABROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100000"; -- 0x6E ROR ABS
593
constant ABROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100001"; -- 0x6E ROR ABS
594
constant ABROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100010"; -- 0x6E ROR ABS
595
constant ABROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100011"; -- 0x6E ROR ABS
596
constant ABROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100100"; -- 0x6E ROR ABS
597
constant ABROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100101"; -- 0x6E ROR ABS
598
constant ABROR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011100110"; -- 0x6E ROR ABS
599
constant ABINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100000"; -- 0xEE INC ABS
600
constant ABINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100001"; -- 0xEE INC ABS
601
constant ABINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100010"; -- 0xEE INC ABS
602
constant ABINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100011"; -- 0xEE INC ABS
603
constant ABINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100100"; -- 0xEE INC ABS
604
constant ABINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100101"; -- 0xEE INC ABS
605
constant ABINC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011100110"; -- 0xEE INC ABS
606
constant ABDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100000"; -- 0xCE DEC ABS
607
constant ABDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100001"; -- 0xCE DEC ABS
608
constant ABDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100010"; -- 0xCE DEC ABS
609
constant ABDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100011"; -- 0xCE DEC ABS
610
constant ABDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100100"; -- 0xCE DEC ABS
611
constant ABDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100101"; -- 0xCE DEC ABS
612
constant ABDEC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011100110"; -- 0xCE DEC ABS
613
constant ABTSB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000000"; -- 0x0C TSB ABS
614
constant ABTSB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000001"; -- 0x0C TSB ABS
615
constant ABTSB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000010"; -- 0x0C TSB ABS
616
constant ABTSB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000011"; -- 0x0C TSB ABS
617
constant ABTSB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000100"; -- 0x0C TSB ABS
618
constant ABTSB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000101"; -- 0x0C TSB ABS
619
constant ABTSB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000110"; -- 0x0C TSB ABS
620
constant ABTSB_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011000111"; -- 0x0C TSB ABS
621
constant ABTRB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000000"; -- 0x1C TRB ABS
622
constant ABTRB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000001"; -- 0x1C TRB ABS
623
constant ABTRB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000010"; -- 0x1C TRB ABS
624
constant ABTRB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000011"; -- 0x1C TRB ABS
625
constant ABTRB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000100"; -- 0x1C TRB ABS
626
constant ABTRB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000101"; -- 0x1C TRB ABS
627
constant ABTRB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000110"; -- 0x1C TRB ABS
628
constant ABTRB_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111000111"; -- 0x1C TRB ABS
629
 
630
------------------------------------
631
--           ABSOLUTE,X           --
632
------------------------------------
633
constant AXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111010000"; -- 0xBD LDA ABS,X
634
constant AXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111010001"; -- 0xBD LDA ABS,X
635
constant AXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111010010"; -- 0xBD LDA ABS,X
636
constant AXLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111010011"; -- 0xBD LDA ABS,X
637
constant AXLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111000000"; -- 0xBC LDY ABS,X
638
constant AXLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111000001"; -- 0xBC LDY ABS,X
639
constant AXLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111000010"; -- 0xBC LDY ABS,X
640
constant AXLDY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111000011"; -- 0xBC LDY ABS,X
641
constant AXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111010000"; -- 0x9D STA ABS,X
642
constant AXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111010001"; -- 0x9D STA ABS,X
643
constant AXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111010010"; -- 0x9D STA ABS,X
644
constant AXSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111010011"; -- 0x9D STA ABS,X
645
constant AXSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111100000"; -- 0x9E STZ ABS,X
646
constant AXSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111100001"; -- 0x9E STZ ABS,X
647
constant AXSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111100010"; -- 0x9E STZ ABS,X
648
constant AXSTZ_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111100011"; -- 0x9E STZ ABS,X
649
constant AXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111010000"; -- 0x7D ADC ABS,X
650
constant AXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111010001"; -- 0x7D ADC ABS,X
651
constant AXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111010010"; -- 0x7D ADC ABS,X
652
constant AXADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111010011"; -- 0x7D ADC ABS,X
653
constant AXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111010000"; -- 0xFD SBC ABS,X
654
constant AXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111010001"; -- 0xFD SBC ABS,X
655
constant AXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111010010"; -- 0xFD SBC ABS,X
656
constant AXSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111010011"; -- 0xFD SBC ABS,X
657
constant AXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111010000"; -- 0xDD CMP ABS,X
658
constant AXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111010001"; -- 0xDD CMP ABS,X
659
constant AXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111010010"; -- 0xDD CMP ABS,X
660
constant AXCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111010011"; -- 0xDD CMP ABS,X
661
constant AXINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100000"; -- 0xFE INC ABS,X
662
constant AXINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100001"; -- 0xFE INC ABS,X
663
constant AXINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100010"; -- 0xFE INC ABS,X
664
constant AXINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100011"; -- 0xFE INC ABS,X
665
constant AXINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100100"; -- 0xFE INC ABS,X
666
constant AXINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100101"; -- 0xFE INC ABS,X
667
constant AXINC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111100110"; -- 0xFE INC ABS,X
668
constant AXDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100000"; -- 0xDE DEC ABS,X
669
constant AXDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100001"; -- 0xDE DEC ABS,X
670
constant AXDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100010"; -- 0xDE DEC ABS,X
671
constant AXDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100011"; -- 0xDE DEC ABS,X
672
constant AXDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100100"; -- 0xDE DEC ABS,X
673
constant AXDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100101"; -- 0xDE DEC ABS,X
674
constant AXDEC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111100110"; -- 0xDE DEC ABS,X
675
constant AXASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100000"; -- 0x1E ASL ABS,X
676
constant AXASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100001"; -- 0x1E ASL ABS,X
677
constant AXASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100010"; -- 0x1E ASL ABS,X
678
constant AXASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100011"; -- 0x1E ASL ABS,X
679
constant AXASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100100"; -- 0x1E ASL ABS,X
680
constant AXASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100101"; -- 0x1E ASL ABS,X
681
constant AXASL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111100110"; -- 0x1E ASL ABS,X
682
constant AXLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100000"; -- 0x5E LSR ABS,X
683
constant AXLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100001"; -- 0x5E LSR ABS,X
684
constant AXLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100010"; -- 0x5E LSR ABS,X
685
constant AXLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100011"; -- 0x5E LSR ABS,X
686
constant AXLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100100"; -- 0x5E LSR ABS,X
687
constant AXLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100101"; -- 0x5E LSR ABS,X
688
constant AXLSR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111100110"; -- 0x5E LSR ABS,X
689
constant AXROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100000"; -- 0x3E ROL ABS,X
690
constant AXROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100001"; -- 0x3E ROL ABS,X
691
constant AXROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100010"; -- 0x3E ROL ABS,X
692
constant AXROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100011"; -- 0x3E ROL ABS,X
693
constant AXROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100100"; -- 0x3E ROL ABS,X
694
constant AXROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100101"; -- 0x3E ROL ABS,X
695
constant AXROL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111100110"; -- 0x3E ROL ABS,X
696
constant AXROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100000"; -- 0x7E ROR ABS,X
697
constant AXROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100001"; -- 0x7E ROR ABS,X
698
constant AXROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100010"; -- 0x7E ROR ABS,X
699
constant AXROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100011"; -- 0x7E ROR ABS,X
700
constant AXROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100100"; -- 0x7E ROR ABS,X
701
constant AXROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100101"; -- 0x7E ROR ABS,X
702
constant AXROR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111100110"; -- 0x7E ROR ABS,X
703
constant AXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111010000"; -- 0x3D AND ABS,X
704
constant AXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111010001"; -- 0x3D AND ABS,X
705
constant AXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111010010"; -- 0x3D AND ABS,X
706
constant AXAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111010011"; -- 0x3D AND ABS,X
707
constant AXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111010000"; -- 0x1D ORA ABS,X
708
constant AXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111010001"; -- 0x1D ORA ABS,X
709
constant AXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111010010"; -- 0x1D ORA ABS,X
710
constant AXORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111010011"; -- 0x1D ORA ABS,X
711
constant AXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111010000"; -- 0x5D EOR ABS,X
712
constant AXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111010001"; -- 0x5D EOR ABS,X
713
constant AXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111010010"; -- 0x5D EOR ABS,X
714
constant AXEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111010011"; -- 0x5D EOR ABS,X
715
constant AXBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111000000"; -- 0x3C BIT ABS,X
716
constant AXBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111000001"; -- 0x3C BIT ABS,X
717
constant AXBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111000010"; -- 0x3C BIT ABS,X
718
constant AXBIT_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111000011"; -- 0x3C BIT ABS,X
719
 
720
------------------------------------
721
--           ABSOLUTE,Y           --
722
------------------------------------
723
constant AYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110010000"; -- 0xB9 LDA ABS,Y
724
constant AYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110010001"; -- 0xB9 LDA ABS,Y
725
constant AYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110010010"; -- 0xB9 LDA ABS,Y
726
constant AYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101110010011"; -- 0xB9 LDA ABS,Y
727
constant AYLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111100000"; -- 0xBE LDX ABS,Y
728
constant AYLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111100001"; -- 0xBE LDX ABS,Y
729
constant AYLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111100010"; -- 0xBE LDX ABS,Y
730
constant AYLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111100011"; -- 0xBE LDX ABS,Y
731
constant AYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110010000"; -- 0x99 STA ABS,Y
732
constant AYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110010001"; -- 0x99 STA ABS,Y
733
constant AYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110010010"; -- 0x99 STA ABS,Y
734
constant AYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100110010011"; -- 0x99 STA ABS,Y
735
constant AYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110010000"; -- 0x79 ADC ABS,Y
736
constant AYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110010001"; -- 0x79 ADC ABS,Y
737
constant AYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110010010"; -- 0x79 ADC ABS,Y
738
constant AYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110010011"; -- 0x79 ADC ABS,Y
739
constant AYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011110010100"; -- 0x79 ADC ABS,Y
740
constant AYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110010000"; -- 0xF9 SBC ABS,Y
741
constant AYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110010001"; -- 0xF9 SBC ABS,Y
742
constant AYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110010010"; -- 0xF9 SBC ABS,Y
743
constant AYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110010011"; -- 0xF9 SBC ABS,Y
744
constant AYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111110010100"; -- 0xF9 SBC ABS,Y
745
constant AYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110010000"; -- 0xD9 CMP ABS,Y
746
constant AYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110010001"; -- 0xD9 CMP ABS,Y
747
constant AYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110010010"; -- 0xD9 CMP ABS,Y
748
constant AYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110110010011"; -- 0xD9 CMP ABS,Y
749
constant AYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110010000"; -- 0x19 ORA ABS,Y
750
constant AYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110010001"; -- 0x19 ORA ABS,Y
751
constant AYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110010010"; -- 0x19 ORA ABS,Y
752
constant AYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000110010011"; -- 0x19 ORA ABS,Y
753
constant AYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110010000"; -- 0x39 AND ABS,Y
754
constant AYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110010001"; -- 0x39 AND ABS,Y
755
constant AYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110010010"; -- 0x39 AND ABS,Y
756
constant AYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001110010011"; -- 0x39 AND ABS,Y
757
constant AYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110010000"; -- 0x59 EOR ABS,Y
758
constant AYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110010001"; -- 0x59 EOR ABS,Y
759
constant AYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110010010"; -- 0x59 EOR ABS,Y
760
constant AYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010110010011"; -- 0x59 EOR ABS,Y
761
 
762
------------------------------------------------
763
--           ABSOLUTE LONG (JUMP...)          --
764
------------------------------------------------
765
constant ABJML_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111000000"; -- 0x5C JML ABS
766
constant ABJML_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111000001"; -- 0x5C JML ABS
767
constant ABJML_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111000010"; -- 0x5C JML ABS
768
constant ABJSL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100000"; -- 0x22 JSL ABS
769
constant ABJSL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100001"; -- 0x22 JSL ABS
770
constant ABJSL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100010"; -- 0x22 JSL ABS
771
constant ABJSL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100011"; -- 0x22 JSL ABS
772
constant ABJSL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100100"; -- 0x22 JSL ABS
773
constant ABJSL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000100101"; -- 0x22 JSL ABS
774
 
775
------------------------------------
776
--           RELATIVE             --
777
------------------------------------
778
constant   BRA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000000000"; -- 0x80 BRA       
779
constant   BCC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100000000"; -- 0x90 BCC       
780
constant   BCS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100000000"; -- 0xB0 BCS       
781
constant   BEQ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100000000"; -- 0xF0 BEQ       
782
constant   BNE_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100000000"; -- 0xD0 BNE       
783
constant   BPL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100000000"; -- 0x10 BPL       
784
constant   BMI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100000000"; -- 0x30 BMI       
785
constant   BVC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100000000"; -- 0x50 BVC       
786
constant   BVS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100000000"; -- 0x70 BVS       
787
 
788
---------------------------------------
789
--           RELATIVE LONG           --
790
---------------------------------------
791
constant   BRL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000100000"; -- 0x82 BRL       
792
constant   BRL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000100001"; -- 0x82 BRL       
793
 
794
-------------------------------
795
--           STACK           --
796
-------------------------------
797
constant   PEA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101000000"; -- 0xF4 PEA
798
constant   PEA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101000001"; -- 0xF4 PEA
799
constant   PEA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101000010"; -- 0xF4 PEA
800
constant   PEA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101000011"; -- 0xF4 PEA
801
constant   PEI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101000000"; -- 0xD4 PEI
802
constant   PEI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101000001"; -- 0xD4 PEI
803
constant   PEI_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101000010"; -- 0xD4 PEI
804
constant   PEI_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101000011"; -- 0xD4 PEI
805
constant   PEI_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101000100"; -- 0xD4 PEI
806
constant   PER_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000100000"; -- 0x62 PER
807
constant   PER_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000100001"; -- 0x62 PER
808
constant   PER_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000100010"; -- 0x62 PER
809
constant   PER_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000100011"; -- 0x62 PER
810
constant   PER_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000100100"; -- 0x62 PER
811
 
812
----------------------------------
813
--          DIRECT,Y            --
814
----------------------------------
815
constant DYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110000"; -- 0xB7 LDA [DIR],Y
816
constant DYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110001"; -- 0xB7 LDA [DIR],Y
817
constant DYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110010"; -- 0xB7 LDA [IND],Y
818
constant DYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110011"; -- 0xB7 LDA [DIR],Y
819
constant DYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110100"; -- 0xB7 LDA [DIR],Y
820
constant DYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110101"; -- 0xB7 LDA [DIR],Y
821
constant DYLDA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101101110110"; -- 0xB7 LDA [DIR],Y
822
constant DYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110000"; -- 0x97 STA [DIR],Y
823
constant DYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110001"; -- 0x97 STA [DIR],Y
824
constant DYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110010"; -- 0x97 STA [DIR],Y
825
constant DYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110011"; -- 0x97 STA [DIR],Y
826
constant DYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110100"; -- 0x97 STA [DIR],Y
827
constant DYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110101"; -- 0x97 STA [DIR],Y
828
constant DYSTA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100101110110"; -- 0x97 STA [DIR],Y
829
constant DYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110000"; -- 0x77 ADC [DIR],Y
830
constant DYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110001"; -- 0x77 ADC [DIR],Y
831
constant DYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110010"; -- 0x77 ADC [DIR],Y
832
constant DYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110011"; -- 0x77 ADC [DIR],Y
833
constant DYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110100"; -- 0x77 ADC [DIR],Y
834
constant DYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110101"; -- 0x77 ADC [DIR],Y
835
constant DYADC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011101110110"; -- 0x77 ADC [DIR],Y
836
constant DYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110000"; -- 0xF7 SBC [DIR],Y
837
constant DYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110001"; -- 0xF7 SBC [DIR],Y
838
constant DYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110010"; -- 0xF7 SBC [DIR],Y
839
constant DYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110011"; -- 0xF7 SBC [DIR],Y
840
constant DYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110100"; -- 0xF7 SBC [DIR],Y
841
constant DYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110101"; -- 0xF7 SBC [DIR],Y
842
constant DYSBC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111101110110"; -- 0xF7 SBC [DIR],Y
843
constant DYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110000"; -- 0xD7 CMP [DIR],Y
844
constant DYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110001"; -- 0xD7 CMP [DIR],Y
845
constant DYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110010"; -- 0xD7 CMP [DIR],Y
846
constant DYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110011"; -- 0xD7 CMP [DIR],Y
847
constant DYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110100"; -- 0xD7 CMP [DIR],Y
848
constant DYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110101"; -- 0xD7 CMP [DIR],Y
849
constant DYCMP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110101110110"; -- 0xD7 CMP [DIR],Y
850
constant DYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110000"; -- 0x37 AND [DIR],Y
851
constant DYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110001"; -- 0x37 AND [DIR],Y
852
constant DYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110010"; -- 0x37 AND [DIR],Y
853
constant DYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110011"; -- 0x37 AND [DIR],Y
854
constant DYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110100"; -- 0x37 AND [DIR],Y
855
constant DYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110101"; -- 0x37 AND [DIR],Y
856
constant DYAND_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001101110110"; -- 0x37 AND [DIR],Y
857
constant DYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110000"; -- 0x17 ORA [DIR],Y
858
constant DYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110001"; -- 0x17 ORA [DIR],Y
859
constant DYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110010"; -- 0x17 ORA [DIR],Y
860
constant DYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110011"; -- 0x17 ORA [DIR],Y
861
constant DYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110100"; -- 0x17 ORA [DIR],Y
862
constant DYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110101"; -- 0x17 ORA [DIR],Y
863
constant DYORA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000101110110"; -- 0x17 ORA [DIR],Y
864
constant DYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110000"; -- 0x57 EOR [DIR],Y
865
constant DYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110001"; -- 0x57 EOR [DIR],Y
866
constant DYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110010"; -- 0x57 EOR [DIR],Y
867
constant DYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110011"; -- 0x57 EOR [DIR],Y
868
constant DYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110100"; -- 0x57 EOR [DIR],Y
869
constant DYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110101"; -- 0x57 EOR [DIR],Y
870
constant DYEOR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101110110"; -- 0x57 EOR [DIR],Y
871
 
872
--------------------------------
873
--          DIRECT            --
874
--------------------------------
875
constant DILDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110000"; -- 0xA7 LDA [DIR]
876
constant DILDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110001"; -- 0xA7 LDA [DIR]
877
constant DILDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110010"; -- 0xA7 LDA [IND]
878
constant DILDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110011"; -- 0xA7 LDA [DIR]
879
constant DILDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110100"; -- 0xA7 LDA [DIR]
880
constant DILDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101001110101"; -- 0xA7 LDA [DIR]
881
constant DISTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110000"; -- 0x87 STA [DIR]
882
constant DISTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110001"; -- 0x87 STA [DIR]
883
constant DISTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110010"; -- 0x87 STA [DIR]
884
constant DISTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110011"; -- 0x87 STA [DIR]
885
constant DISTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110100"; -- 0x87 STA [DIR]
886
constant DISTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100001110101"; -- 0x87 STA [DIR]
887
constant DIADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110000"; -- 0x67 ADC [DIR]
888
constant DIADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110001"; -- 0x67 ADC [DIR]
889
constant DIADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110010"; -- 0x67 ADC [DIR]
890
constant DIADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110011"; -- 0x67 ADC [DIR]
891
constant DIADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110100"; -- 0x67 ADC [DIR]
892
constant DIADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011001110101"; -- 0x67 ADC [DIR]
893
constant DISBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110000"; -- 0xE7 SBC [DIR]
894
constant DISBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110001"; -- 0xE7 SBC [DIR]
895
constant DISBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110010"; -- 0xE7 SBC [DIR]
896
constant DISBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110011"; -- 0xE7 SBC [DIR]
897
constant DISBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110100"; -- 0xE7 SBC [DIR]
898
constant DISBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111001110101"; -- 0xE7 SBC [DIR]
899
constant DICMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110000"; -- 0xC7 CMP [DIR]
900
constant DICMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110001"; -- 0xC7 CMP [DIR]
901
constant DICMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110010"; -- 0xC7 CMP [DIR]
902
constant DICMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110011"; -- 0xC7 CMP [DIR]
903
constant DICMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110100"; -- 0xC7 CMP [DIR]
904
constant DICMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110001110101"; -- 0xC7 CMP [DIR]
905
constant DIAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110000"; -- 0x27 AND [DIR]
906
constant DIAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110001"; -- 0x27 AND [DIR]
907
constant DIAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110010"; -- 0x27 AND [DIR]
908
constant DIAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110011"; -- 0x27 AND [DIR]
909
constant DIAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110100"; -- 0x27 AND [DIR]
910
constant DIAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001001110101"; -- 0x27 AND [DIR]
911
constant DIORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110000"; -- 0x07 ORA [DIR]
912
constant DIORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110001"; -- 0x07 ORA [DIR]
913
constant DIORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110010"; -- 0x07 ORA [DIR]
914
constant DIORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110011"; -- 0x07 ORA [DIR]
915
constant DIORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110100"; -- 0x07 ORA [DIR]
916
constant DIORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000001110101"; -- 0x07 ORA [DIR]
917
constant DIEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110000"; -- 0x47 EOR [DIR]
918
constant DIEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110001"; -- 0x47 EOR [DIR]
919
constant DIEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110010"; -- 0x47 EOR [DIR]
920
constant DIEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110011"; -- 0x47 EOR [DIR]
921
constant DIEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110100"; -- 0x47 EOR [DIR]
922
constant DIEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001110101"; -- 0x47 EOR [DIR]
923
 
924
----------------------------------------
925
--            ABSOLUTE LONG           --
926
----------------------------------------
927
constant ALLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011110000"; -- 0xAF LDA ABS_LONG
928
constant ALLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011110001"; -- 0xAF LDA ABS_LONG
929
constant ALLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011110010"; -- 0xAF LDA ABS_LONG
930
constant ALLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011110011"; -- 0xAF LDA ABS_LONG
931
constant ALLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101011110100"; -- 0xAF LDA ABS_LONG
932
constant ALSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011110000"; -- 0x8F STA ABS_LONG
933
constant ALSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011110001"; -- 0x8F STA ABS_LONG
934
constant ALSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011110010"; -- 0x8F STA ABS_LONG
935
constant ALSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011110011"; -- 0x8F STA ABS_LONG
936
constant ALSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100011110100"; -- 0x8F STA ABS_LONG
937
constant ALADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110000"; -- 0x6F ADC ABS_LONG
938
constant ALADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110001"; -- 0x6F ADC ABS_LONG
939
constant ALADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110010"; -- 0x6F ADC ABS_LONG
940
constant ALADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110011"; -- 0x6F ADC ABS_LONG
941
constant ALADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110100"; -- 0x6F ADC ABS_LONG
942
constant ALADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011011110101"; -- 0x6F ADC ABS_LONG
943
constant ALSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110000"; -- 0xEF SBC ABS_LONG
944
constant ALSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110001"; -- 0xEF SBC ABS_LONG
945
constant ALSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110010"; -- 0xEF SBC ABS_LONG
946
constant ALSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110011"; -- 0xEF SBC ABS_LONG
947
constant ALSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110100"; -- 0xEF SBC ABS_LONG
948
constant ALSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111011110101"; -- 0xEF SBC ABS_LONG
949
constant ALORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011110000"; -- 0x0F ORA ABS_LONG
950
constant ALORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011110001"; -- 0x0F ORA ABS_LONG
951
constant ALORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011110010"; -- 0x0F ORA ABS_LONG
952
constant ALORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011110011"; -- 0x0F ORA ABS_LONG
953
constant ALORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000011110100"; -- 0x0F ORA ABS_LONG
954
constant ALAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011110000"; -- 0x2F AND ABS_LONG
955
constant ALAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011110001"; -- 0x2F AND ABS_LONG
956
constant ALAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011110010"; -- 0x2F AND ABS_LONG
957
constant ALAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011110011"; -- 0x2F AND ABS_LONG
958
constant ALAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001011110100"; -- 0x2F AND ABS_LONG
959
constant ALEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011110000"; -- 0x4F EOR ABS_LONG
960
constant ALEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011110001"; -- 0x4F EOR ABS_LONG
961
constant ALEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011110010"; -- 0x4F EOR ABS_LONG
962
constant ALEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011110011"; -- 0x4F EOR ABS_LONG
963
constant ALEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010011110100"; -- 0x4F EOR ABS_LONG
964
constant ALCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011110000"; -- 0xCF CMP ABS_LONG
965
constant ALCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011110001"; -- 0xCF CMP ABS_LONG
966
constant ALCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011110010"; -- 0xCF CMP ABS_LONG
967
constant ALCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011110011"; -- 0xCF CMP ABS_LONG
968
constant ALCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110011110100"; -- 0xCF CMP ABS_LONG
969
 
970
-----------------------------------------
971
--           ABSOLUTE LONG,X           --
972
-----------------------------------------
973
constant AILDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110000"; -- 0xBF LDA ABS_LONG,X
974
constant AILDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110001"; -- 0xBF LDA ABS_LONG,X
975
constant AILDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110010"; -- 0xBF LDA ABS_LONG,X
976
constant AILDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110011"; -- 0xBF LDA ABS_LONG,X
977
constant AILDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110100"; -- 0xBF LDA ABS_LONG,X
978
constant AILDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101111110101"; -- 0xBF LDA ABS_LONG,X
979
constant AISTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110000"; -- 0x9F STA ABS_LONG,X
980
constant AISTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110001"; -- 0x9F STA ABS_LONG,X
981
constant AISTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110010"; -- 0x9F STA ABS_LONG,X
982
constant AISTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110011"; -- 0x9F STA ABS_LONG,X
983
constant AISTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110100"; -- 0x9F STA ABS_LONG,X
984
constant AISTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100111110101"; -- 0x9F STA ABS_LONG,X
985
constant AIADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110000"; -- 0x7F ADC ABS_LONG,X
986
constant AIADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110001"; -- 0x7F ADC ABS_LONG,X
987
constant AIADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110010"; -- 0x7F ADC ABS_LONG,X
988
constant AIADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110011"; -- 0x7F ADC ABS_LONG,X
989
constant AIADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110100"; -- 0x7F ADC ABS_LONG,X
990
constant AIADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011111110101"; -- 0x7F ADC ABS_LONG,X
991
constant AISBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110000"; -- 0xFF SBC ABS_LONG,X
992
constant AISBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110001"; -- 0xFF SBC ABS_LONG,X
993
constant AISBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110010"; -- 0xFF SBC ABS_LONG,X
994
constant AISBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110011"; -- 0xFF SBC ABS_LONG,X
995
constant AISBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110100"; -- 0xFF SBC ABS_LONG,X
996
constant AISBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111111110101"; -- 0xFF SBC ABS_LONG,X
997
constant AICMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110000"; -- 0xDF CMP ABS_LONG,X
998
constant AICMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110001"; -- 0xDF CMP ABS_LONG,X
999
constant AICMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110010"; -- 0xDF CMP ABS_LONG,X
1000
constant AICMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110011"; -- 0xDF CMP ABS_LONG,X
1001
constant AICMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110100"; -- 0xDF CMP ABS_LONG,X
1002
constant AICMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110111110101"; -- 0xDF CMP ABS_LONG,X
1003
constant AIAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110000"; -- 0x3F AND ABS_LONG,X
1004
constant AIAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110001"; -- 0x3F AND ABS_LONG,X
1005
constant AIAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110010"; -- 0x3F AND ABS_LONG,X
1006
constant AIAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110011"; -- 0x3F AND ABS_LONG,X
1007
constant AIAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110100"; -- 0x3F AND ABS_LONG,X
1008
constant AIAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001111110101"; -- 0x3F AND ABS_LONG,X
1009
constant AIORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110000"; -- 0x1F ORA ABS_LONG,X
1010
constant AIORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110001"; -- 0x1F ORA ABS_LONG,X
1011
constant AIORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110010"; -- 0x1F ORA ABS_LONG,X
1012
constant AIORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110011"; -- 0x1F ORA ABS_LONG,X
1013
constant AIORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110100"; -- 0x1F ORA ABS_LONG,X
1014
constant AIORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000111110101"; -- 0x1F ORA ABS_LONG,X
1015
constant AIEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110000"; -- 0x5F EOR ABS_LONG,X
1016
constant AIEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110001"; -- 0x5F EOR ABS_LONG,X
1017
constant AIEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110010"; -- 0x5F EOR ABS_LONG,X
1018
constant AIEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110011"; -- 0x5F EOR ABS_LONG,X
1019
constant AIEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110100"; -- 0x5F EOR ABS_LONG,X
1020
constant AIEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010111110101"; -- 0x5F EOR ABS_LONG,X
1021
 
1022
-----------------------------------------
1023
--            STACK RELATIVE           --
1024
-----------------------------------------
1025
constant SRLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000110000"; -- 0xA3 LDA $XX,S
1026
constant SRLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000110001"; -- 0xA3 LDA $XX,S
1027
constant SRLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101000110010"; -- 0xA3 LDA $XX,S
1028
constant SRSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000110000"; -- 0x83 STA $XX,S
1029
constant SRSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000110001"; -- 0x83 STA $XX,S
1030
constant SRSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100000110010"; -- 0x83 STA $XX,S
1031
constant SRADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000110000"; -- 0x63 ADC $XX,S
1032
constant SRADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000110001"; -- 0x63 ADC $XX,S
1033
constant SRADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011000110010"; -- 0x63 ADC $XX,S
1034
constant SRSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000110000"; -- 0xE3 SBC $XX,S
1035
constant SRSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000110001"; -- 0xE3 SBC $XX,S
1036
constant SRSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111000110010"; -- 0xE3 SBC $XX,S
1037
constant SRCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000110000"; -- 0xC3 CMP $XX,S
1038
constant SRCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000110001"; -- 0xC3 CMP $XX,S
1039
constant SRCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110000110010"; -- 0xC3 CMP $XX,S
1040
constant SRAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000110000"; -- 0x23 AND $XX,S
1041
constant SRAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000110001"; -- 0x23 AND $XX,S
1042
constant SRAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001000110010"; -- 0x23 AND $XX,S
1043
constant SRORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000110000"; -- 0x03 ORA $XX,S
1044
constant SRORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000110001"; -- 0x03 ORA $XX,S
1045
constant SRORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000000110010"; -- 0x03 ORA $XX,S
1046
constant SREOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000110000"; -- 0x43 EOR $XX,S
1047
constant SREOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000110001"; -- 0x43 EOR $XX,S
1048
constant SREOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010000110010"; -- 0x43 EOR $XX,S
1049
 
1050
--------------------------------------------------
1051
--            STACK RELATIVE INDEXED Y          --
1052
--------------------------------------------------
1053
constant SYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110000"; -- 0xB3 LDA ($XX,S),Y
1054
constant SYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110001"; -- 0xB3 LDA ($XX,S),Y
1055
constant SYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110010"; -- 0xB3 LDA ($XX,S),Y
1056
constant SYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110011"; -- 0xB3 LDA ($XX,S),Y
1057
constant SYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110100"; -- 0xB3 LDA ($XX,S),Y
1058
constant SYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0101100110101"; -- 0xB3 LDA ($XX,S),Y
1059
constant SYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110000"; -- 0x93 STA ($XX,S),Y
1060
constant SYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110001"; -- 0x93 STA ($XX,S),Y
1061
constant SYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110010"; -- 0x93 STA ($XX,S),Y
1062
constant SYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110011"; -- 0x93 STA ($XX,S),Y
1063
constant SYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110100"; -- 0x93 STA ($XX,S),Y
1064
constant SYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0100100110101"; -- 0x93 STA ($XX,S),Y
1065
constant SYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110000"; -- 0x73 ADC ($XX,S),Y
1066
constant SYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110001"; -- 0x73 ADC ($XX,S),Y
1067
constant SYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110010"; -- 0x73 ADC ($XX,S),Y
1068
constant SYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110011"; -- 0x73 ADC ($XX,S),Y
1069
constant SYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110100"; -- 0x73 ADC ($XX,S),Y
1070
constant SYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0011100110101"; -- 0x73 ADC ($XX,S),Y
1071
constant SYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110000"; -- 0xF3 SBC ($XX,S),Y
1072
constant SYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110001"; -- 0xF3 SBC ($XX,S),Y
1073
constant SYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110010"; -- 0xF3 SBC ($XX,S),Y
1074
constant SYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110011"; -- 0xF3 SBC ($XX,S),Y
1075
constant SYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110100"; -- 0xF3 SBC ($XX,S),Y
1076
constant SYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0111100110101"; -- 0xF3 SBC ($XX,S),Y
1077
constant SYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110000"; -- 0xD3 CMP ($XX,S),Y
1078
constant SYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110001"; -- 0xD3 CMP ($XX,S),Y
1079
constant SYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110010"; -- 0xD3 CMP ($XX,S),Y
1080
constant SYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110011"; -- 0xD3 CMP ($XX,S),Y
1081
constant SYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110100"; -- 0xD3 CMP ($XX,S),Y
1082
constant SYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0110100110101"; -- 0xD3 CMP ($XX,S),Y
1083
constant SYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110000"; -- 0x33 AND ($XX,S),Y
1084
constant SYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110001"; -- 0x33 AND ($XX,S),Y
1085
constant SYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110010"; -- 0x33 AND ($XX,S),Y
1086
constant SYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110011"; -- 0x33 AND ($XX,S),Y
1087
constant SYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110100"; -- 0x33 AND ($XX,S),Y
1088
constant SYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0001100110101"; -- 0x33 AND ($XX,S),Y
1089
constant SYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110000"; -- 0x13 ORA ($XX,S),Y
1090
constant SYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110001"; -- 0x13 ORA ($XX,S),Y
1091
constant SYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110010"; -- 0x13 ORA ($XX,S),Y
1092
constant SYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110011"; -- 0x13 ORA ($XX,S),Y
1093
constant SYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110100"; -- 0x13 ORA ($XX,S),Y
1094
constant SYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0000100110101"; -- 0x13 ORA ($XX,S),Y
1095
constant SYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110000"; -- 0x53 EOR ($XX,S),Y
1096
constant SYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110001"; -- 0x53 EOR ($XX,S),Y
1097
constant SYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110010"; -- 0x53 EOR ($XX,S),Y
1098
constant SYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110011"; -- 0x53 EOR ($XX,S),Y
1099
constant SYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110100"; -- 0x53 EOR ($XX,S),Y
1100
constant SYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010100110101"; -- 0x53 EOR ($XX,S),Y
1101
 
1102
------------------------------------
1103
--           MOVE BLOCK           --
1104
------------------------------------
1105
constant MBMVN_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000000"; -- 0x54 MVN $xx,$xx
1106
constant MBMVN_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000001"; -- 0x54 MVN $xx,$xx
1107
constant MBMVN_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000010"; -- 0x54 MVN $xx,$xx
1108
constant MBMVN_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000011"; -- 0x54 MVN $xx,$xx
1109
constant MBMVN_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000100"; -- 0x54 MVN $xx,$xx
1110
constant MBMVN_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000101"; -- 0x54 MVN $xx,$xx
1111
constant MBMVN_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000110"; -- 0x54 MVN $xx,$xx
1112
constant MBMVN_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010101000111"; -- 0x54 MVN $xx,$xx
1113
 
1114
constant MBMVP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000000"; -- 0x44 MVP $xx,$xx
1115
constant MBMVP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000001"; -- 0x44 MVP $xx,$xx
1116
constant MBMVP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000010"; -- 0x44 MVP $xx,$xx
1117
constant MBMVP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000011"; -- 0x44 MVP $xx,$xx
1118
constant MBMVP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000100"; -- 0x44 MVP $xx,$xx
1119
constant MBMVP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000101"; -- 0x44 MVP $xx,$xx
1120
constant MBMVP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000110"; -- 0x44 MVP $xx,$xx
1121
constant MBMVP_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "0010001000111"; -- 0x44 MVP $xx,$xx
1122
 
1123
-------------------------------------------------
1124
--           NEW OPCODES (WDM OPCODE)          --
1125
-------------------------------------------------
1126
-- IMPLIED
1127
constant   PHR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110000"; -- 0x8B PHR AXY->S (two byte instruction)
1128
constant   PHR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110001"; -- 0x8B PHR AXY->S (two byte instruction)
1129
constant   PHR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110010"; -- 0x8B PHR AXY->S (two byte instruction)
1130
constant   PHR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110011"; -- 0x8B PHR AXY->S (two byte instruction)
1131
constant   PHR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110100"; -- 0x8B PHR AXY->S (two byte instruction)
1132
constant   PHR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100010110101"; -- 0x8B PHR AXY->S (two byte instruction)
1133
 
1134
constant   PLR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110000"; -- 0xAB PLR S->YXA (two byte instruction)
1135
constant   PLR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110001"; -- 0xAB PLR S->YXA (two byte instruction)
1136
constant   PLR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110010"; -- 0xAB PLR S->YXA (two byte instruction)
1137
constant   PLR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110011"; -- 0xAB PLR S->YXA (two byte instruction)
1138
constant   PLR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110100"; -- 0xAB PLR S->YXA (two byte instruction)
1139
constant   PLR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110101"; -- 0xAB PLR S->YXA (two byte instruction)
1140
constant   PLR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1101010110110"; -- 0xAB PLR S->YXA (two byte instruction)
1141
 
1142
constant   SAV_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000000"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1143
constant   SAV_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000001"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1144
constant   SAV_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000010"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1145
constant   SAV_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000011"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1146
constant   SAV_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000100"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1147
constant   SAV_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000101"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1148
constant   SAV_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000110"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1149
constant   SAV_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100000111"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1150
constant   SAV_OP8: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100001000"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1151
constant   SAV_OP9: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100001001"; -- 0x90 SAV AXYBDP->S (two byte instruction)
1152
 
1153
constant   RST_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010000"; -- 0x91 RST S->PDBYXA (two byte instruction)
1154
constant   RST_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010001"; -- 0x91 RST S->PDBYXA (two byte instruction)
1155
constant   RST_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010010"; -- 0x91 RST S->PDBYXA (two byte instruction)
1156
constant   RST_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010011"; -- 0x91 RST S->PDBYXA (two byte instruction)
1157
constant   RST_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010100"; -- 0x91 RST S->PDBYXA (two byte instruction)
1158
constant   RST_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010101"; -- 0x91 RST S->PDBYXA (two byte instruction)
1159
constant   RST_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010110"; -- 0x91 RST S->PDBYXA (two byte instruction)
1160
constant   RST_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100010111"; -- 0x91 RST S->PDBYXA (two byte instruction)
1161
constant   RST_OP8: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100011000"; -- 0x91 RST S->PDBYXA (two byte instruction)
1162
constant   RST_OP9: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100011001"; -- 0x91 RST S->PDBYXA (two byte instruction)
1163
constant  RST_OP10: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100100011010"; -- 0x91 RST S->PDBYXA (two byte instruction)
1164
 
1165
-- MULTIPLY UNSIGNED 16X16->32 BIT
1166
constant   MPU_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011100000"; -- 0x8E MPU multiply A*X (two byte instruction)
1167
constant   MPU_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011100001"; -- 0x8E MPU multiply A*X (two byte instruction)
1168
constant   MPU_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011100010"; -- 0x8E MPU multiply A*X (two byte instruction)
1169
constant   MPU_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011100011"; -- 0x8E MPU multiply A*X (two byte instruction)
1170
 
1171
-- MULTIPLY SIGNED 16X16->32 BIT
1172
constant   MPS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011110000"; -- 0x8F MPS multiply A*X (two byte instruction)
1173
constant   MPS_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011110001"; -- 0x8F MPS multiply A*X (two byte instruction)
1174
constant   MPS_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011110010"; -- 0x8F MPS multiply A*X (two byte instruction)
1175
constant   MPS_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1100011110011"; -- 0x8F MPS multiply A*X (two byte instruction)
1176
 
1177
-- REGISTERS EXCHANGE
1178
constant   XYX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1111010110000"; -- 0xEB EXCHANGE X <-> Y (two byte instruction)
1179
constant   XYX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1111010110001"; -- 0xEB EXCHANGE X <-> Y (two byte instruction)
1180
constant   XYX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1111010110010"; -- 0xEB EXCHANGE X <-> Y (two byte instruction)
1181
constant   XAX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1000010110000"; -- 0x0B EXCHANGE A <-> X (two byte instruction)
1182
constant   XAX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1000010110001"; -- 0x0B EXCHANGE A <-> X (two byte instruction)
1183
constant   XAX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1000010110010"; -- 0x0B EXCHANGE A <-> X (two byte instruction)
1184
constant   XAY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1001010110000"; -- 0x2B EXCHANGE A <-> Y (two byte instruction)
1185
constant   XAY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1001010110001"; -- 0x2B EXCHANGE A <-> Y (two byte instruction)
1186
constant   XAY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1001010110010"; -- 0x2B EXCHANGE A <-> Y (two byte instruction)
1187
 
1188
-- MISC
1189
constant   EXT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1111011000000"; -- 0xEC EXTEND SIGN OF A TO B (two byte instruction)
1190
constant   NEG_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) :=  "1111011010000"; -- 0xED NEGATE A         (two byte instruction)
1191
 
1192
 
1193
-- ALU microcode
1194
constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000";    -- no operation
1195
constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001";    -- sum with carry
1196
constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010";    -- subtract with borrow
1197
constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011";    -- and
1198
constant  OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100";    -- or
1199
constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101";    -- xor
1200
constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110";    -- increment by 1
1201
constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111";    -- decrement by 1
1202
constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000";    -- shift left
1203
constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001";    -- shift right
1204
constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010";    -- rotation left
1205
constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011";    -- rotation right
1206
constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100";    -- sum without carry (used for indexing and branches)
1207
constant SWC_N: STD_LOGIC_VECTOR(4 downto 0) := "01100";    -- subtract without borrow (used only by branches with negative offset)
1208
constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101";    -- bit test (used by BIT opcode)
1209
constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110";    -- decimal adjustement for BCD sum
1210
constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111";    -- decimal adjustement for BCD subtract
1211
constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000";    -- compare
1212
constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001";    -- test and set bit
1213
constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010";    -- test and reset bit
1214
constant EXT_A: STD_LOGIC_VECTOR(4 downto 0) := "10011";    -- extend sign
1215
constant NEG_A: STD_LOGIC_VECTOR(4 downto 0) := "10100";    -- negate
1216
 
1217
-- PCR microcode
1218
constant NOP_PC: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PC no operation
1219
constant LSB_PC: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PC load lsb
1220
constant MSB_PC: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- PC load msb
1221
constant INC_PC: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- PC increment by 1
1222
constant LOD_PC: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- PC load lsb\msb  (used by JMP\JSR instructions)
1223
constant LML_PC: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- PC load lsb\msb from oper register (used for JML\JSL instructions)
1224
constant IN2_PC: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- PC = PC +2 (BRK opcode)
1225
constant DE3_PC: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- PC = PC -3 (MVN/MVP opcodes)
1226
constant BRA_PC: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- PC branch
1227
constant BRL_PC: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- PC branch long 
1228
 
1229
-- MPR (memory data pointer) microcode
1230
constant NOP_M: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation
1231
constant LSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- load lsb
1232
constant MSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- load msb
1233
constant INC_M: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- increment 
1234
constant DEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- decrement
1235
constant VEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- load vector
1236
constant ZPL_M: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- load ZEROPAGE
1237
constant ALL_M: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- load all 16 bit register
1238
constant ICC_M: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- increment MSB with carry
1239
constant DOX_M: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- add D + offset + X
1240
constant DOY_M: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- add D + offset + Y
1241
constant AOS_M: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- add S + offset
1242
constant ABX_M: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- add opr+X
1243
constant ABY_M: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- add opr+Y
1244
constant ADX_M: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- add X
1245
constant ADY_M: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- add Y
1246
constant MHB_M: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- load high byte 
1247
constant AOY_M: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- add opr+Y and concatenates SBR
1248
 
1249
-- address multiplexer microcode
1250
constant ADPC: STD_LOGIC_VECTOR(2 downto 0) := "000";  -- select PC
1251
constant ADMP: STD_LOGIC_VECTOR(2 downto 0) := "001";  -- select MP
1252
constant ADSP: STD_LOGIC_VECTOR(2 downto 0) := "010";  -- select SP
1253
constant ADDI: STD_LOGIC_VECTOR(2 downto 0) := "011";  -- select Direct
1254
constant ADXR: STD_LOGIC_VECTOR(2 downto 0) := "100";  -- select X register
1255
constant ADYR: STD_LOGIC_VECTOR(2 downto 0) := "101";  -- select Y register
1256
constant ADNP: STD_LOGIC_VECTOR(2 downto 0) := "000";  -- no operation (PC)
1257
 
1258
-- PR microcode
1259
constant NOP_P: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- PR no operation
1260
constant PLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- PR load
1261
constant FLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- NV load
1262
constant FLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- NZC load
1263
constant FLV_P: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- NVZC load
1264
constant SEC_P: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- 1 => C 
1265
constant CLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- 0 => C 
1266
constant SEI_P: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- 1 => I 
1267
constant CLI_P: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- 0 => I 
1268
constant SED_P: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- 1 => D 
1269
constant CLD_P: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- 0 => D 
1270
constant CLV_P: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- 0 => V 
1271
constant AUC_P: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- auc => ACR 
1272
constant HAC_P: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- hold ACR 
1273
constant SID_P: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- 1 => I/D 
1274
constant LDZ_P: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- Z load
1275
constant XCE_P: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- E => C; C => E
1276
constant SEP_P: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- P = P OR din
1277
constant REP_P: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- P = P AND not din
1278
constant WDM_P: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- 1 => op_exp;
1279
constant WDC_P: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- 0 => op_exp;
1280
constant FLW_P: STD_LOGIC_VECTOR(4 downto 0) := "10101"; -- NZ load, 0 -> op_exp
1281
constant MUF_P: STD_LOGIC_VECTOR(4 downto 0) := "10110"; -- Z load from unsigned multplier
1282
constant MSF_P: STD_LOGIC_VECTOR(4 downto 0) := "10111"; -- NZ load from unsigned multplier
1283
 
1284
-- register operation microcode REGOP (decreg)
1285
constant NOP_R: STD_LOGIC_VECTOR(5 downto 0) := "000000";  -- no operation
1286
constant ALL_R: STD_LOGIC_VECTOR(5 downto 0) := "000001";  -- register A load lsb
1287
constant ALM_R: STD_LOGIC_VECTOR(5 downto 0) := "000010";  -- register A load msb
1288
constant A16_R: STD_LOGIC_VECTOR(5 downto 0) := "000011";  -- register A load msb & lsb
1289
constant XLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000100";  -- register X load lsb
1290
constant XLM_R: STD_LOGIC_VECTOR(5 downto 0) := "000101";  -- register X load msb 
1291
constant X16_R: STD_LOGIC_VECTOR(5 downto 0) := "000110";  -- register X load msb & lsb 
1292
constant YLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000111";  -- register Y load lsb
1293
constant YLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001000";  -- register Y load msb
1294
constant Y16_R: STD_LOGIC_VECTOR(5 downto 0) := "001001";  -- register Y load msb & lsb
1295
constant DLL_R: STD_LOGIC_VECTOR(5 downto 0) := "001010";  -- register D load lsb
1296
constant DLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001011";  -- register D load msb
1297
constant D16_R: STD_LOGIC_VECTOR(5 downto 0) := "001100";  -- register D load msb & lsb
1298
constant OLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001101";  -- register O load lsb
1299
constant OMD_R: STD_LOGIC_VECTOR(5 downto 0) := "001110";  -- register O load msb
1300
constant SLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001111";  -- register S load lsb
1301
constant SLM_R: STD_LOGIC_VECTOR(5 downto 0) := "010000";  -- register S load msb
1302
constant S16_R: STD_LOGIC_VECTOR(5 downto 0) := "010001";  -- register S load msb & lsb
1303
constant SUP_R: STD_LOGIC_VECTOR(5 downto 0) := "010010";  -- register S increment by 1
1304
constant SDW_R: STD_LOGIC_VECTOR(5 downto 0) := "010011";  -- register S decrement by 1
1305
constant SAU_R: STD_LOGIC_VECTOR(5 downto 0) := "010100";  -- register A (lsb) load/register S increment by 1
1306
constant SXU_R: STD_LOGIC_VECTOR(5 downto 0) := "010101";  -- register X (lsb) load/register S increment by 1
1307
constant SXM_R: STD_LOGIC_VECTOR(5 downto 0) := "010110";  -- register X (msb) load/register S increment by 1
1308
constant SYU_R: STD_LOGIC_VECTOR(5 downto 0) := "010111";  -- register Y (lsb) load/register S increment by 1
1309
constant SYM_R: STD_LOGIC_VECTOR(5 downto 0) := "011000";  -- register Y (msb) load/register S increment by 1
1310
constant KLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011001";  -- register K (PBR) load
1311
constant BLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011010";  -- register B (DBR) load
1312
constant KCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011011";  -- register K (PBR) clear and register S decrement by 1
1313
constant BCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011100";  -- register B (DBR) clear
1314
constant SKC_R: STD_LOGIC_VECTOR(5 downto 0) := "011101";  -- register B (DBR) clear and register S decrement by 1
1315
constant DEA_R: STD_LOGIC_VECTOR(5 downto 0) := "011110";  -- register A decrement (MVN/MVP)
1316
constant O16_R: STD_LOGIC_VECTOR(5 downto 0) := "011111";  -- register O load msb & lsb
1317
constant OSU_R: STD_LOGIC_VECTOR(5 downto 0) := "100000";  -- register O load lsb/register S increment by 1
1318
constant MVN_R: STD_LOGIC_VECTOR(5 downto 0) := "100001";  -- register XY increment by 1, A decremented by 1
1319
constant MVP_R: STD_LOGIC_VECTOR(5 downto 0) := "100010";  -- register XY decrement by 1, A decremented by 1
1320
constant MUL_R: STD_LOGIC_VECTOR(5 downto 0) := "100011";  -- register A/B load multiplication lsb result, register X load multiplication msb result
1321
constant MUI_R: STD_LOGIC_VECTOR(5 downto 0) := "100100";  -- multiplication init
1322
constant MUS_R: STD_LOGIC_VECTOR(5 downto 0) := "100101";  -- multiplication (unsigned) start
1323
constant MSS_R: STD_LOGIC_VECTOR(5 downto 0) := "100110";  -- multiplication (signed) start
1324
constant WAI_R: STD_LOGIC_VECTOR(5 downto 0) := "100111";  -- WAI set flipflop
1325
constant STP_R: STD_LOGIC_VECTOR(5 downto 0) := "101000";  -- STP set flipflop
1326
constant BLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101001";  -- register B (DBR) load/register S incremented by 1
1327
constant DLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101010";  -- register D load msb & lsb/register S incremented by 1
1328
 
1329
-- register multiplexer microcode RSEL (ALU operand #1)
1330
constant EXT_O: STD_LOGIC_VECTOR(4 downto 0) := "00000";  -- external data bus
1331
constant ARD_O: STD_LOGIC_VECTOR(4 downto 0) := "00001";  -- register A msb & lsb select
1332
constant ARM_O: STD_LOGIC_VECTOR(4 downto 0) := "00010";  -- register A msb select (also returns A swapped)
1333
constant XRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00011";  -- register X msb & lsb select
1334
constant XRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00100";  -- register X msb select
1335
constant YRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00101";  -- register Y msb & lsb select
1336
constant YRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00110";  -- register Y msb select
1337
constant SRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00111";  -- register S lsb select
1338
constant PRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01000";  -- register P select
1339
constant PLR_O: STD_LOGIC_VECTOR(4 downto 0) := "01001";  -- register PCL select
1340
constant PHR_O: STD_LOGIC_VECTOR(4 downto 0) := "01010";  -- register PCH select
1341
constant ORD_O: STD_LOGIC_VECTOR(4 downto 0) := "01011";  -- register O msb & lsb select 
1342
constant Z00_O: STD_LOGIC_VECTOR(4 downto 0) := "01100";  -- select (all zero output)
1343
constant DRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01101";  -- register D msb & lsb select
1344
constant DRM_O: STD_LOGIC_VECTOR(4 downto 0) := "01110";  -- register D msb select
1345
constant KRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01111";  -- register K PBR
1346
constant BRD_O: STD_LOGIC_VECTOR(4 downto 0) := "10000";  -- register B PBR
1347
constant EXM_O: STD_LOGIC_VECTOR(4 downto 0) := "10001";  -- external data bus on MSB, O on lsb
1348
constant OMD_O: STD_LOGIC_VECTOR(4 downto 0) := "10010";  -- register O msb select 
1349
constant PCR_O: STD_LOGIC_VECTOR(4 downto 0) := "10011";  -- register PC (16 bit) select
1350
 
1351
-- data multiplexer microcode DMUX (ALU operand #2)
1352
constant NOP_D: STD_LOGIC_VECTOR(2 downto 0) := "000";
1353
constant ORD_D: STD_LOGIC_VECTOR(2 downto 0) := "001";
1354
constant EXT_D: STD_LOGIC_VECTOR(2 downto 0) := "010";
1355
constant EXM_D: STD_LOGIC_VECTOR(2 downto 0) := "011";
1356
constant BCD_D: STD_LOGIC_VECTOR(2 downto 0) := "100";
1357
 
1358
-- read/write control
1359
constant   RDE: STD_LOGIC_VECTOR(1 downto 0) := "11";    -- data bus read
1360
constant   WRE: STD_LOGIC_VECTOR(1 downto 0) := "10";    -- data bus write (combinatorial mode)
1361
constant   WRL: STD_LOGIC_VECTOR(1 downto 0) := "01";    -- data bus write (registered mode)
1362
 
1363
begin
1364
  process(em,m,x,a)
1365
  begin
1366
         -----------------------------------
1367
         --          NATIVE MODE          --
1368
         -----------------------------------
1369
    if em = '0' then
1370
          -- The PLA is arranged like an ROM, there are an address input "a" and an data output "q". The address of PLA is 13 bit wide 
1371
          -- and composed in this way:
1372
          --
1373
          --  W  ----  CPU OPCODE   ---- --- MPC --
1374
          --  |  |                     | |        |  
1375
          --  |  |                     | |        |  
1376
          --  W  X--X--X--X--X--X--X--X--Y--Y--Y--Y 
1377
          -- 12-11-10-09-08-07-06-05-04-03-02-01-00
1378
          --
1379
          -- the bit (12) W is the two byte instruction bit
1380
          -- the bits (11-4) (X field) is formed by CPU instruction opcode 
1381
          -- the bits (3-0) (Y field) is formed by the three bit wide microinstruction program counter (MPC)  
1382
          -- The MPC field is cleared at each opcode fetch by FSM and since it's three bit wide there are
1383
          -- an maximum of eight microinstructions available per opcode 
1384
          --
1385
          -- The bits 10-3 of PLA address serves to select the microcode group of a related CPU opcode 
1386
          -- and they are stable for all instruction execution time, instead the remaining three bit 2-0 (MPC field) of PLA address 
1387
          -- increment at each clock in order to address the next microcode instructions.   
1388
          -- microcode assembly:
1389
          -- Due the particulary pipeline structure of this CPU, all microinstructions have an extra cycle hidden on fetch 
1390
          -- of the next opcode instruction and normally this extra cycle is coded as "NOP" (see the last line  "when  others =>...").
1391
          -- However there are some instructions where this extra cycle is used for some functions like decimal adjustments etc of
1392
          -- ADC and SBC instructions (see DAA and DAS).
1393
          --
1394
          -- Microcode fields:
1395
          --     
1396
          --                          DMUX: ALU operand #2 multiplexer
1397
          --                          |       AI: effective address is indexed (X or Y)
1398
          --                          |       |   VP: vector pull
1399
          --                          |       |   |   ML: memory lock            
1400
          --                          |       |   |   |   VPA: valid program address 
1401
          --                          |       |   |   |   |   VDA: valid data address 
1402
          --                          |       |   |   |   |   |   EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction) 
1403
          --                          |       |   |   |   |   |   |   W: read/write control
1404
          --                          |       |   |   |   |   |   |   |    CLI: clear interrupt request
1405
          --                          |       |   |   |   |   |   |   |    |    PD: PC/MP address output multiplexer select
1406
          --                          |       |   |   |   |   |   |   |    |    |      PCR: register PC (program counter)
1407
          --                          |       |   |   |   |   |   |   |    |    |      |        MPR: register MP (memory pointer)
1408
          --                          |       |   |   |   |   |   |   |    |    |      |        |       P_OP: register P set/reset bit
1409
          --                          |       |   |   |   |   |   |   |    |    |      |        |       |       ALUOP: ALU operation
1410
          --                          |       |   |   |   |   |   |   |    |    |      |        |       |       |       REGOP: registers load/increment/decrement etc.
1411
          --                          |       |   |   |   |   |   |   |    |    |      |        |       |       |       |       RSEL: registers output multiplexer select
1412
          --                          |       |   |   |   |   |   |   |    |    |      |        |       |       |       |       |
1413
          --                          |       |   |   |   |   |   |   |    |    |      |        |       |       |       |       |
1414
                 case a is              -- DMUX    AI  VP  ML VPA VDA  EI  W    CLI  PD     PCR      MPR     P_OP    ALUOP   REGOP   RSEL
1415
                        ------------------------------------
1416
                        --            IMPLIED             --
1417
                        ------------------------------------
1418
                        -- BRK
1419
                        when    BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- if no interrupt request then PC=PC+2 
1420
                        when    BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1 
1421
                        when    BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 
1422
                        when    BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 
1423
                        when    BRK_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & KCL_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD
1424
                        when    BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP
1425
                        when    BRK_OP6 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP 
1426
 
1427
                        -- COP
1428
                        when    COP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- if no interrupt request then PC=PC+2 
1429
                        when    COP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1 
1430
                        when    COP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 
1431
                        when    COP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 
1432
                        when    COP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & KCL_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD
1433
                        when    COP_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP
1434
                        when    COP_OP6 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP 
1435
 
1436
                        -- NOP
1437
                   when    NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI
1438
 
1439
                        -- CLC
1440
                        when    CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI
1441
 
1442
                        -- SEC
1443
                        when    SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI
1444
 
1445
                        -- CLI
1446
                        when    CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI
1447
 
1448
                        -- SEI
1449
                        when    SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI
1450
 
1451
                        -- CLV
1452
                        when    CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI
1453
 
1454
                        -- CLD
1455
                        when    CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI
1456
 
1457
                        -- SED
1458
                        when    SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI
1459
 
1460
                        -- TAX
1461
                        when    TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & ARD_O; -- A->X; EI
1462
 
1463
                        -- TXA
1464