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[/] [v65c816/] [trunk/] [regmux.vhd] - Blame information for rev 2

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1 2 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8 bit seven-way multiplexer
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entity regmux is
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  port(  sel:  in STD_LOGIC_VECTOR(4 downto 0);
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           a:  in STD_LOGIC_VECTOR(7 downto 0);
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           b:  in STD_LOGIC_VECTOR(15 downto 0);
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           c:  in STD_LOGIC_VECTOR(15 downto 0);
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           d:  in STD_LOGIC_VECTOR(15 downto 0);
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           e:  in STD_LOGIC_VECTOR(15 downto 0);
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           g:  in STD_LOGIC_VECTOR(7 downto 0);
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           h:  in STD_LOGIC_VECTOR(7 downto 0);
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           i:  in STD_LOGIC_VECTOR(7 downto 0);
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           j:  in STD_LOGIC_VECTOR(15 downto 0);
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           k:  in STD_LOGIC_VECTOR(15 downto 0);
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                          l:  in STD_LOGIC_VECTOR(7 downto 0);
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                          m:  in STD_LOGIC_VECTOR(7 downto 0);
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           y: out STD_LOGIC_VECTOR(15 downto 0)
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      );
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end regmux;
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architecture comb of regmux is
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constant EXT_O: STD_LOGIC_VECTOR(4 downto 0) := "00000";  -- external data bus
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constant ARD_O: STD_LOGIC_VECTOR(4 downto 0) := "00001";  -- register C msb & lsb select
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constant ARM_O: STD_LOGIC_VECTOR(4 downto 0) := "00010";  -- register C msb select (also returns C swapped)
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constant XRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00011";  -- register X msb & lsb select
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constant XRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00100";  -- register X msb select
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constant YRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00101";  -- register Y msb & lsb select
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constant YRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00110";  -- register Y msb select
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constant SRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00111";  -- register S lsb select
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constant PRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01000";  -- register P select
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constant PLR_O: STD_LOGIC_VECTOR(4 downto 0) := "01001";  -- register PCL select
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constant PHR_O: STD_LOGIC_VECTOR(4 downto 0) := "01010";  -- register PCH select
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constant ORD_O: STD_LOGIC_VECTOR(4 downto 0) := "01011";  -- register O msb & lsb select 
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constant Z00_O: STD_LOGIC_VECTOR(4 downto 0) := "01100";  -- select (all zero output)
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constant DRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01101";  -- register D msb & lsb select
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constant DRM_O: STD_LOGIC_VECTOR(4 downto 0) := "01110";  -- register D msb select
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constant KRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01111";  -- register K PBR
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constant BRD_O: STD_LOGIC_VECTOR(4 downto 0) := "10000";  -- register B PBR
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constant EXM_O: STD_LOGIC_VECTOR(4 downto 0) := "10001";  -- external data bus on MSB, O on lsb
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constant OMD_O: STD_LOGIC_VECTOR(4 downto 0) := "10010";  -- register O msb select 
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constant PCR_O: STD_LOGIC_VECTOR(4 downto 0) := "10011";  -- register PC (16 bit) select
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begin
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  process(sel,a,b,c,d,e,g,h,i,j,k,l,m)
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  begin
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    case sel is
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      when EXT_O  => y(7 downto 0) <= a;
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                               y(15 downto 8) <= (others => '0');
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      when EXM_O  => y(15 downto 8) <= a;
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                               y(7 downto 0) <= j(7 downto 0);
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      when ARD_O  => y <= b;
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                when ARM_O  => y(7 downto 0) <= b(15 downto 8);
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                               y(15 downto 8) <= b(7 downto 0);
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      when XRD_O  => y <= c;
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                when XRM_O  => y(7 downto 0) <= c(15 downto 8);
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                               y(15 downto 8) <= (others => '0');
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      when YRD_O  => y <= d;
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                when YRM_O  => y(7 downto 0) <= d(15 downto 8);
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                               y(15 downto 8) <= (others => '0');
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      when SRD_O  => y <= e;
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      when PRD_O  => y(7 downto 0) <= g;
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                               y(15 downto 8) <= (others => '0');
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      when PLR_O  => y(7 downto 0) <= h;
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                               y(15 downto 8) <= (others => '0');
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      when PHR_O  => y(7 downto 0) <= i;
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                               y(15 downto 8) <= (others => '0');
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      when ORD_O  => y <= j;
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      when Z00_O  => y <= (others => '0');
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      when DRD_O  => y <= k;
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                when DRM_O  => y(7 downto 0) <= k(15 downto 8);
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                               y(15 downto 8) <= (others => '0');
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      when KRD_O  => y(7 downto 0) <= l;
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                               y(15 downto 8) <= (others => '0');
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      when BRD_O  => y(7 downto 0) <= m;
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                               y(15 downto 8) <= (others => '0');
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      when OMD_O  => y(7 downto 0) <= j(15 downto 8);
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                               y(15 downto 8) <= (others => '0');
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                when PCR_O  => y(7 downto 0) <= h;
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                               y(15 downto 8) <= i;
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      when others => y(7 downto 0) <= a;
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                               y(15 downto 8) <= (others => '0');
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    end case;
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  end process;
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end comb;
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