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[/] [v65c816/] [trunk/] [v65c816_bench.vhd] - Blame information for rev 4

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---------------------------------------------------------------------------------------
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-- CN3 glue logic                                                                    -- 
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-- autoinitializing logic                                                            -- 
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-- full synchronous logic design                                                     --                                                    
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-- full VHDL-RTL style coding design                                                 --
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-- target: ALTERA CPLD MAX II EPM570F256C5                                           --
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-- project by Valerio Venturi ELMA Riva del Garda (TN) Italy (2009)                  --
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-- Date: 16/10/2009                                                                  --
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---------------------------------------------------------------------------------------
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11
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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14
-- global architecture 
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entity v65c816_bench is
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end v65c816_bench;
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use work.v65c816;
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20
architecture behavior of v65c816_bench is
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  component v65c816 is
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          port(     clk0:    in STD_LOGIC;                       -- PHASE0 clock input
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                                         res:    in STD_LOGIC;                       -- reset input
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                                         irq:    in STD_LOGIC;                       -- interrupt request input
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                                         nmi:    in STD_LOGIC;                       -- not maskable interrupt input
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                                         rdy:    in STD_LOGIC;                       -- wait state input (read/write)
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                                          rw:   out STD_LOGIC;                       -- read/write out
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                                         vpa:   out STD_LOGIC;                       -- vpa
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                                         vda:   out STD_LOGIC;                       -- vda
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                                          vp:   out STD_LOGIC;                       -- vector pull
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                                         ope:   out STD_LOGIC;                       -- microcode end 
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                                                e:   out STD_LOGIC;                       -- emulation (1)/native mode (0) 
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                                                m:   out STD_LOGIC;                       -- M status   
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                                                x:   out STD_LOGIC;                       -- X status   
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                                 op_exp:   out STD_LOGIC;                                 -- two byte instruction running
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                                        addr:   out STD_LOGIC_VECTOR(23 downto 0);   -- 16 bit address bus out
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                                data_in:    in STD_LOGIC_VECTOR(7 downto 0);    -- 8 bit input data bus
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                          data_out:   out STD_LOGIC_VECTOR(7 downto 0);    -- 8 bit output data bus
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                                  a_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit A register
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                                  x_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit X register
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                                  y_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Y register
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                                  s_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit S register
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                                 op_reg:   out STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Operand register         
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                                  p_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit P register
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                                  k_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit K register
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                                  b_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit B register
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                                  o_reg:   out STD_LOGIC_VECTOR(7 downto 0);    --  8 bit Opcode register
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                                  mcode:   out STD_LOGIC_VECTOR(3 downto 0)     --  4 bit microcode sequence register
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                        );
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  end component;
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  signal clk0,res,irq,nmi,rdy,rw,vpa,vda,vp,ope,e,m,x,op_exp:             STD_LOGIC;
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  signal addr:                                                            STD_LOGIC_VECTOR(23 downto 0);
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  signal data_in:                                                         STD_LOGIC_VECTOR(7 downto 0);
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  signal data_out:                                                        STD_LOGIC_VECTOR(7 downto 0);
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  signal a_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit A register
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  signal x_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit X register
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  signal y_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Y register
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  signal s_reg:                                                           STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit S register
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  signal op_reg:                                                          STD_LOGIC_VECTOR(15 downto 0);   -- 16 bit Operand register      
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  signal p_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit P register
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  signal k_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit K register
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  signal b_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit B register
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  signal o_reg:                                                           STD_LOGIC_VECTOR(7 downto 0);    --  8 bit Opcode register
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  signal mcode:                                                           STD_LOGIC_VECTOR(3 downto 0);    --  4 bit microcode sequence register
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  constant clk_period: time := 50 ns;
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  --signal clock: STD_LOGIC := '0';
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  begin
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  u1:   v65c816 port map(
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                         clk0,
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                                                                 res,
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                                                                 irq,
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                                                                 nmi,
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                                                                 rdy,
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                                                                 rw,
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                                                                 vpa,
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                                                                 vda,
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                                                                 vp,
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                                                                 ope,
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                                                                 e,
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                                                                 m,
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                                                                 x,
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                                                                 op_exp,
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                         addr,
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                                                                 data_in,
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                                                                 data_out,
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                         a_reg,
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                                             x_reg,
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                                             y_reg,
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                                             s_reg,
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                                             op_reg,
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                                             p_reg,
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                                             k_reg,
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                                             b_reg,
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                                             o_reg,
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                                             mcode
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                                                 );
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101
 
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  tst_clock: process                                       -- 10 MHZ (period 100 ns) clock generation
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             variable clktmp: STD_LOGIC := '0';
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             begin
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               clktmp := not clktmp;
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               clk0 <= clktmp;
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             wait for 50 ns;
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             end process;
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  stimulus:  process
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             begin
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               -- signal initialization before reset
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               res <= '0';
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                              irq <= '1';
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                              nmi <= '1';
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                              rdy <= '1';
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               wait for 350 ns;
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               -- device reset completed
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               res <= '1';
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               wait for 600 ns;
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               data_in <= "00000000";                      -- fetch lsb reset PC vector 0x00
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11000001";                      -- fetch msb reset PC vector 0xc1 (0xc100)
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               wait for 70 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00011000";                      -- CLC
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11111011";                      -- XCE
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";                      -- XCE execution
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11000010";                      -- REP #%00100000
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00100000";                      -- $20
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "10101001";                      -- LDA #$0000
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000000";                      -- $00
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000000";                      -- $00
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00011000";                      -- CLC
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "01101001";                      -- ADC #$0001
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000001";                      -- $01
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000000";                      -- $00
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00111000";                      -- SEC
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101001";                      -- SBC #0002
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000010";                      -- $02
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "00000000";                      -- $00
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               data_in <= "ZZZZZZZZ";
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               wait for 50 ns;
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               data_in <= "11101010";                      -- NOP
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               wait for 50 ns;
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               data_in <= "ZZZZZZZZ";
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               --wait for 1000000 ns;
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               wait;
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            end process;
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end behavior;
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