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[/] [vspi/] [trunk/] [projnav/] [xps/] [drivers/] [spiifc_v1_00_a/] [src/] [spiifc.h] - Blame information for rev 14

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1 14 mjlyons
/*****************************************************************************
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* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.h
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* Version:           1.00.a
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* Description:       spiifc Driver Header File
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* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
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*****************************************************************************/
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#ifndef SPIIFC_H
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#define SPIIFC_H
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/***************************** Include Files *******************************/
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#include "xbasic_types.h"
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#include "xstatus.h"
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#include "xil_io.h"
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/************************** Constant Definitions ***************************/
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/**
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 * User Logic Slave Space Offsets
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 * -- SLV_REG0 : user logic slave module register 0
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 * -- SLV_REG1 : user logic slave module register 1
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 * -- SLV_REG2 : user logic slave module register 2
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 * -- SLV_REG3 : user logic slave module register 3
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 * -- SLV_REG4 : user logic slave module register 4
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 * -- SLV_REG5 : user logic slave module register 5
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 * -- SLV_REG6 : user logic slave module register 6
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 * -- SLV_REG7 : user logic slave module register 7
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 * -- SLV_REG8 : user logic slave module register 8
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 * -- SLV_REG9 : user logic slave module register 9
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 * -- SLV_REG10 : user logic slave module register 10
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 * -- SLV_REG11 : user logic slave module register 11
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 * -- SLV_REG12 : user logic slave module register 12
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 * -- SLV_REG13 : user logic slave module register 13
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 * -- SLV_REG14 : user logic slave module register 14
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 * -- SLV_REG15 : user logic slave module register 15
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 */
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#define SPIIFC_USER_SLV_SPACE_OFFSET (0x00000000)
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#define SPIIFC_SLV_REG0_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000000)
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#define SPIIFC_SLV_REG1_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000004)
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#define SPIIFC_SLV_REG2_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000008)
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#define SPIIFC_SLV_REG3_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000000C)
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#define SPIIFC_SLV_REG4_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000010)
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#define SPIIFC_SLV_REG5_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000014)
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#define SPIIFC_SLV_REG6_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000018)
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#define SPIIFC_SLV_REG7_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000001C)
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#define SPIIFC_SLV_REG8_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000020)
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#define SPIIFC_SLV_REG9_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000024)
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#define SPIIFC_SLV_REG10_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000028)
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#define SPIIFC_SLV_REG11_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000002C)
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#define SPIIFC_SLV_REG12_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000030)
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#define SPIIFC_SLV_REG13_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000034)
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#define SPIIFC_SLV_REG14_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000038)
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#define SPIIFC_SLV_REG15_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000003C)
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/**
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 * Interrupt Controller Space Offsets
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 * -- INTR_DGIER : device (peripheral) global interrupt enable register
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 * -- INTR_ISR   : ip (user logic) interrupt status register
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 * -- INTR_IER   : ip (user logic) interrupt enable register
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 */
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#define SPIIFC_INTR_CNTRL_SPACE_OFFSET (0x00000100)
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#define SPIIFC_INTR_DGIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x0000001C)
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#define SPIIFC_INTR_IPISR_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000020)
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#define SPIIFC_INTR_IPIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000028)
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/**
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 * Interrupt Controller Masks
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 * -- INTR_TERR_MASK : transaction error
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 * -- INTR_DPTO_MASK : data phase time-out
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 * -- INTR_IPIR_MASK : ip interrupt requeset
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 * -- INTR_RFDL_MASK : read packet fifo deadlock interrupt request
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 * -- INTR_WFDL_MASK : write packet fifo deadlock interrupt request
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 * -- INTR_IID_MASK  : interrupt id
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 * -- INTR_GIE_MASK  : global interrupt enable
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 * -- INTR_NOPEND    : the DIPR has no pending interrupts
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 */
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#define INTR_TERR_MASK (0x00000001UL)
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#define INTR_DPTO_MASK (0x00000002UL)
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#define INTR_IPIR_MASK (0x00000004UL)
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#define INTR_RFDL_MASK (0x00000020UL)
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#define INTR_WFDL_MASK (0x00000040UL)
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#define INTR_IID_MASK (0x000000FFUL)
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#define INTR_GIE_MASK (0x80000000UL)
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#define INTR_NOPEND (0x80)
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/**************************** Type Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *******************/
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/**
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 *
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 * Write a value to a SPIIFC register. A 32 bit write is performed.
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 * If the component is implemented in a smaller width, only the least
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 * significant data is written.
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 *
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 * @param   BaseAddress is the base address of the SPIIFC device.
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 * @param   RegOffset is the register offset from the base to write to.
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 * @param   Data is the data written to the register.
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 *
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 * @return  None.
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 *
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 * @note
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 * C-style signature:
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 *      void SPIIFC_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
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 *
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 */
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#define SPIIFC_mWriteReg(BaseAddress, RegOffset, Data) \
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        Xil_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
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/**
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 *
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 * Read a value from a SPIIFC register. A 32 bit read is performed.
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 * If the component is implemented in a smaller width, only the least
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 * significant data is read from the register. The most significant data
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 * will be read as 0.
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 *
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 * @param   BaseAddress is the base address of the SPIIFC device.
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 * @param   RegOffset is the register offset from the base to write to.
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 *
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 * @return  Data is the data from the register.
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 *
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 * @note
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 * C-style signature:
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 *      Xuint32 SPIIFC_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
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 *
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 */
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#define SPIIFC_mReadReg(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (RegOffset))
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/**
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 *
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 * Write/Read 32 bit value to/from SPIIFC user logic slave registers.
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 *
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 * @param   BaseAddress is the base address of the SPIIFC device.
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 * @param   RegOffset is the offset from the slave register to write to or read from.
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 * @param   Value is the data written to the register.
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 *
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 * @return  Data is the data from the user logic slave register.
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 *
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 * @note
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 * C-style signature:
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 *      void SPIIFC_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value)
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 *      Xuint32 SPIIFC_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset)
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 *
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 */
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#define SPIIFC_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg5(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg6(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg7(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg8(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg9(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg10(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg11(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg12(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg13(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg14(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mWriteSlaveReg15(BaseAddress, RegOffset, Value) \
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        Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset), (Xuint32)(Value))
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#define SPIIFC_mReadSlaveReg0(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg1(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg2(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg3(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg4(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg5(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg6(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg7(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg8(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg9(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg10(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg11(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg12(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg13(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg14(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset))
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#define SPIIFC_mReadSlaveReg15(BaseAddress, RegOffset) \
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        Xil_In32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset))
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/**
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 *
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 * Write/Read 32 bit value to/from SPIIFC user logic memory (BRAM).
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 *
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 * @param   Address is the memory address of the SPIIFC device.
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 * @param   Data is the value written to user logic memory.
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 *
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 * @return  The data from the user logic memory.
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 *
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 * @note
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 * C-style signature:
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 *      void SPIIFC_mWriteMemory(Xuint32 Address, Xuint32 Data)
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 *      Xuint32 SPIIFC_mReadMemory(Xuint32 Address)
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 *
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 */
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#define SPIIFC_mWriteMemory(Address, Data) \
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        Xil_Out32(Address, (Xuint32)(Data))
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#define SPIIFC_mReadMemory(Address) \
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        Xil_In32(Address)
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/************************** Function Prototypes ****************************/
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/**
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 *
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 * Enable all possible interrupts from SPIIFC device.
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 *
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 * @param   baseaddr_p is the base address of the SPIIFC device.
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 *
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 * @return  None.
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 *
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 * @note    None.
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 *
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 */
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void SPIIFC_EnableInterrupt(void * baseaddr_p);
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/**
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 *
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 * Example interrupt controller handler.
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 *
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 * @param   baseaddr_p is the base address of the SPIIFC device.
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 *
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 * @return  None.
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 *
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 * @note    None.
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 *
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 */
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void SPIIFC_Intr_DefaultHandler(void * baseaddr_p);
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/**
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 *
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 * Run a self-test on the driver/device. Note this may be a destructive test if
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 * resets of the device are performed.
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 *
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 * If the hardware system is not built correctly, this function may never
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 * return to the caller.
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 *
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 * @param   baseaddr_p is the base address of the SPIIFC instance to be worked on.
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 *
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 * @return
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 *
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 *    - XST_SUCCESS   if all self-test code passed
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 *    - XST_FAILURE   if any self-test code failed
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 *
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 * @note    Caching must be turned off for this function to work.
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 * @note    Self test may fail if data memory and device are not on the same bus.
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 *
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 */
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XStatus SPIIFC_SelfTest(void * baseaddr_p);
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#endif /** SPIIFC_H */

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